Report: Add 3n-tsh

[csit.git] / docs / report / vpp_performance_tests / packet_latency_graphs / ip4.rst

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst
index 78d258c..23c19de 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst
@@ -13,13 +13,13 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
 physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in
 physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in

-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4?h=rls1810>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4?h=rls1908>`_.

 
 .. toctree::
 
 
 .. toctree::
 

-    ip4-3n-hsw-x520
-    ip4-3n-hsw-x710
-    ip4-3n-hsw-xl710
-    ip4-3n-skx-x710
-    ip4-2n-skx-x710

     ip4-2n-skx-xxv710
     ip4-2n-skx-xxv710

+    ip4-2n-skx-x710
+    ip4-3n-skx-xxv710
+    ip4-3n-skx-x710
+    ip4-3n-hsw-xl710
+    ip4-3n-tsh-x520