Report: Add 2n-clx

[csit.git] / docs / report / vpp_performance_tests / packet_latency_graphs / ip4_tunnels.rst

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
index cc3d5e3..6ff5d67 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
@@ -13,7 +13,7 @@ thread(s), a.k.a. VPP data plane thread(s), and their physical CPU core(s)
 placement.
 
 CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls1908>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls2001>`_.
 
 .. toctree::