Report: Configure 1901.2

[csit.git] / docs / report / vpp_performance_tests / packet_latency_graphs / ip4_tunnels.rst

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
index dade32a..fffea0f 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
@@ -13,10 +13,12 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
 physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls1810>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls1901>`_.
 
 .. toctree::
 
+    ip4_tunnels-3n-skx-x710
+
+..
     ip4_tunnels-3n-hsw-x520
     ip4_tunnels-3n-hsw-x710
-    ip4_tunnels-3n-skx-x710