CSIT-1489: Change graphs to display results by suite generator

[csit.git] / docs / report / vpp_performance_tests / packet_latency_graphs / ip6.rst

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
index 4f79f35..c0de92f 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
@@ -13,7 +13,7 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
 physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6?h=rls1810>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6?h=rls1901>`_.
 
 .. toctree::
 
@@ -21,5 +21,6 @@ CSIT source code for the test cases used for plots can be found in
     ip6-3n-hsw-x710
     ip6-3n-hsw-xl710
     ip6-3n-skx-x710
+    ip6-3n-skx-xxv710
     ip6-2n-skx-x710
     ip6-2n-skx-xxv710