Report: Configure 1908.1.39

[csit.git] / docs / report / vpp_performance_tests / packet_latency_graphs / ip6.rst

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
index 3080d8f..ce9ce88 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
@@ -13,13 +13,15 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
 physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in
 physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in

-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6?h=rls1901>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6?h=rls1908>`_.

 
 .. toctree::
 
 
 .. toctree::
 

-    ip6-3n-hsw-x520
-    ip6-3n-hsw-x710
-    ip6-3n-hsw-xl710
-    ip6-3n-skx-x710
-    ip6-2n-skx-x710

     ip6-2n-skx-xxv710
     ip6-2n-skx-xxv710

+    ip6-2n-skx-x710
+    ip6-3n-skx-xxv710
+    ip6-3n-skx-x710
+    ip6-3n-hsw-xl710
+
+..
+    ip6-3n-tsh-x520