csit rls1704 report: final update to csit_release_notes.rst, packet_*_graphs.rst...

[csit.git] / docs / report / vpp_performance_tests / packet_latency_graphs / ipv4.rst

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ipv4.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ipv4.rst
index fb85fe9..5ddf813 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ipv4.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ipv4.rst
@@ -27,7 +27,7 @@ ii) East-to-West: TGint2-to-SUT2-to-SUT1-to-TGint1.
     `csit-vpp-perf-1704-all
     <https://jenkins.fd.io/view/csit/job/csit-vpp-perf-1704-all/>`_,
     with Robot Framework result files csit-vpp-perf-1704-all-<id>.zip
-    `archived here <../../_static/archive/>`_
+    `archived here <../../_static/archive/>`_.
 
 VPP packet latency in 1t1c setup (1thread, 1core) is presented in the graph below.