Report: Add 2n-clx

[csit.git] / docs / report / vpp_performance_tests / packet_latency_graphs / l2.rst

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
index 9643740..b1a87de 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
@@ -13,7 +13,7 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
 physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in
 physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in

-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls1908>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls2001>`_.

 
 .. toctree::
 
 
 .. toctree::
 


@@ -21,5 +21,7 @@ CSIT source code for the test cases used for plots can be found in
     l2-2n-skx-x710
     l2-3n-skx-xxv710
     l2-3n-skx-x710
     l2-2n-skx-x710
     l2-3n-skx-xxv710
     l2-3n-skx-x710

+    l2-2n-clx-xxv710
+    l2-2n-clx-x710

     l2-3n-hsw-xl710
     l2-3n-tsh-x520
     l2-3n-hsw-xl710
     l2-3n-tsh-x520