Report: Add 2n-clx latency 1

[csit.git] / docs / report / vpp_performance_tests / throughput_speedup_multi_core / container_memif.rst

diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/container_memif.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/container_memif.rst
index 2713cc6..4574ca5 100644 (file)
--- a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/container_memif.rst
+++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/container_memif.rst
@@ -15,15 +15,14 @@ running in multiple configurations of VPP worker thread(s), a.k.a. VPP
 data plane thread(s), and their physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls1901>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls2001>`_.
 
 .. toctree::
 
-    container_memif-3n-hsw-x520
-    container_memif-3n-hsw-x710
-    container_memif-3n-hsw-xl710
-    container_memif-3n-skx-x710
-    container_memif-2n-skx-x710
+    container_memif-3n-tsh-x520
+    container_memif-2n-clx-xxv710
+    container_memif-2n-clx-cx556a
 
 ..
     container_memif-2n-skx-xxv710
+    container_memif-3n-skx-xxv710