C-Docs: New structure

[csit.git] / docs / report / vpp_performance_tests / throughput_speedup_multi_core / ip4_tunnels.rst

diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst
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-
-.. raw:: latex
-
-    \clearpage
-
-IPv4 Tunnels
-============
-
-Following sections include Throughput Speedup Analysis for VPP multi-
-core multi-thread configurations with no Hyper-Threading, specifically
-for tested 2t2c (2threads, 2cores) and 4t4c scenarios. 1t1c throughput
-results are used as a reference for reported speedup ratio.
-Performance is reported for VPP
-running in multiple configurations of VPP worker thread(s), a.k.a. VPP
-data plane thread(s), and their physical CPU core(s) placement.
-
-CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls2302>`_.
-
-.. toctree::
-
-    ip4_tunnels-2n-icx-xxv710
-    ip4_tunnels-2n-icx-e810cq
-    ip4_tunnels-3n-icx-xxv710
-    ip4_tunnels-3n-icx-e810cq
-    ip4_tunnels-3n-icx-e810xxv
-    ip4_tunnels-2n-clx-xxv710
-    ip4_tunnels-2n-zn2-xxv710
-    ip4_tunnels-3n-alt-xl710
-    ip4_tunnels-3n-tsh-x520
-    ip4_tunnels-3n-snr-e822cq