Report: Add 3n-icx-e810xxv gtpu tests

[csit.git] / docs / report / vpp_performance_tests / throughput_speedup_multi_core / ip4_tunnels.rst

diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst
index eab4312..c066950 100644 (file)
--- a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst
+++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst
@@ -15,11 +15,17 @@ running in multiple configurations of VPP worker thread(s), a.k.a. VPP
 data plane thread(s), and their physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls1908>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls2206>`_.
 
 .. toctree::
 
+    ip4_tunnels-2n-icx-xxv710
+    ip4_tunnels-3n-icx-xxv710
+    ip4_tunnels-3n-icx-e810xxv
+    ip4_tunnels-2n-skx-xxv710
+    ip4_tunnels-2n-clx-xxv710
+    ip4_tunnels-2n-zn2-xxv710
     ip4_tunnels-3n-skx-xxv710
-    ip4_tunnels-3n-hsw-xl710
+    ip4_tunnels-3n-alt-xl710
     ip4_tunnels-3n-tsh-x520
     ip4_tunnels-3n-dnv-x553