feat(docs): Add SPR

[csit.git] / fdio.infra.ansible / inventories / lf_inventory / host_vars / 10.32.8.19.yaml

diff --git a/fdio.infra.ansible/inventories/lf_inventory/host_vars/10.32.8.19.yaml b/fdio.infra.ansible/inventories/lf_inventory/host_vars/10.32.8.19.yaml
index 5c1a85d..22210ae 100644 (file)
--- a/fdio.infra.ansible/inventories/lf_inventory/host_vars/10.32.8.19.yaml
+++ b/fdio.infra.ansible/inventories/lf_inventory/host_vars/10.32.8.19.yaml
@@ -31,4 +31,4 @@ cpu_microarchitecture: "cascadelake"
 
 intel_700_matrix: "dpdk22.07"
 intel_800_matrix: "dpdk22.07"
-mellanox_cx5_matrix: "dpdk22.07"
+mellanox_matrix: "dpdk22.07"