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feat(docs): Add SPR
[csit.git] / fdio.infra.ansible / inventories / lf_inventory / host_vars / 10.32.8.22.yaml
diff --git a/fdio.infra.ansible/inventories/lf_inventory/host_vars/10.32.8.22.yaml b/fdio.infra.ansible/inventories/lf_inventory/host_vars/10.32.8.22.yaml
index 2b6c4e1..e59d654 100644 (file)
--- a/fdio.infra.ansible/inventories/lf_inventory/host_vars/10.32.8.22.yaml
+++ b/fdio.infra.ansible/inventories/lf_inventory/host_vars/10.32.8.22.yaml
@@ -31,4 +31,4 @@ cpu_microarchitecture: "cascadelake"
 
 intel_700_matrix: "dpdk22.07"
 intel_800_matrix: "dpdk22.07"
-mellanox_cx5_matrix: "dpdk22.07"
\ No newline at end of file
+mellanox_matrix: "dpdk22.07"
\ No newline at end of file
Integration tests