X-Git-Url: https://gerrit.fd.io/r/gitweb?p=csit.git;a=blobdiff_plain;f=docs%2Freport%2Fintroduction%2Fmethodology_multi_core_speedup.rst;h=05307549f40f90a3d75fee4e16a6b3519d88a751;hp=b42bf42f9202eeae64602f980f1f4e21705ca08e;hb=83d6c91ed14a474f3c3bfdd0b7366e772fdd13d5;hpb=bbfcee8d3cf51ec01d269245970ef41bb072c580

diff --git a/docs/report/introduction/methodology_multi_core_speedup.rst b/docs/report/introduction/methodology_multi_core_speedup.rst
index b42bf42f92..05307549f4 100644
--- a/docs/report/introduction/methodology_multi_core_speedup.rst
+++ b/docs/report/introduction/methodology_multi_core_speedup.rst
@@ -1,7 +1,7 @@
 Multi-Core Speedup
 ------------------
 
-All performance tests are executed with single processor core and with
+All performance tests are executed with single physical core and with
 multiple cores scenarios.
 
 Intel Hyper-Threading (HT)
@@ -14,9 +14,8 @@ applied in BIOS and requires server SUT reload for it to take effect,
 making it impractical for continuous changes of HT mode of operation.
 
 |csit-release| performance tests are executed with server SUTs' Intel
-XEON processors configured with Intel Hyper-Threading Disabled for all
-Xeon Haswell testbeds (3n-hsw) and with Intel Hyper-Threading Enabled
-for all Xeon Skylake testbeds.
+XEON processors configured with Intel Hyper-Threading Enabled
+for all Xeon Skylake and Xeon Cascadelake testbeds.
 
 More information about physical testbeds is provided in
 :ref:`tested_physical_topologies`.
@@ -27,15 +26,8 @@ Multi-core Tests
 |csit-release| multi-core tests are executed in the following VPP worker
 thread and physical core configurations:
 
-#. Intel Xeon Haswell testbeds (3n-hsw) with Intel HT disabled
-   (1 logical CPU core per each physical core):
-
-  #. 1t1c - 1 VPP worker thread on 1 physical core.
-  #. 2t2c - 2 VPP worker threads on 2 physical cores.
-  #. 4t4c - 4 VPP worker threads on 4 physical cores.
-
-#. Intel Xeon Skylake testbeds (2n-skx, 3n-skx) with Intel HT enabled
-   (2 logical CPU cores per each physical core):
+#. Intel Xeon Skylake and Cascadelake testbeds (2n-skx, 3n-skx, 2n-clx)
+   with Intel HT enabled (2 logical CPU cores per each physical core):
 
   #. 2t1c - 2 VPP worker threads on 1 physical core.
   #. 4t2c - 4 VPP worker threads on 2 physical cores.