X-Git-Url: https://gerrit.fd.io/r/gitweb?p=csit.git;a=blobdiff_plain;f=docs%2Freport%2Fintroduction%2Fphysical_testbeds.rst;h=30a4698f8bc9df95a3dbef036908ffe5b8b1dcf2;hp=fbc16eeaa377313e42105bebc2e3c2bb6934248e;hb=bf0fa247e2e95c14bc76dae43a0df26be410d931;hpb=f85930d7b1e3cda191a2e60cbc4e64d93c5fd139

diff --git a/docs/report/introduction/physical_testbeds.rst b/docs/report/introduction/physical_testbeds.rst
index fbc16eeaa3..30a4698f8b 100644
--- a/docs/report/introduction/physical_testbeds.rst
+++ b/docs/report/introduction/physical_testbeds.rst
@@ -1,7 +1,7 @@
 .. _tested_physical_topologies:
 
-Physical Testbeds
-=================
+Performance Physical Testbeds
+=============================
 
 All :abbr:`FD.io (Fast Data Input/Ouput)` :abbr:`CSIT (Continuous System
 Integration and Testing)` performance test results included in this
@@ -26,18 +26,11 @@ Two physical server topology types are used:
 Current FD.io production testbeds are built with SUT servers based on
 the following processor architectures:
 
-- Intel Xeon: Skylake Platinum 8180, Cascadelake 6252N, (Icelake 8358 
-  installation in progress).
+- Intel Xeon: Skylake Platinum 8180, Cascadelake 6252N, Icelake 8358.
 - Intel Atom: Denverton C3858.
 - Arm: TaiShan 2280, hip07-d05.
 - AMD EPYC: Zen2 7532.
 
-CSIT-2106 report data for Intel Xeon Icelake testbeds comes from
-testbeds in Intel labs set up per CSIT specification and running CSIT
-code. Physical setup used is specified in 2n-icx and 3n-icx sections
-below. For details about tested VPP and CSIT versions
-see :ref:`vpp_performance_tests_release_notes`.
-
 Server SUT performance depends on server and processor type, hence
 results for testbeds based on different servers must be reported
 separately, and compared if appropriate.
@@ -46,7 +39,39 @@ Complete technical specifications of compute servers used in CSIT
 physical testbeds are maintained in FD.io CSIT repository:
 https://git.fd.io/csit/tree/docs/lab/testbed_specifications.md.
 
-Following is the description of existing production testbeds.
+Physical NICs and Drivers
+-------------------------
+
+SUT and TG servers are equipped with a number of different NIC models.
+
+VPP is performance tested on SUTs with the following NICs and drivers:
+
+#. 2p10GE: x550, x553 Intel (codename Niantic)
+   - DPDK Poll Mode Driver (PMD).
+#. 4p10GE: x710-DA4 Intel (codename Fortville, FVL)
+   - DPDK PMD.
+   - AVF in PMD mode.
+   - AF_XDP in PMD mode.
+#. 2p25GE: xxv710-DA2 Intel (codename Fortville, FVL)
+   - DPDK PMD.
+   - AVF in PMD mode.
+   - AF_XDP in PMD mode.
+#. 2p100GE: cx556a-edat Mellanox ConnectX5
+   - RDMA_core in PMD mode.
+#. 2p100GE: E810-2CQDA2 Intel (codename Columbiaville, CVL)
+   - DPDK PMD.
+   - AVF in PMD mode.
+
+DPDK applications, testpmd and l3fwd, are performance tested on the same
+SUTs exclusively with DPDK drivers for all NICs.
+
+TRex running on TGs is using DPDK drivers for all NICs.
+
+VPP hoststack tests utilize ab (Apache HTTP server benchmarking tool)
+running on TGs and using Linux drivers for all NICs.
+
+For more information see :ref:`vpp_test_environment`
+and :ref:`dpdk_test_environment`.
 
 2-Node AMD EPYC Zen2 (2n-zn2)
 -----------------------------
@@ -73,14 +98,13 @@ GHz, 32 cores). 2n-zn2 physical topology is shown below.
         :alt: testbed-2n-zn2
         :align: center
 
-SUT server is populated with the following NIC models:
+SUT NICs:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
 #. NIC-3: cx556a-edat ConnectX5 2p100GE Mellanox.
 
-TG server runs TRex application and is populated with the following
-NIC models:
+TG NICs:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
@@ -90,7 +114,7 @@ All AMD EPYC Zen2 7532 servers run with AMD SMT enabled, doubling the
 number of logical cores exposed to Linux.
 
 2-Node Xeon Cascadelake (2n-clx)
----------------------------------
+--------------------------------
 
 Three 2n-clx testbeds are in operation in FD.io labs. Each 2n-clx testbed
 is built with two SuperMicro SYS-7049GP-TRT servers, SUTs are equipped with two
@@ -115,7 +139,7 @@ Cache, 2.70 GHz, 28 cores). 2n-clx physical topology is shown below.
         :alt: testbed-2n-clx
         :align: center
 
-SUT servers are populated with the following NIC models:
+SUT NICs:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
@@ -124,8 +148,7 @@ SUT servers are populated with the following NIC models:
 #. NIC-5: empty, future expansion.
 #. NIC-6: empty, future expansion.
 
-TG servers run T-Rex application and are populated with the following
-NIC models:
+TG NICs:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
@@ -137,15 +160,14 @@ NIC models:
 All Intel Xeon Cascadelake servers run with Intel Hyper-Threading enabled,
 doubling the number of logical cores exposed to Linux.
 
-2-Node Xeon Icelake (2n-icx) EXPERIMENTAL
------------------------------------------
+.. _physical_testbeds_2n_icx:
+
+2-Node Xeon Icelake (2n-icx)
+----------------------------
 
-One 2n-icx testbed located in Intel labs was used for CSIT testing. It
-is built with two SuperMicro SYS-740GP-TNRT servers. SUT is equipped
-with two Intel Xeon Gold 6338N processors (48 MB Cache, 2.20 GHz, 32
-cores). TG is equiped with two Intel Xeon Ice Lake Platinum 8360Y
-processors (54 MB Cache, 2.40 GHz, 36 cores). 2n-icx physical topology
-is shown below.
+One 2n-icx testbed is in operation in FD.io labs. It is built with two
+SuperMicro SYS-740GP-TNRT servers, each in turn equipped with two Intel Xeon
+Platinum 8358 processors (48 MB Cache, 2.60 GHz, 32 cores).
 
 .. only:: latex
 
@@ -164,22 +186,23 @@ is shown below.
         :alt: testbed-2n-icx
         :align: center
 
-SUT and TG servers are populated with the following NIC models:
+SUT and TG NICs:
 
-#. NIC-1: E810-2CQDA2 2p100GbE Intel.
+#. NIC-1: xxv710-DA2 2p25GE Intel.
+#. NIC-2: E810-2CQDA2 2p100GbE Intel (* to be added).
+#. NIC-3: E810-CQDA4 4p100GbE Intel (* to be added).
 
 All Intel Xeon Icelake servers run with Intel Hyper-Threading enabled,
 doubling the number of logical cores exposed to Linux.
 
-3-Node Xeon Icelake (3n-icx) EXPERIMENTAL
------------------------------------------
+.. _physical_testbeds_3n_icx:
+
+3-Node Xeon Icelake (3n-icx)
+----------------------------
 
-One 3n-icx testbed located in Intel labs was used for CSIT testing. It
-is built with three SuperMicro SYS-740GP-TNRT servers. SUTs are
-equipped each with two Intel Xeon Platinum 8360Y processors (54 MB
-Cache, 2.40 GHz, 36 cores). TG is equiped with two Intel Xeon Ice Lake
-Platinum 8360Y processors (54 MB Cache, 2.40 GHz, 36 cores). 3n-icx
-physical topology is shown below.
+One 3n-icx testbed is in operation in FD.io labs. It is built with three
+SuperMicro SYS-740GP-TNRT servers, each in turn equipped with two Intel Xeon
+Platinum 8358 processors (48 MB Cache, 2.60 GHz, 32 cores).
 
 .. only:: latex
 
@@ -198,9 +221,11 @@ physical topology is shown below.
         :alt: testbed-3n-icx
         :align: center
 
-SUT and TG servers are populated with the following NIC models:
+SUT and TG NICs:
 
-#. NIC-1: E810-2CQDA2 2p100GbE Intel.
+#. NIC-1: xxv710-DA2 2p25GE Intel.
+#. NIC-2: E810-2CQDA2 2p100GbE Intel (* to be added).
+#. NIC-3: E810-CQDA4 4p100GbE Intel (* to be added).
 
 All Intel Xeon Icelake servers run with Intel Hyper-Threading enabled,
 doubling the number of logical cores exposed to Linux.
@@ -230,7 +255,7 @@ Cache, 2.50 GHz, 28 cores). 2n-skx physical topology is shown below.
         :alt: testbed-2n-skx
         :align: center
 
-SUT servers are populated with the following NIC models:
+SUT NICs:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
@@ -239,8 +264,7 @@ SUT servers are populated with the following NIC models:
 #. NIC-5: empty, future expansion.
 #. NIC-6: empty, future expansion.
 
-TG servers run T-Rex application and are populated with the following
-NIC models:
+TG NICs:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
@@ -278,7 +302,7 @@ Cache, 2.50 GHz, 28 cores). 3n-skx physical topology is shown below.
         :alt: testbed-3n-skx
         :align: center
 
-SUT1 and SUT2 servers are populated with the following NIC models:
+SUT1 and SUT2 NICs:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
@@ -287,8 +311,7 @@ SUT1 and SUT2 servers are populated with the following NIC models:
 #. NIC-5: empty, future expansion.
 #. NIC-6: empty, future expansion.
 
-TG servers run T-Rex application and are populated with the following
-NIC models:
+TG NICs:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
@@ -327,15 +350,14 @@ Cache, 2.00 GHz, 12 cores). 2n-dnv physical topology is shown below.
         :alt: testbed-2n-dnv
         :align: center
 
-SUT server have four internal 10G NIC port:
+SUT 10GE NIC ports:
 
 #. P-1: x553 copper port.
 #. P-2: x553 copper port.
 #. P-3: x553 fiber port.
 #. P-4: x553 fiber port.
 
-TG server run T-Rex software traffic generator and are populated with the
-following NIC models:
+TG NICs:
 
 #. NIC-1: x550-T2 2p10GE Intel.
 #. NIC-2: x550-T2 2p10GE Intel.
@@ -371,16 +393,53 @@ topology is shown below.
         :alt: testbed-3n-dnv
         :align: center
 
-SUT1 and SUT2 servers are populated with the following NIC models:
+SUT1 and SUT2 NICs:
 
 #. NIC-1: x553 2p10GE fiber Intel.
 #. NIC-2: x553 2p10GE copper Intel.
 
-TG servers run T-Rex application and are populated with the following
-NIC models:
+TG NICs:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 
+.. _physical_testbeds_3n_alt:
+
+3-Node ARM Altra (3n-alt)
+---------------------------
+
+One 3n-tsh testbed is built with: i) one SuperMicro SYS-740GP-TNRT
+server acting as TG and equipped with two Intel Xeon Icelake Platinum
+8358 processors (80 MB Cache, 2.60 GHz, 32 cores), and ii) one Ampere
+Altra server acting as SUT and equipped with two Q80-30 processors
+(80* ARM Neoverse N1). 3n-alt physical topology is shown below.
+
+.. only:: latex
+
+    .. raw:: latex
+
+        \begin{figure}[H]
+            \centering
+                \graphicspath{{../_tmp/src/introduction/}}
+                \includegraphics[width=0.90\textwidth]{testbed-3n-alt}
+                \label{fig:testbed-3n-alt}
+        \end{figure}
+
+.. only:: html
+
+    .. figure:: testbed-3n-alt.svg
+        :alt: testbed-3n-alt
+        :align: center
+
+SUT1 and SUT2 NICs:
+
+#. NIC-1: xl710-QDA2-2p40GE Intel.
+
+TG NICs:
+
+#. NIC-1: xxv710-DA2-2p25GE Intel.
+#. NIC-2: e810-XXVDA4-4p25GE Intel.
+#. NIC-3: e810-2CQDA2-2p100GE Intel.
+
 3-Node ARM TaiShan (3n-tsh)
 ---------------------------
 
@@ -407,20 +466,19 @@ processor (64* ARM Cortex-A72). 3n-tsh physical topology is shown below.
         :alt: testbed-3n-tsh
         :align: center
 
-SUT1 and SUT2 servers are populated with the following NIC models:
+SUT1 and SUT2 NICs:
 
 #. NIC-1: connectx4 2p25GE Mellanox.
 #. NIC-2: x520 2p10GE Intel.
 
-TG server runs T-Rex application and is populated with the following
-NIC models:
+TG NICs:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
 #. NIC-3: xl710-QDA2 2p40GE Intel.
 
 2-Node ARM ThunderX2 (2n-tx2)
----------------------------
+-----------------------------
 
 One 2n-tx2 testbed is built with: i) one SuperMicro SYS-7049GP-TRT
 server acting as TG and equipped with two Intel Xeon Skylake Platinum
@@ -445,12 +503,11 @@ ThunderX2 ARMv8 CN9975 processors. 2n-tx2 physical topology is shown below.
         :alt: testbed-2n-tx2
         :align: center
 
-SUT server is populated with the following NIC models:
+SUT NICs:
 
 #. NIC-1: xl710-QDA2 2p40GE Intel (not connected).
 #. NIC-2: xl710-QDA2 2p40GE Intel.
 
-TG server run T-Rex application and is populated with the following
-NIC models:
+TG NICs:
 
 #. NIC-1: xl710-QDA2 2p40GE Intel.