X-Git-Url: https://gerrit.fd.io/r/gitweb?p=csit.git;a=blobdiff_plain;f=docs%2Freport%2Fintroduction%2Fphysical_testbeds.rst;h=74d3c58183ea555d0c5ae8bb23d21426ae79a77c;hp=ba6cd393896c7f10d9a75b902d8238faf81a2878;hb=b659ab3d2638652de0357d29be1ec7704df97555;hpb=2c55fe4a2d74352090b64118858a3557e197aeee

diff --git a/docs/report/introduction/physical_testbeds.rst b/docs/report/introduction/physical_testbeds.rst
index ba6cd39389..74d3c58183 100644
--- a/docs/report/introduction/physical_testbeds.rst
+++ b/docs/report/introduction/physical_testbeds.rst
@@ -6,9 +6,8 @@ Physical Testbeds
 All :abbr:`FD.io (Fast Data Input/Ouput)` :abbr:`CSIT (Continuous System
 Integration and Testing)` performance testing listed in this report are
 executed on physical testbeds built with bare-metal servers hosted by
-:abbr:`LF (Linux Foundation)` FD.io project.
-
-Two testbed topologies are used:
+:abbr:`LF (Linux Foundation)` FD.io project. Two testbed topologies are
+used:
 
 - **3-Node Topology**: Consisting of two servers acting as SUTs
   (Systems Under Test) and one server as TG (Traffic Generator), all
@@ -28,6 +27,11 @@ Server SUT and DUT performance depends on server and processor type,
 hence results for testbeds based on different servers must be reported
 separately, and compared if appropriate.
 
+Complete technical specifications of compute servers used in CSIT
+physical testbeds are maintained in FD.io CSIT repository:
+`FD.io CSIT testbeds - Xeon Skylake, Arm, Atom`_ and
+`FD.io CSIT Testbeds - Xeon Haswell`_.
+
 Following sections describe existing production testbed types.
 
 3-Node Xeon Haswell (3n-hsw)
@@ -77,10 +81,6 @@ All Intel Xeon Haswell servers run with Intel Hyper-Threading disabled,
 making the number of logical cores exposed to Linux match the number of
 18 physical cores per processor socket.
 
-Complete 3n-hsw testbeds specification is available on
-`CSIT LF testbed <https://wiki.fd.io/view/CSIT/CSIT_LF_testbed>`_
-wiki page.
-
 Total of three 3n-hsw testbeds are in operation in FD.io labs.
 
 3-Node Xeon Skylake (3n-skx)
@@ -130,10 +130,6 @@ All Intel Xeon Skylake servers run with Intel Hyper-Threading enabled,
 doubling the number of logical cores exposed to Linux, with 56 logical
 cores and 28 physical cores per processor socket.
 
-Complete 3n-skx testbeds specification is available on
-`CSIT LF lab extension <https://wiki.fd.io/view/CSIT/fdio_csit_lab_ext_lld_draft>`_
-wiki page.
-
 Total of two 3n-skx testbeds are in operation in FD.io labs.
 
 2-Node Xeon Skylake (2n-skx)
@@ -183,8 +179,47 @@ All Intel Xeon Skylake servers run with Intel Hyper-Threading enabled,
 doubling the number of logical cores exposed to Linux, with 56 logical
 cores and 28 physical cores per processor socket.
 
-Complete 2n-skx testbed specification is available on
-`CSIT/Testbeds: Xeon Skx, Arm, Atom
-<https://wiki.fd.io/view/CSIT/Testbeds:_Xeon_Skx,_Arm,_Atom.>`_ wiki page.
-
 Total of four 2n-skx testbeds are in operation in FD.io labs.
+
+2-Node Atom Denverton (2n-dnv)
+------------------------------
+
+2n-dnv testbed is based on one Intel S2600WFT Server that is equipped with
+two Intel Xeon Skylake Platinum 8180 2.5GHz 28 core processors and one
+SuperMicro SYS-E300-9A server that is equipped with one Intel Atom CPU
+C3858 2.00GHz 12 core processors. Physical testbed topology is depicted in
+a figure below.
+
+.. only:: latex
+
+    .. raw:: latex
+
+        \begin{figure}[H]
+            \centering
+                \graphicspath{{../_tmp/src/introduction/}}
+                \includegraphics[width=0.90\textwidth]{testbed-2n-dnv}
+                \label{fig:testbed-2n-dnv}
+        \end{figure}
+
+.. only:: html
+
+    .. figure:: testbed-2n-dnv.svg
+        :alt: testbed-2n-dnv
+        :align: center
+
+SUT server have four internal 10G NIC port:
+
+#. P-1: x553 copper port.
+#. P-2: x553 copper port.
+#. P-3: x553 fiber port.
+#. P-4: x553 fiber port.
+
+TG server run T-Rex software traffic generator and are populated with the
+following NIC models:
+
+#. NIC-1: x550-T2 2p10GE Intel.
+#. NIC-2: x550-T2 2p10GE Intel.
+#. NIC-3: x520-DA2 2p10GE Intel.
+#. NIC-4: x520-DA2 2p10GE Intel.
+
+The 2n-dnv testbed is in operation in Intel SH labs.