X-Git-Url: https://gerrit.fd.io/r/gitweb?p=csit.git;a=blobdiff_plain;f=docs%2Freport%2Fintroduction%2Fphysical_testbeds.rst;h=b5c9c9db3667c7d54bee10ee69a99005b247cc4d;hp=3776c03d727bf4e007bdbd13977bd6150cc06a80;hb=bb7e8747d67176367fabadac85bc4e2571a47c93;hpb=9c459a2b303eb8d776ac040bc82830d850a67623

diff --git a/docs/report/introduction/physical_testbeds.rst b/docs/report/introduction/physical_testbeds.rst
index 3776c03d72..b5c9c9db36 100644
--- a/docs/report/introduction/physical_testbeds.rst
+++ b/docs/report/introduction/physical_testbeds.rst
@@ -29,7 +29,8 @@ the following processor architectures:
 - Intel Xeon: Skylake Platinum 8180, Haswell-SP E5-2699v3,
   Cascade Lake Platinum 8280, Cascade Lake 6252N.
 - Intel Atom: Denverton C3858.
-- ARM: TaiShan 2280, hip07-d05.
+- Arm: TaiShan 2280, hip07-d05.
+- AMD EPYC: Zen2 7532.
 
 Server SUT performance depends on server and processor type, hence
 results for testbeds based on different servers must be reported
@@ -41,6 +42,47 @@ https://git.fd.io/csit/tree/docs/lab/testbed_specifications.md.
 
 Following is the description of existing production testbeds.
 
+2-Node AMD EPYC Zen2 (2n-zn2)
+-----------------------------
+
+One 2n-zn2 testbed in in operation in FD.io labs. It is built based on
+two SuperMicro SuperMicro AS-1114S-WTRT servers, with SUT and TG servers
+equipped with one AMD EPYC Zen2 7532 processor each (256 MB Cache, 2.40
+GHz, 32 cores). 2n-zn2 physical topology is shown below.
+
+.. only:: latex
+
+    .. raw:: latex
+
+        \begin{figure}[H]
+            \centering
+                \graphicspath{{../_tmp/src/introduction/}}
+                \includegraphics[width=0.90\textwidth]{testbed-2n-zn2}
+                \label{fig:testbed-2n-zn2}
+        \end{figure}
+
+.. only:: html
+
+    .. figure:: testbed-2n-zn2.svg
+        :alt: testbed-2n-zn2
+        :align: center
+
+SUT server is populated with the following NIC models:
+
+#. NIC-1: x710-DA4 4p10GE Intel.
+#. NIC-2: xxv710-DA2 2p25GE Intel.
+#. NIC-3: cx556a-edat ConnectX5 2p100GE Mellanox.
+
+TG server runs TRex application and is populated with the following
+NIC models:
+
+#. NIC-1: x710-DA4 4p10GE Intel.
+#. NIC-2: xxv710-DA2 2p25GE Intel.
+#. NIC-3: cx556a-edat ConnectX5 2p100GE Mellanox.
+
+All AMD EPYC Zen2 7532 servers run with AMD SMT enabled, doubling the
+number of logical cores exposed to Linux.
+
 2-Node Xeon Cascade Lake (2n-clx)
 ---------------------------------
 
@@ -344,8 +386,45 @@ SUT1 and SUT2 servers are populated with the following NIC models:
 #. NIC-1: connectx4 2p25GE Mellanox.
 #. NIC-2: x520 2p10GE Intel.
 
-TG servers run T-Rex application and are populated with the following
+TG server runs T-Rex application and is populated with the following
 NIC models:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
+#. NIC-3: xl710-QDA2 2p40GE Intel.
+
+2-Node ARM ThunderX2 (2n-tx2)
+---------------------------
+
+One 2n-tx2 testbed is built with: i) one SuperMicro SYS-7049GP-TRT
+server acting as TG and equipped with two Intel Xeon Skylake Platinum
+8180 processors (38.5 MB Cache, 2.50 GHz, 28 cores), and ii) one Marvell
+ThnderX2 9975 (28* ThunderX2) server acting as SUT and equipped with two
+ThunderX2 ARMv8 CN9975 processors. 2n-tx2 physical topology is shown below.
+
+.. only:: latex
+
+    .. raw:: latex
+
+        \begin{figure}[H]
+            \centering
+                \graphicspath{{../_tmp/src/introduction/}}
+                \includegraphics[width=0.90\textwidth]{testbed-2n-tx2}
+                \label{fig:testbed-2n-tx2}
+        \end{figure}
+
+.. only:: html
+
+    .. figure:: testbed-2n-tx2.svg
+        :alt: testbed-2n-tx2
+        :align: center
+
+SUT server is populated with the following NIC models:
+
+#. NIC-1: xl710-QDA2 2p40GE Intel (not connected).
+#. NIC-2: xl710-QDA2 2p40GE Intel.
+
+TG server run T-Rex application and is populated with the following
+NIC models:
+
+#. NIC-1: xl710-QDA2 2p40GE Intel.