X-Git-Url: https://gerrit.fd.io/r/gitweb?p=csit.git;a=blobdiff_plain;f=docs%2Freport%2Fintroduction%2Ftest_environment_intro.rst;h=c2feb1b4c4797ba49d1f184d138299e8f2b8adf7;hp=b02520b99da10c4fd5d00c593c87e6ba867e6591;hb=cc58afc7de521e571fe4cbaa4c9841a2d3e9be52;hpb=c5e84fbee876a45d3495cde6f4e2d8140cacbe5a diff --git a/docs/report/introduction/test_environment_intro.rst b/docs/report/introduction/test_environment_intro.rst index b02520b99d..c2feb1b4c4 100644 --- a/docs/report/introduction/test_environment_intro.rst +++ b/docs/report/introduction/test_environment_intro.rst @@ -1,57 +1,104 @@ Test Environment ================ -Physical Testbeds ------------------ +.. _test_environment_versioning: -FD.io CSIT performance tests are executed in physical testbeds hosted by -:abbr:`LF (Linux Foundation)` for FD.io project. Two physical testbed -topology types are used: +Environment Versioning +---------------------- -- **3-Node Topology**: Consisting of two servers acting as SUTs - (Systems Under Test) and one server as TG (Traffic Generator), all - connected in ring topology. -- **2-Node Topology**: Consisting of one server acting as SUTs and one - server as TG both connected in ring topology. +CSIT test environment versioning has been introduced to track +modifications of the test environment. -Tested SUT servers are based on a range of processors including Intel -Xeon Haswell-SP, Intel Xeon Skylake-SP, Intel Xeon Cascadelake-SP, Arm, Intel -Atom. More detailed description is provided in -:ref:`tested_physical_topologies`. Tested logical topologies are -described in :ref:`tested_logical_topologies`. +Any benchmark anomalies (progressions, regressions) between releases of +a DUT application (e.g. VPP, DPDK), are determined by testing it in the +same test environment, to avoid test environment changes clouding the +picture. +To beter distinguish impact of test environment changes, +we also execute tests without any SUT (just with TRex TG sending packets +over a link looping back to TG). -Server Specifications ---------------------- +A mirror approach is introduced to determine benchmarking anomalies due +to the test environment change. This is achieved by testing the same DUT +application version between releases of CSIT test system. This works +under the assumption that the behaviour of the DUT is deterministic +under the test conditions. -Complete technical specifications of compute servers used in CSIT -physical testbeds are maintained in FD.io CSIT repository: -`FD.io CSIT testbeds - Xeon Cascadelake`_, -`FD.io CSIT testbeds - Xeon Skylake, Arm, Atom`_ and -`FD.io CSIT Testbeds - Xeon Haswell`_. +CSIT test environment versioning scheme ensures integrity of all the +test system components, including their HW revisions, compiled SW code +versions and SW source code, within a specific CSIT version. Components +included in the CSIT environment versioning include: -Pre-Test Server Calibration ---------------------------- +- **HW** Server hardware firmware and BIOS (motherboard, processsor, + NIC(s), accelerator card(s)), tracked in CSIT branch in + :file:`./docs/lab/_hw_bios_cfg.md`, e.g. `Xeon + Skylake servers + `_. +- **Linux** Server Linux OS version and configuration, tracked in CSIT + Reports in `SUT Settings + `_ + and `Pre-Test Server Calibration + `_. +- **TRex** TRex Traffic Generator version, drivers and configuration + tracked in `TG Settings + `_. +- **CSIT** CSIT framework code tracked in CSIT release branches. -Number of SUT server sub-system runtime parameters have been identified -as impacting data plane performance tests. Calibrating those parameters -is part of FD.io CSIT pre-test activities, and includes measuring and -reporting following: +Following is the list of CSIT versions to date: -#. System level core jitter – measure duration of core interrupts by - Linux in clock cycles and how often interrupts happen. Using - `CPU core jitter tool `_. +- Ver. 1 associated with CSIT rls1908 branch (`HW + `_, `Linux + `_, + `TRex + `_, + `CSIT `_). +- Ver. 2 associated with CSIT rls2001 branch (`HW + `_, `Linux + `_, + `TRex + `_, + `CSIT `_). +- Ver. 4 associated with CSIT rls2005 branch (`HW + `_, `Linux + `_, + `TRex + `_, + `CSIT `_). +- Ver. 5 associated with CSIT rls2009 branch (`HW + `_, `Linux + `_, + `TRex + `_, + `CSIT `_). -#. Memory bandwidth – measure bandwidth with `Intel MLC tool - `_. + - The main change is TRex data-plane core resource adjustments: + `increase from 7 to 8 cores and pinning cores to interfaces `_ + for better TRex performance with symmetric traffic profiles. +- Ver. 6 associated with CSIT rls2101 branch (`HW + `_, `Linux + `_, + `TRex + `_, + `CSIT `_). -#. Memory latency – measure memory latency with Intel MLC tool. + - The main change is TRex version upgrade: + `increase from 2.82 to 2.86 `_. +- Ver. 7 associated with CSIT rls2106 branch (`HW + `_, `Linux + `_, + `TRex + `_, + `CSIT `_). -#. Cache latency at all levels (L1, L2, and Last Level Cache) – measure - cache latency with Intel MLC tool. + - TRex version upgrade: + `increase from 2.86 to 2.88 `_. + - Ubuntu upgrade: + `upgrade from 18.04 LTS to 20.04.2 LTS `_. +- Ver. 8 associated with CSIT rls2110 branch (`HW + `_, `Linux + `_, + `TRex + `_, + `CSIT `_). -Measured values of listed parameters are especially important for -repeatable zero packet loss throughput measurements across multiple -system instances. Generally they come useful as a background data for -comparing data plane performance results across disparate servers. - -Following sections include measured calibration data for testbeds. + - Intel NIC 700/800 series firmware upgrade based on DPDK compatibility + matrix: `depends on testbed type `_.