X-Git-Url: https://gerrit.fd.io/r/gitweb?p=csit.git;a=blobdiff_plain;f=docs%2Freport%2Fintroduction%2Ftest_environment_intro.rst;h=ddb14ce9a8494a834eb32c4b6c3c25e3364254a5;hp=c35cba3161a1e9f6bb1c78d069e7c6244dcd5f2c;hb=07dc2213e6c0e95147e7025b02e91ed89ea07209;hpb=ca585727f655942827ea4db1ae0318485655a109 diff --git a/docs/report/introduction/test_environment_intro.rst b/docs/report/introduction/test_environment_intro.rst index c35cba3161..ddb14ce9a8 100644 --- a/docs/report/introduction/test_environment_intro.rst +++ b/docs/report/introduction/test_environment_intro.rst @@ -1,6 +1,8 @@ Test Environment ================ +.. _test_environment_versioning: + Environment Versioning ---------------------- @@ -30,12 +32,12 @@ included in the CSIT environment versioning include: `_. - **Linux** Server Linux OS version and configuration, tracked in CSIT Reports in `SUT Settings - `_ + `_ and `Pre-Test Server Calibration - `_. + `_. - **TRex** TRex Traffic Generator version, drivers and configuration tracked in `TG Settings - `_. + `_. - **CSIT** CSIT framework code tracked in CSIT release branches. Following is the list of CSIT versions to date: @@ -58,15 +60,51 @@ Following is the list of CSIT versions to date: `TRex `_, `CSIT `_). +- Ver. 5 associated with CSIT rls2009 branch (`HW + `_, `Linux + `_, + `TRex + `_, + `CSIT `_). + + - The main change is TRex data-plane core resource adjustments: + `increase from 7 to 8 cores and pinning cores to interfaces `_ + for better TRex performance with symmetric traffic profiles. +- Ver. 6 associated with CSIT rls2101 branch (`HW + `_, `Linux + `_, + `TRex + `_, + `CSIT `_). + + - The main change is TRex version upgrade: + `increase from 2.82 to 2.86 `_. +- Ver. 7 associated with CSIT rls2106 branch (`HW + `_, `Linux + `_, + `TRex + `_, + `CSIT `_). + + - TRex version upgrade: + `increase from 2.86 to 2.88 `_. + - Ubuntu upgrade: + `upgrade from 18.04 LTS to 20.04.2 LTS `_. +- Ver. 8 associated with CSIT rls2110 branch (`HW + `_, `Linux + `_, + `TRex + `_, + `CSIT `_). -To identify performance changes due to VPP code development from -v20.01.0 to v20.05.0, both have been tested in CSIT environment ver. 4 -and compared against each other. All substantial progressions and -regressions have been marked up with RCA analysis. -:ref:`vpp_throughput_comparisons` and :ref:`vpp_known_issues`. + - Intel NIC 700/800 series firmware upgrade based on DPDK compatibility + matrix: `depends on testbed type `_. -CSIT environment ver. 4 has been evaluated against the ver. 2 by -benchmarking VPP v20.01.0 in both environment versions. +To identify performance changes due to VPP code development between previous +and current VPP release version, both have been tested in CSIT environment of +latest version and compared against each other. All substantial progressions and +regressions have been marked up with RCA analysis. See +:ref:`vpp_throughput_comparisons` and :ref:`vpp_known_issues`. Physical Testbeds ----------------- @@ -82,7 +120,7 @@ topology types are used: server as TG both connected in ring topology. Tested SUT servers are based on a range of processors including Intel -Xeon Haswell-SP, Intel Xeon Skylake-SP, Intel Xeon Cascade Lake-SP, Arm, +Intel Xeon Skylake-SP, Intel Xeon Cascade Lake-SP, Arm, Intel Atom. More detailed description is provided in :ref:`tested_physical_topologies`. Tested logical topologies are described in :ref:`tested_logical_topologies`. @@ -93,5 +131,4 @@ Server Specifications Complete technical specifications of compute servers used in CSIT physical testbeds are maintained in FD.io CSIT repository: `FD.io CSIT testbeds - Xeon Cascade Lake`_, -`FD.io CSIT testbeds - Xeon Skylake, Arm, Atom`_ and -`FD.io CSIT Testbeds - Xeon Haswell`_. +`FD.io CSIT testbeds - Xeon Skylake, Arm, Atom`_.