X-Git-Url: https://gerrit.fd.io/r/gitweb?p=csit.git;a=blobdiff_plain;f=docs%2Freport%2Ftestpmd_performance_tests%2Foverview.rst;h=78d214808a02dbdeec982870d855ece1112c873a;hp=db1ac7849d8c313c1bae97cda984122e57c7db2a;hb=10649b3ce07bbb3144d196c403d8c1fa65ddf116;hpb=da2aa127ee071e37bc4d6060dd39476179e65365

diff --git a/docs/report/testpmd_performance_tests/overview.rst b/docs/report/testpmd_performance_tests/overview.rst
index db1ac7849d..78d214808a 100644
--- a/docs/report/testpmd_performance_tests/overview.rst
+++ b/docs/report/testpmd_performance_tests/overview.rst
@@ -42,8 +42,8 @@ tested NIC models include:
 #. 2port40GE VIC1385 Cisco.
 #. 2port40GE XL710 Intel.
 
-Detailed LF FD.io test bed specification and topology is described in
-`wiki CSIT LF testbed <https://wiki.fd.io/view/CSIT/CSIT_LF_testbed>`_.
+For detailed LF FD.io test bed specification and physical topology please refer
+to `LF FDio CSIT testbed wiki page <https://wiki.fd.io/view/CSIT/CSIT_LF_testbed>`_.
 
 Performance Tests Coverage
 --------------------------
@@ -71,6 +71,11 @@ CSIT |release| includes following performance test suites, listed per NIC type:
   - **L2IntLoop** - L2 Interface Loop forwarding any Ethernet frames between
     two Interfaces.
 
+- 2port40GE XL710 Intel
+
+  - **L2IntLoop** - L2 Interface Loop forwarding any Ethernet frames between
+    two Interfaces.
+
 Execution of performance tests takes time, especially the throughput discovery
 tests. Due to limited HW testbed resources available within FD.io labs hosted
 by Linux Foundation, the number of tests for NICs other than X520 (a.k.a.
@@ -94,7 +99,6 @@ following Testpmd thread and core configurations:
 
 #. 1t1c - 1 Testpmd pmd thread on 1 CPU physical core.
 #. 2t2c - 2 Testpmd pmd threads on 2 CPU physical cores.
-#. 4t4c - 4 Testpmd pmd threads on 4 CPU physical cores.
 
 Note that in many tests running Testpmd reaches tested NIC I/O bandwidth
 or packets-per-second limit.
@@ -147,4 +151,4 @@ Reported latency values are measured using following methodology:
 - TRex setup introduces an always-on error of about 2*2usec per latency flow -
   additonal Tx/Rx interface latency induced by TRex SW writing and reading
   packet timestamps on CPU cores without HW acceleration on NICs closer to the
-  interface line.
\ No newline at end of file
+  interface line.