X-Git-Url: https://gerrit.fd.io/r/gitweb?p=csit.git;a=blobdiff_plain;f=docs%2Freport%2Fvpp_performance_tests%2Fpacket_latency_graphs%2Fip4.rst;fp=docs%2Freport%2Fvpp_performance_tests%2Fpacket_latency_graphs%2Fip4.rst;h=894f99748f98b251fd1ada678c3b4d64435c3e3a;hp=23c19dee3f6a5af252798adccfba919b4f0b5592;hb=80e558550b0f076857618c4451987fb60ced19b9;hpb=a08fc340f548a4b223c7c139b4fe59531cf7c694 diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst index 23c19dee3f..894f99748f 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst @@ -13,7 +13,7 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in -`CSIT git repository `_. +`CSIT git repository `_. .. toctree:: @@ -21,5 +21,7 @@ CSIT source code for the test cases used for plots can be found in ip4-2n-skx-x710 ip4-3n-skx-xxv710 ip4-3n-skx-x710 + ip4-2n-clx-xxv710 + ip4-2n-clx-x710 ip4-3n-hsw-xl710 ip4-3n-tsh-x520