X-Git-Url: https://gerrit.fd.io/r/gitweb?p=csit.git;a=blobdiff_plain;f=docs%2Freport%2Fvpp_performance_tests%2Fpacket_latency_graphs%2Fl2.rst;fp=docs%2Freport%2Fvpp_performance_tests%2Fpacket_latency_graphs%2Fl2.rst;h=b1a87deadb4ddf21b5b309b128d4d52d1ac4baed;hp=9643740888b9921bdbfe543f3cbf7746f59cf189;hb=80e558550b0f076857618c4451987fb60ced19b9;hpb=a08fc340f548a4b223c7c139b4fe59531cf7c694 diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst index 9643740888..b1a87deadb 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst @@ -13,7 +13,7 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in -`CSIT git repository `_. +`CSIT git repository `_. .. toctree:: @@ -21,5 +21,7 @@ CSIT source code for the test cases used for plots can be found in l2-2n-skx-x710 l2-3n-skx-xxv710 l2-3n-skx-x710 + l2-2n-clx-xxv710 + l2-2n-clx-x710 l2-3n-hsw-xl710 l2-3n-tsh-x520