X-Git-Url: https://gerrit.fd.io/r/gitweb?p=csit.git;a=blobdiff_plain;f=docs%2Freport%2Fvpp_performance_tests%2Fpacket_latency_graphs%2Fsrv6.rst;h=f3ce5434528b77be4b3722e4c34466779ec35ff9;hp=c7f5a03f0eb393df6db1c70c6e9f96e1e4c16f8c;hb=89d1c95ef55a732f1d5dfbbb8a2117439ac05bd4;hpb=dfff0ee80f3912a6db3f4356254f4cb3e3a9450d

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst
index c7f5a03f0e..f3ce543452 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst
@@ -13,8 +13,10 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
 physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/srv6?h=rls1810>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/srv6?h=rls1908>`_.
 
 .. toctree::
 
-    srv6-3n-hsw-x520
+    srv6-3n-skx-xxv710
+    srv6-3n-hsw-xl710
+    srv6-3n-tsh-x520