X-Git-Url: https://gerrit.fd.io/r/gitweb?p=csit.git;a=blobdiff_plain;f=docs%2Freport%2Fvpp_performance_tests%2Fthroughput_speedup_multi_core%2Fip4_tunnels.rst;h=c995cfc2e39bf7c8e9c6c8ffae8b0e2e6836ee24;hp=574112c7ac611c751022504b0642d045bf060c33;hb=39d8a85dd7bcec88318469308c8ce576aae7dfb1;hpb=426ddf0d4bc727a8cd9522980ab96309d45af0f6 diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst index 574112c7ac..c995cfc2e3 100644 --- a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst +++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst @@ -15,10 +15,9 @@ running in multiple configurations of VPP worker thread(s), a.k.a. VPP data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in -`CSIT git repository `_. +`CSIT git repository `_. .. toctree:: - ip4_tunnels-3n-hsw-x520 - ip4_tunnels-3n-hsw-x710 - ip4_tunnels-3n-skx-x710 + ip4_tunnels-3n-skx-xxv710 + ip4_tunnels-3n-hsw-xl710