X-Git-Url: https://gerrit.fd.io/r/gitweb?p=csit.git;a=blobdiff_plain;f=docs%2Freport%2Fvpp_performance_tests%2Fthroughput_speedup_multi_core%2Fipsec.rst;h=d612a8acce249a8227170834e6d71551dc06adbd;hp=82124a3db214eaf491c30b89f4b66143d8eb3a89;hb=53310a9c512daecbe20a45eb48f5167ea5a6a8b2;hpb=43480e631defcb2fa40cc35e48ee40ce31b1dd68 diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst index 82124a3db2..d612a8acce 100644 --- a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst +++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst @@ -1,3 +1,8 @@ + +.. raw:: latex + + \clearpage + IPSec IPv4 Routing ================== @@ -12,54 +17,8 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in -`CSIT git repository `_. - -3n-hsw-xl710 -~~~~~~~~~~~~ - -64b-base_and_scale ------------------- - -.. raw:: html - -
- -:index:`Speedup: ipsec-3n-hsw-xl710-64b-base_and_scale-ndr` - -.. raw:: html +`CSIT git repository `_. - - -



-
- -.. raw:: latex - - \begin{figure}[H] - \centering - \graphicspath{{../_build/_static/vpp/}} - \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{ipsec-3n-hsw-xl710-64b-base_and_scale-ndr-tsa} - \label{fig:ipsec-3n-hsw-xl710-64b-base_and_scale-ndr-tsa} - \end{figure} - -.. raw:: html - -
- -:index:`Speedup: ipsec-3n-hsw-xl710-64b-base_and_scale-pdr` - -.. raw:: html - - - -



-
- -.. raw:: latex +.. toctree:: - \begin{figure}[H] - \centering - \graphicspath{{../_build/_static/vpp/}} - \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{ipsec-3n-hsw-xl710-64b-base_and_scale-pdr-tsa} - \label{fig:ipsec-3n-hsw-xl710-64b-base_and_scale-pdr-tsa} - \end{figure} + ipsec-3n-hsw-xl710