.. include:: ../introduction/test_environment_intro.rst
+.. include:: ../introduction/test_environment_sut_calib_hsw.rst
+
+.. include:: ../introduction/test_environment_sut_calib_skx.rst
+
.. include:: ../introduction/test_environment_sut_conf_1.rst
.. include:: ../introduction/test_environment_sut_conf_3.rst
testbeds demonstrates single server[DUT1] and single client[DUT2] scenario
using DMM framework and kernel tcp/ip stack.
-In addition to above, |csit-release| report does also include VPP unit test
-results. VPP unit tests are developed within the FD.io VPP project and as they
-complement CSIT system functional tests, they are provided mainly as a reference
-and to provide a more complete view of automated testing executed against
-|vpp-release|.
-
FD.io CSIT system is developed using two main coding platforms :abbr:`RF (Robot
Framework)` and Python2.7. |csit-release| source code for the executed test
suites is available in CSIT branch |release| in the directory
cores and 28 physical cores per processor socket.
Complete 2n-skx testbed specification is available on
-`CSIT LF lab extension <https://wiki.fd.io/view/CSIT/fdio_csit_lab_ext_lld_draft>`_
-wiki page.
+`CSIT/Testbeds: Xeon Skx, Arm, Atom
+<https://wiki.fd.io/view/CSIT/Testbeds:_Xeon_Skx,_Arm,_Atom.>`_ wiki page.
Total of four 2n-skx testbeds are in operation in FD.io labs.
::
-$ sudo /home/testuser/mlc --c2c_latency
-Intel(R) Memory Latency Checker - v3.5
-Command line parameters: --c2c_latency
-
-Measuring cache-to-cache transfer latency (in ns)...
-Local Socket L2->L2 HIT latency 53.7
-Local Socket L2->L2 HITM latency 53.7
-Remote Socket L2->L2 HITM latency (data address homed in writer socket)
- Reader Numa Node
-Writer Numa Node 0 1
- 0 - 113.9
- 1 113.9 -
-Remote Socket L2->L2 HITM latency (data address homed in reader socket)
- Reader Numa Node
-Writer Numa Node 0 1
- 0 - 177.9
- 1 177.6 -
\ No newline at end of file
+ $ sudo /home/testuser/mlc --c2c_latency
+ Intel(R) Memory Latency Checker - v3.5
+ Command line parameters: --c2c_latency
+
+ Measuring cache-to-cache transfer latency (in ns)...
+ Local Socket L2->L2 HIT latency 53.7
+ Local Socket L2->L2 HITM latency 53.7
+ Remote Socket L2->L2 HITM latency (data address homed in writer socket)
+ Reader Numa Node
+ Writer Numa Node 0 1
+ 0 - 113.9
+ 1 113.9 -
+ Remote Socket L2->L2 HITM latency (data address homed in reader socket)
+ Reader Numa Node
+ Writer Numa Node 0 1
+ 0 - 177.9
+ 1 177.6 -
- *L2patch tests* - Tests measure performance of L2patch, cross linking
RX and TX of two physical interfaces.
- - *2-node tests* - Baseline set of 2-node tests covering base ip4, ip4,
+ - *2-node tests* - Baseline set of 2-node tests covering base ip4, ip6,
l2patch, l2bd, l2xc.
- *Generated tests* - Simplified and unified test structure,
DPDK I/O mbufs. Tests are automatically tagged during execution indicating
configuration.
- - *Intel Skylake* - Topologies consisting of 2-node and 3-node using
- SuperMirco servers each equipped with two Intel Xeon Skylake Platinum
- processors.
+ - *Intel Skylake* - Topologies consisting of 2-node and 3-node using
+ SuperMirco servers each equipped with two Intel Xeon Skylake Platinum
+ processors. Full Ansible playbooks refactor for quick server
+ (re)installation and reference pointers of configuration.
#. **Presentation and Analytics Layer**
#. **Test Framework Optimizations**
- - *Performance tests efficiency* - Qemu build/install optimizations,
- warmup phase handling, vpp restart handling. Resulted in improved
- stability and reduced total execution time by 30% for single pkt
- size e.g. 64B/78B.
-
- *General code housekeeping* - ongoing RF keywords optimizations,
removal of redundant RF keywords.