CSIT-1342: Edit the static content for CSIT-1810 report

Change-Id: I44abd4ad646813cc70e9fa2b46b51ee7613dc501
Signed-off-by: Tibor Frank <tifrank@cisco.com>

diff --git a/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst b/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst
index 9dd2add..8f5b807 100644 (file)
--- a/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst
+++ b/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst
@@ -39,6 +39,10 @@ a.k.a. L3FWD data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst b/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst
index a673dc1..32dec95 100644 (file)
--- a/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst
+++ b/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst
@@ -40,6 +40,10 @@ thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst b/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst
index 77ed39a..190aa3d 100644 (file)
--- a/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst
+++ b/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst b/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst
index eeb4d65..143b864 100644 (file)
--- a/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst
+++ b/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst
@@ -1,8 +1,4 @@
 
-.. raw:: latex
-
-    \clearpage
-
 .. raw:: html
 
     <script type="text/javascript">
@@ -40,6 +36,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/csit_release_notes.rst b/docs/report/vpp_performance_tests/csit_release_notes.rst
index 379072c..831ee1b 100644 (file)
--- a/docs/report/vpp_performance_tests/csit_release_notes.rst
+++ b/docs/report/vpp_performance_tests/csit_release_notes.rst
@@ -54,6 +54,10 @@ Changes in |csit-release|
    - **General Code Housekeeping**: Ongoing RF keywords optimizations,
      removal of redundant RF keywords.
 
+.. raw:: latex
+
+    \clearpage
+
 .. _vpp_known_issues:
 
 Known Issues

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
index 4c27c89..0199276 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
@@ -40,6 +40,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/container_orchestrated.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/container_orchestrated.rst
index d746c53..f975f2d 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/container_orchestrated.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/container_orchestrated.rst
@@ -40,6 +40,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/kubernetes/perf/container_memif?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst
index a88e007..0890761 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst
@@ -40,6 +40,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
index db0cfd0..27e83c4 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
@@ -40,6 +40,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
index 5ba63dc..0ad3e34 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
@@ -40,6 +40,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6_tunnels.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6_tunnels.rst
index a193e79..050ace5 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6_tunnels.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6_tunnels.rst
@@ -40,6 +40,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6_tunnels?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ipsec.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ipsec.rst
index 3978a8c..30363a7 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ipsec.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ipsec.rst
@@ -43,6 +43,10 @@ placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/crypto?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-xl710
 ~~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
index ca30ee4..db76780 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
@@ -1,8 +1,4 @@
 
-.. raw:: latex
-
-    \clearpage
-
 .. raw:: html
 
     <script type="text/javascript">
@@ -40,6 +36,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst
index a070b81..3fa202b 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst
@@ -40,6 +40,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/srv6?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst
index 1efd705..11072cc 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst
@@ -41,6 +41,10 @@ placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vm_vhost?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
index cc114bb..26d1e6b 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
@@ -41,6 +41,10 @@ placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vts?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/container_memif.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/container_memif.rst
index 47b7570..5789f44 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/container_memif.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/container_memif.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/container_orchestrated.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/container_orchestrated.rst
index 572ea5a..3b6bdfe 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/container_orchestrated.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/container_orchestrated.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/kubernetes/perf/container_memif?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4.rst
index 9aa1b10..ece6bec 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4_tunnels.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4_tunnels.rst
index 4f24afe..7a818d9 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4_tunnels.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4_tunnels.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6.rst
index ec02256..8a02290 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6_tunnels.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6_tunnels.rst
index ca635a2..cfd1be7 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6_tunnels.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6_tunnels.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6_tunnels?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/ipsec.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/ipsec.rst
index cc8e5c0..3d61369 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/ipsec.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/ipsec.rst
@@ -43,6 +43,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/crypto?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-xl710
 ~~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/l2.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/l2.rst
index f6e4227..d64cef1 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/l2.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/l2.rst
@@ -1,8 +1,4 @@
 
-.. raw:: latex
-
-    \clearpage
-
 .. raw:: html
 
     <script type="text/javascript">
@@ -40,6 +36,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/srv6.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/srv6.rst
index fd5c6f8..5e11278 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/srv6.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/srv6.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/srv6?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/vm_vhost.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/vm_vhost.rst
index 0b86d76..529b994 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/vm_vhost.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/vm_vhost.rst
@@ -41,6 +41,10 @@ and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vm_vhost?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/vts.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/vts.rst
index 985057d..b885fdc 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/vts.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/vts.rst
@@ -41,6 +41,10 @@ and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vts?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 

diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/l2.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/l2.rst
index 55d4525..f866fbd 100644 (file)
--- a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/l2.rst
+++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/l2.rst
@@ -1,8 +1,4 @@
 
-.. raw:: latex
-
-    \clearpage
-
 .. raw:: html
 
     <script type="text/javascript">