From: Tibor Frank <tifrank@cisco.com>
Date: Mon, 5 Nov 2018 14:01:37 +0000 (+0100)
Subject: CSIT-1342: Edit the static content for CSIT-1810 report
X-Git-Url: https://gerrit.fd.io/r/gitweb?p=csit.git;a=commitdiff_plain;h=b641b5bf12a0d1b63ac9afb7c89133297d3b63fe

CSIT-1342: Edit the static content for CSIT-1810 report

Change-Id: I44abd4ad646813cc70e9fa2b46b51ee7613dc501
Signed-off-by: Tibor Frank <tifrank@cisco.com>
---

diff --git a/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst b/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst
index 9dd2add5aa..8f5b807240 100644
--- a/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst
+++ b/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst
@@ -39,6 +39,10 @@ a.k.a. L3FWD data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst b/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst
index a673dc1318..32dec95c00 100644
--- a/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst
+++ b/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst
@@ -40,6 +40,10 @@ thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst b/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst
index 77ed39ad32..190aa3d6ac 100644
--- a/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst
+++ b/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst b/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst
index eeb4d652d5..143b864e8f 100644
--- a/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst
+++ b/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst
@@ -1,8 +1,4 @@
 
-.. raw:: latex
-
-    \clearpage
-
 .. raw:: html
 
     <script type="text/javascript">
@@ -40,6 +36,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/csit_release_notes.rst b/docs/report/vpp_performance_tests/csit_release_notes.rst
index 379072c119..831ee1b2c9 100644
--- a/docs/report/vpp_performance_tests/csit_release_notes.rst
+++ b/docs/report/vpp_performance_tests/csit_release_notes.rst
@@ -54,6 +54,10 @@ Changes in |csit-release|
    - **General Code Housekeeping**: Ongoing RF keywords optimizations,
      removal of redundant RF keywords.
 
+.. raw:: latex
+
+    \clearpage
+
 .. _vpp_known_issues:
 
 Known Issues
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
index 4c27c89b48..0199276303 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
@@ -40,6 +40,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/container_orchestrated.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/container_orchestrated.rst
index d746c53674..f975f2ddd0 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/container_orchestrated.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/container_orchestrated.rst
@@ -40,6 +40,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/kubernetes/perf/container_memif?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst
index a88e007464..08907610a7 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst
@@ -40,6 +40,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
index db0cfd0852..27e83c4359 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
@@ -40,6 +40,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
index 5ba63dc9de..0ad3e342c6 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
@@ -40,6 +40,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6_tunnels.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6_tunnels.rst
index a193e7913a..050ace5069 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6_tunnels.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6_tunnels.rst
@@ -40,6 +40,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6_tunnels?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ipsec.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ipsec.rst
index 3978a8c136..30363a73d2 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ipsec.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ipsec.rst
@@ -43,6 +43,10 @@ placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/crypto?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-xl710
 ~~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
index ca30ee470f..db767807f4 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
@@ -1,8 +1,4 @@
 
-.. raw:: latex
-
-    \clearpage
-
 .. raw:: html
 
     <script type="text/javascript">
@@ -40,6 +36,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst
index a070b8130a..3fa202bfd1 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst
@@ -40,6 +40,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/srv6?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst
index 1efd705e63..11072ccceb 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst
@@ -41,6 +41,10 @@ placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vm_vhost?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
index cc114bb8dc..26d1e6b201 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
@@ -41,6 +41,10 @@ placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vts?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/container_memif.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/container_memif.rst
index 47b7570154..5789f4458e 100644
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/container_memif.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/container_memif.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/container_orchestrated.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/container_orchestrated.rst
index 572ea5aef0..3b6bdfe6d7 100644
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/container_orchestrated.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/container_orchestrated.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/kubernetes/perf/container_memif?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4.rst
index 9aa1b10e3e..ece6bec0e6 100644
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4_tunnels.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4_tunnels.rst
index 4f24afe2b4..7a818d91c7 100644
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4_tunnels.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip4_tunnels.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6.rst
index ec02256e77..8a022907f9 100644
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6_tunnels.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6_tunnels.rst
index ca635a229c..cfd1be7eec 100644
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6_tunnels.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/ip6_tunnels.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6_tunnels?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/ipsec.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/ipsec.rst
index cc8e5c0972..3d61369ecb 100644
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/ipsec.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/ipsec.rst
@@ -43,6 +43,10 @@ physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/crypto?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-xl710
 ~~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/l2.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/l2.rst
index f6e422727a..d64cef192a 100644
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/l2.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/l2.rst
@@ -1,8 +1,4 @@
 
-.. raw:: latex
-
-    \clearpage
-
 .. raw:: html
 
     <script type="text/javascript">
@@ -40,6 +36,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/srv6.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/srv6.rst
index fd5c6f8e8f..5e11278df7 100644
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/srv6.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/srv6.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/srv6?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/vm_vhost.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/vm_vhost.rst
index 0b86d762a7..529b994b27 100644
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/vm_vhost.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/vm_vhost.rst
@@ -41,6 +41,10 @@ and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vm_vhost?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/vts.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/vts.rst
index 985057d194..b885fdc233 100644
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/vts.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/vts.rst
@@ -41,6 +41,10 @@ and their physical CPU core(s) placement.
 CSIT source code for the test cases used for plots can be found in
 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vts?h=rls1810>`_.
 
+.. raw:: latex
+
+    \clearpage
+
 3n-hsw-x520
 ~~~~~~~~~~~
 
diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/l2.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/l2.rst
index 55d45257f0..f866fbd6e7 100644
--- a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/l2.rst
+++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/l2.rst
@@ -1,8 +1,4 @@
 
-.. raw:: latex
-
-    \clearpage
-
 .. raw:: html
 
     <script type="text/javascript">