/*- * BSD LICENSE * * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * Neither the name of Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _I40E_RXTX_H_ #define _I40E_RXTX_H_ /** * 32 bits tx flags, high 16 bits for L2TAG1 (VLAN), * low 16 bits for others. */ #define I40E_TX_FLAG_L2TAG1_SHIFT 16 #define I40E_TX_FLAG_L2TAG1_MASK 0xffff0000 #define I40E_TX_FLAG_CSUM ((uint32_t)(1 << 0)) #define I40E_TX_FLAG_INSERT_VLAN ((uint32_t)(1 << 1)) #define I40E_TX_FLAG_TSYN ((uint32_t)(1 << 2)) #define RTE_PMD_I40E_RX_MAX_BURST 32 #define RTE_PMD_I40E_TX_MAX_BURST 32 #define RTE_I40E_VPMD_RX_BURST 32 #define RTE_I40E_VPMD_TX_BURST 32 #define RTE_I40E_RXQ_REARM_THRESH 32 #define RTE_I40E_MAX_RX_BURST RTE_I40E_RXQ_REARM_THRESH #define RTE_I40E_TX_MAX_FREE_BUF_SZ 64 #define RTE_I40E_DESCS_PER_LOOP 4 #define I40E_RXBUF_SZ_1024 1024 #define I40E_RXBUF_SZ_2048 2048 /* In none-PXE mode QLEN must be whole number of 32 descriptors. */ #define I40E_ALIGN_RING_DESC 32 #define I40E_MIN_RING_DESC 64 #define I40E_MAX_RING_DESC 4096 #undef container_of #define container_of(ptr, type, member) ({ \ typeof(((type *)0)->member)(*__mptr) = (ptr); \ (type *)((char *)__mptr - offsetof(type, member)); }) #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\ I40E_TX_DESC_CMD_EOP) enum i40e_header_split_mode { i40e_header_split_none = 0, i40e_header_split_enabled = 1, i40e_header_split_always = 2, i40e_header_split_reserved }; #define I40E_HEADER_SPLIT_NONE ((uint8_t)0) #define I40E_HEADER_SPLIT_L2 ((uint8_t)(1 << 0)) #define I40E_HEADER_SPLIT_IP ((uint8_t)(1 << 1)) #define I40E_HEADER_SPLIT_UDP_TCP ((uint8_t)(1 << 2)) #define I40E_HEADER_SPLIT_SCTP ((uint8_t)(1 << 3)) #define I40E_HEADER_SPLIT_ALL (I40E_HEADER_SPLIT_L2 | \ I40E_HEADER_SPLIT_IP | \ I40E_HEADER_SPLIT_UDP_TCP | \ I40E_HEADER_SPLIT_SCTP) /* HW desc structure, both 16-byte and 32-byte types are supported */ #ifdef RTE_LIBRTE_I40E_16BYTE_RX_DESC #define i40e_rx_desc i40e_16byte_rx_desc #else #define i40e_rx_desc i40e_32byte_rx_desc #endif struct i40e_rx_entry { struct rte_mbuf *mbuf; }; /* * Structure associated with each RX queue. */ struct i40e_rx_queue { struct rte_mempool *mp; /**< mbuf pool to populate RX ring */ volatile union i40e_rx_desc *rx_ring;/**< RX ring virtual address */ uint64_t rx_ring_phys_addr; /**< RX ring DMA address */ struct i40e_rx_entry *sw_ring; /**< address of RX soft ring */ uint16_t nb_rx_desc; /**< number of RX descriptors */ uint16_t rx_free_thresh; /**< max free RX desc to hold */ uint16_t rx_tail; /**< current value of tail */ uint16_t nb_rx_hold; /**< number of held free RX desc */ struct rte_mbuf *pkt_first_seg; /**< first segment of current packet */ struct rte_mbuf *pkt_last_seg; /**< last segment of current packet */ #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC uint16_t rx_nb_avail; /**< number of staged packets ready */ uint16_t rx_next_avail; /**< index of next staged packets */ uint16_t rx_free_trigger; /**< triggers rx buffer allocation */ struct rte_mbuf fake_mbuf; /**< dummy mbuf */ struct rte_mbuf *rx_stage[RTE_PMD_I40E_RX_MAX_BURST * 2]; #endif uint16_t rxrearm_nb; /**< number of remaining to be re-armed */ uint16_t rxrearm_start; /**< the idx we start the re-arming from */ uint64_t mbuf_initializer; /**< value to init mbufs */ uint8_t port_id; /**< device port ID */ uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise */ uint16_t queue_id; /**< RX queue index */ uint16_t reg_idx; /**< RX queue register index */ uint8_t drop_en; /**< if not 0, set register bit */ volatile uint8_t *qrx_tail; /**< register address of tail */ struct i40e_vsi *vsi; /**< the VSI this queue belongs to */ uint16_t rx_buf_len; /* The packet buffer size */ uint16_t rx_hdr_len; /* The header buffer size */ uint16_t max_pkt_len; /* Maximum packet length */ uint8_t hs_mode; /* Header Split mode */ bool q_set; /**< indicate if rx queue has been configured */ bool rx_deferred_start; /**< don't start this queue in dev start */ uint16_t rx_using_sse; /**