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;
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;   An edge router typically sits between two networks such as the provider
;   core network and the provider access network. A typical packet processing
;   pipeline for the downstream traffic (i.e. traffic from core to access
;   network) contains the following functional blocks: Packet RX & Routing,
;   Traffic management and Packet TX. The input packets are assumed to be
;   IPv4, while the output packets are Q-in-Q IPv4.
;
;  A simple implementation for this functional pipeline is presented below.
;
;                  Packet Rx &                Traffic Management               Packet Tx
;                   Routing                    (Pass-Through)                (Pass-Through)
;             _____________________  SWQ0  ______________________  SWQ4  _____________________
; RXQ0.0 --->|                     |----->|                      |----->|                     |---> TXQ0.0
;            |                     | SWQ1 |                      | SWQ5 |                     |
; RXQ1.0 --->|                     |----->|                      |----->|                     |---> TXQ1.0
;            |        (P1)         | SWQ2 |         (P2)         | SWQ6 |        (P3)         |
; RXQ2.0 --->|                     |----->|                      |----->|                     |---> TXQ2.0
;            |                     | SWQ3 |                      | SWQ7 |                     |
; RXQ3.0 --->|                     |----->|                      |----->|                     |---> TXQ3.0
;            |_____________________|      |______________________|      |_____________________|
;                       |                  |  ^  |  ^  |  ^  |  ^
;                       |                  |__|  |__|  |__|  |__|
;                       +--> SINK0          TM0   TM1   TM2   TM3
;                      (Default)
;
; Input packet: Ethernet/IPv4
; Output packet: Ethernet/QinQ/IPv4
;
; Packet buffer layout:
; #	Field Name		Offset (Bytes)	Size (Bytes)
; 0	Mbuf			0 		128
; 1	Headroom		128 		128
; 2	Ethernet header		256 		14
; 3	IPv4 header		270 		20

[EAL]
log_level = 0

[PIPELINE0]
type = MASTER
core = 0

[PIPELINE1]
type = ROUTING
core = 1
pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
pktq_out = SWQ0 SWQ1 SWQ2 SWQ3 SINK0
encap = ethernet_qinq
qinq_sched = test
ip_hdr_offset = 270

[PIPELINE2]
type = PASS-THROUGH
core = 2
pktq_in = SWQ0 SWQ1 SWQ2 SWQ3 TM0 TM1 TM2 TM3
pktq_out = TM0 TM1 TM2 TM3 SWQ4 SWQ5 SWQ6 SWQ7

[PIPELINE3]
type = PASS-THROUGH
core = 3
pktq_in = SWQ4 SWQ5 SWQ6 SWQ7
pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0

[MEMPOOL0]
pool_size = 2M