New upstream version 18.11-rc1

[deb_dpdk.git] / config / common_base

diff --git a/config/common_base b/config/common_base
index 4bcbaf9..d12ae98 100644 (file)
--- a/config/common_base
+++ b/config/common_base
@@ -55,12 +55,18 @@ CONFIG_RTE_MAJOR_ABI=
 #
 CONFIG_RTE_CACHE_LINE_SIZE=64
 
+#
+# Memory model
+#
+CONFIG_RTE_USE_C11_MEM_MODEL=n
+
 #
 # Compile Environment Abstraction Layer
 #
 CONFIG_RTE_LIBRTE_EAL=y
 CONFIG_RTE_MAX_LCORE=128
 CONFIG_RTE_MAX_NUMA_NODES=8
+CONFIG_RTE_MAX_HEAPS=32
 CONFIG_RTE_MAX_MEMSEG_LISTS=64
 # each memseg list will be limited to either RTE_MAX_MEMSEG_PER_LIST pages
 # or RTE_MAX_MEM_MB_PER_LIST megabytes worth of memory, whichever is smaller
@@ -128,7 +134,7 @@ CONFIG_RTE_MAX_QUEUES_PER_PORT=1024
 CONFIG_RTE_LIBRTE_IEEE1588=n
 CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS=16
 CONFIG_RTE_ETHDEV_RXTX_CALLBACKS=y
-CONFIG_RTE_ETHDEV_PROFILE_ITT_WASTED_RX_ITERATIONS=n
+CONFIG_RTE_ETHDEV_PROFILE_WITH_VTUNE=n
 
 #
 # Turn off Tx preparation stage
@@ -138,6 +144,11 @@ CONFIG_RTE_ETHDEV_PROFILE_ITT_WASTED_RX_ITERATIONS=n
 #
 CONFIG_RTE_ETHDEV_TX_PREPARE_NOOP=n
 
+#
+# Common libraries, before Bus/PMDs
+#
+CONFIG_RTE_LIBRTE_COMMON_DPAAX=n
+
 #
 # Compile the Intel FPGA bus
 #
@@ -163,6 +174,11 @@ CONFIG_RTE_LIBRTE_ARK_DEBUG_TX=n
 CONFIG_RTE_LIBRTE_ARK_DEBUG_STATS=n
 CONFIG_RTE_LIBRTE_ARK_DEBUG_TRACE=n
 
+#
+# Compile Aquantia Atlantic PMD driver
+#
+CONFIG_RTE_LIBRTE_ATLANTIC_PMD=y
+
 #
 # Compile AMD PMD
 #
@@ -217,6 +233,11 @@ CONFIG_RTE_LIBRTE_DPAA2_USE_PHYS_IOVA=y
 CONFIG_RTE_LIBRTE_DPAA2_PMD=n
 CONFIG_RTE_LIBRTE_DPAA2_DEBUG_DRIVER=n
 
+#
+# Compile NXP ENETC PMD Driver
+#
+CONFIG_RTE_LIBRTE_ENETC_PMD=n
+
 #
 # Compile burst-oriented Amazon ENA PMD driver
 #
@@ -399,6 +420,11 @@ CONFIG_RTE_LIBRTE_PMD_FAILSAFE=y
 #
 CONFIG_RTE_LIBRTE_MVPP2_PMD=n
 
+#
+# Compile Marvell MVNETA PMD driver
+#
+CONFIG_RTE_LIBRTE_MVNETA_PMD=n
+
 #
 # Compile support for VMBus library
 #
@@ -479,6 +505,12 @@ CONFIG_RTE_CRYPTO_MAX_DEVS=64
 CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO=n
 CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO_DEBUG=n
 
+#
+# Compile NXP CAAM JR crypto Driver
+#
+CONFIG_RTE_LIBRTE_PMD_CAAM_JR=n
+CONFIG_RTE_LIBRTE_PMD_CAAM_JR_BE=n
+
 #
 # Compile NXP DPAA2 crypto sec driver for CAAM HW
 #
@@ -490,6 +522,11 @@ CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=n
 CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=n
 CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
 
+#
+# Compile PMD for Cavium OCTEON TX crypto device
+#
+CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
+
 #
 # Compile PMD for QuickAssist based devices - see docs for details
 #
@@ -500,6 +537,7 @@ CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
 #
 CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48
 CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16
+CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536
 
 #
 # Compile PMD for virtio crypto devices
@@ -559,7 +597,6 @@ CONFIG_RTE_LIBRTE_PMD_CCP=n
 # Compile PMD for Marvell Crypto device
 #
 CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO=n
-CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO_DEBUG=n
 
 #
 # Compile generic security library
@@ -602,6 +639,7 @@ CONFIG_RTE_EVENT_MAX_QUEUES_PER_DEV=64
 CONFIG_RTE_EVENT_TIMER_ADAPTER_NUM_MAX=32
 CONFIG_RTE_EVENT_ETH_INTR_RING_SIZE=1024
 CONFIG_RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE=32
+CONFIG_RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE=32
 
 #
 # Compile PMD for skeleton event device
@@ -614,6 +652,11 @@ CONFIG_RTE_LIBRTE_PMD_SKELETON_EVENTDEV_DEBUG=n
 #
 CONFIG_RTE_LIBRTE_PMD_SW_EVENTDEV=y
 
+#
+# Compile PMD for distributed software event device
+#
+CONFIG_RTE_LIBRTE_PMD_DSW_EVENTDEV=y
+
 #
 # Compile PMD for octeontx sso event device
 #
@@ -661,7 +704,6 @@ CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y
 # Compile librte_ring
 #
 CONFIG_RTE_LIBRTE_RING=y
-CONFIG_RTE_RING_USE_C11_MEM_MODEL=n
 
 #
 # Compile librte_mempool
@@ -745,6 +787,11 @@ CONFIG_RTE_LIBRTE_BITRATE=y
 #
 CONFIG_RTE_LIBRTE_LATENCY_STATS=y
 
+#
+# Compile librte_telemetry
+#
+CONFIG_RTE_LIBRTE_TELEMETRY=n
+
 #
 # Compile librte_lpm
 #