New upstream version 18.02

[deb_dpdk.git] / drivers / crypto / qat / qat_crypto.h

diff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h
index 3f35a00..c182af2 100644 (file)
--- a/drivers/crypto/qat/qat_crypto.h
+++ b/drivers/crypto/qat/qat_crypto.h
@@ -1,34 +1,5 @@
-/*-
- *   BSD LICENSE
- *
- *   Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions
- *   are met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in
- *       the documentation and/or other materials provided with the
- *       distribution.
- *     * Neither the name of Intel Corporation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2016 Intel Corporation
  */
 
 #ifndef _QAT_CRYPTO_H_
@@ -50,6 +21,13 @@
        (((num) + (align) - 1) & ~((align) - 1))
 #define QAT_64_BTYE_ALIGN_MASK (~0x3f)
 
+#define QAT_CSR_HEAD_WRITE_THRESH 32U
+/* number of requests to accumulate before writing head CSR */
+#define QAT_CSR_TAIL_WRITE_THRESH 32U
+/* number of requests to accumulate before writing tail CSR */
+#define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U
+/* number of inflights below which no tail write coalescing should occur */
+
 struct qat_session;
 
 enum qat_device_gen {
@@ -63,7 +41,7 @@ enum qat_device_gen {
 struct qat_queue {
        char            memz_name[RTE_MEMZONE_NAMESIZE];
        void            *base_addr;             /* Base address */
-       phys_addr_t     base_phys_addr;         /* Queue physical address */
+       rte_iova_t      base_phys_addr;         /* Queue physical address */
        uint32_t        head;                   /* Shadow copy of the head */
        uint32_t        tail;                   /* Shadow copy of the tail */
        uint32_t        modulo;
@@ -73,11 +51,17 @@ struct qat_queue {
        uint8_t         hw_bundle_number;
        uint8_t         hw_queue_number;
        /* HW queue aka ring offset on bundle */
+       uint32_t        csr_head;               /* last written head value */
+       uint32_t        csr_tail;               /* last written tail value */
+       uint16_t        nb_processed_responses;
+       /* number of responses processed since last CSR head write */
+       uint16_t        nb_pending_requests;
+       /* number of requests pending since last CSR tail write */
 };
 
 struct qat_qp {
        void                    *mmap_bar_addr;
-       rte_atomic16_t          inflights16;
+       uint16_t                inflights16;
        struct  qat_queue       tx_q;
        struct  qat_queue       rx_q;
        struct  rte_cryptodev_stats stats;