#define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
/* RoCE slow path command */
#define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
+/* RoCE slow path command to query CC Gen1 support. */
+#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)
+/* RoCE slow path command to modify CC Gen1 support. */
+#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)
/* Engine CKV - The device's serial number. */
#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
/* Engine CKV - Per-function random nonce data. */
*/
uint16_t req_type;
#define HWRM_VER_GET UINT32_C(0x0)
+ #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
#define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
#define HWRM_FUNC_VF_CFG UINT32_C(0xf)
/* Reserved for future use. */
#define HWRM_RING_FREE UINT32_C(0x51)
#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
+ #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
#define HWRM_RING_RESET UINT32_C(0x5e)
#define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
#define HWRM_RING_GRP_FREE UINT32_C(0x61)
#define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
#define HWRM_FW_RESET UINT32_C(0xc0)
#define HWRM_FW_QSTATUS UINT32_C(0xc1)
+ #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
+ #define HWRM_FW_SYNC UINT32_C(0xc3)
/* Experimental */
#define HWRM_FW_SET_TIME UINT32_C(0xc8)
/* Experimental */
/* Experimental */
#define HWRM_FW_IPC_MSG UINT32_C(0x110)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
#define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
/* Experimental */
#define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
+ /* Configures the BW of any VF */
+ #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
+ /* Queries the BW of any VF */
+ #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
/* Experimental */
#define HWRM_SELFTEST_QLIST UINT32_C(0x200)
/* Experimental */
#define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
/* Experimental */
#define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
+ /* Experimental */
+ #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
/* */
#define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
+ /* */
+ #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
/* Experimental */
#define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
#define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
* should retry the request.
*/
#define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
+ /*
+ * This error code is only reported by firmware when some
+ * sub-option of a supported HWRM command is unsupported.
+ */
+ #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
/*
* Generic HWRM execution error that represents an
* internal error.
#define HWRM_VERSION_MINOR 9
#define HWRM_VERSION_UPDATE 2
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 9
-#define HWRM_VERSION_STR "1.9.2.9"
+#define HWRM_VERSION_RSVD 53
+#define HWRM_VERSION_STR "1.9.2.53"
/****************
* hwrm_ver_get *
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
UINT32_C(0x8)
+ /*
+ * If set to 1, then the KONG host mailbox channel is supported.
+ * If set to 0, then the KONG host mailbox channel is not supported.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
+ UINT32_C(0x10)
+ /*
+ * If set to 1, then the 64bit flow handle is supported in addition to the
+ * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
+ * supported. By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
+ UINT32_C(0x20)
+ /*
+ * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
+ * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
+ * If set to 0, then filter types not supported.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
+ UINT32_C(0x40)
+ /*
+ * If set to 1, firmware is capable to support virtio vSwitch offload model.
+ * If set to 0, firmware can't supported virtio vSwitch offload model.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
+ UINT32_C(0x80)
+ /*
+ * If set to 1, firmware is capable to support trusted VF.
+ * If set to 0, firmware is not capable to support trusted VF.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
+ UINT32_C(0x100)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
struct bd_base {
uint8_t type;
/* This value identifies the type of buffer descriptor. */
- #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
- #define BD_BASE_TYPE_SFT 0
+ #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
+ #define BD_BASE_TYPE_SFT 0
/*
* Indicates that this BD is 16B long and is used for
* normal L2 packet transmission.
*/
- #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
+ #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
/*
* Indicates that this BD is 1BB long and is an empty
* TX BD. Not valid for use by the driver.
*/
- #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
+ #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
/*
* Indicates that this BD is 16B long and is an RX Producer
* (ie. empty) buffer descriptor.
*/
- #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
+ #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
/*
* Indicates that this BD is 16B long and is an RX
* Producer Buffer BD.
*/
- #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
+ #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
/*
* Indicates that this BD is 16B long and is an
* RX Producer Assembly Buffer Descriptor.
*/
- #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
+ #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
/*
* Indicates that this BD is 32B long and is used for
* normal L2 packet transmission.
*/
- #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
- #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG
+ #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
+ /*
+ * Indicates that this BD is 32B long and is used for
+ * L2 packet transmission for small packets that require
+ * low latency.
+ */
+ #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
+ #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
uint8_t unused_1[7];
} __attribute__((packed));
uint64_t address;
} __attribute__((packed));
+/* Last 16 bytes of tx_bd_long. */
/* tx_bd_long_hi (size:128b/16B) */
struct tx_bd_long_hi {
/*
TX_BD_LONG_CFA_META_KEY_VLAN_TAG
} __attribute__((packed));
+/*
+ * This structure is used to inform the NIC of packet data that needs to be
+ * transmitted with additional processing that requires extra data such as
+ * VLAN insertion plus attached inline data. This BD type may be used to
+ * improve latency for small packets needing the additional extended features
+ * supported by long BDs.
+ */
+/* tx_bd_long_inline (size:256b/32B) */
+struct tx_bd_long_inline {
+ uint16_t flags_type;
+ /* This value identifies the type of buffer descriptor. */
+ #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
+ #define TX_BD_LONG_INLINE_TYPE_SFT 0
+ /*
+ * This type of BD is 32B long and is used for inline L2 packet
+ * transmission.
+ */
+ #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
+ #define TX_BD_LONG_INLINE_TYPE_LAST \
+ TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
+ /*
+ * All bits in this field may be set on the first BD of a packet.
+ * Only the packet_end bit may be set in non-first BDs.
+ */
+ #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
+ #define TX_BD_LONG_INLINE_FLAGS_SFT 6
+ /*
+ * If set to 1, the packet ends with the data in the buffer
+ * pointed to by this descriptor. This flag must be
+ * valid on every BD.
+ */
+ #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
+ /*
+ * If set to 1, the device will not generate a completion for
+ * this transmit packet unless there is an error in its processing.
+ * If this bit is set to 0, then the packet will be completed
+ * normally.
+ *
+ * This bit may be set only on the first BD of a packet.
+ */
+ #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
+ /*
+ * This value indicates how many 16B BD locations are consumed
+ * in the ring by this packet, including the BD and inline
+ * data.
+ */
+ #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
+ #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
+ /* This field is deprecated. */
+ #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
+ #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
+ /*
+ * If set to 1, the device immediately updates the Send Consumer
+ * Index after the buffer associated with this descriptor has
+ * been transferred via DMA to NIC memory from host memory. An
+ * interrupt may or may not be generated according to the state
+ * of the interrupt avoidance mechanisms. If this bit
+ * is set to 0, then the Consumer Index is only updated as soon
+ * as one of the host interrupt coalescing conditions has been met.
+ *
+ * This bit must be valid on the first BD of a packet.
+ */
+ #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
+ /*
+ * This is the length of the inline data, not including BD length, in
+ * bytes.
+ * The maximum value is 480.
+ *
+ * This field must be valid on all BDs of a packet.
+ */
+ uint16_t len;
+ /*
+ * The opaque data field is passed through to the completion and can be
+ * used for any data that the driver wants to associate with the transmit
+ * BD.
+ *
+ * This field must be valid on the first BD of a packet.
+ */
+ uint32_t opaque;
+ uint64_t unused1;
+ /*
+ * All bits in this field must be valid on the first BD of a packet.
+ * Their value on other BDs of the packet is ignored.
+ */
+ uint16_t lflags;
+ /*
+ * If set to 1, the controller replaces the TCP/UPD checksum
+ * fields of normal TCP/UPD checksum, or the inner TCP/UDP
+ * checksum field of the encapsulated TCP/UDP packets with the
+ * hardware calculated TCP/UDP checksum for the packet associated
+ * with this descriptor. The flag is ignored if the LSO flag is set.
+ */
+ #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
+ /*
+ * If set to 1, the controller replaces the IP checksum of the
+ * normal packets, or the inner IP checksum of the encapsulated
+ * packets with the hardware calculated IP checksum for the
+ * packet associated with this descriptor.
+ */
+ #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
+ /*
+ * If set to 1, the controller will not append an Ethernet CRC
+ * to the end of the frame.
+ *
+ * Packet must be 64B or longer when this flag is set. It is not
+ * useful to use this bit with any form of TX offload such as
+ * CSO or LSO. The intent is that the packet from the host already
+ * has a valid Ethernet CRC on the packet.
+ */
+ #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
+ /*
+ * If set to 1, the device will record the time at which the packet
+ * was actually transmitted at the TX MAC.
+ */
+ #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
+ /*
+ * If set to 1, the controller replaces the tunnel IP checksum
+ * field with hardware calculated IP checksum for the IP header
+ * of the packet associated with this descriptor. The hardware
+ * updates an outer UDP checksum if it is non-zero.
+ */
+ #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
+ /*
+ * This bit must be 0 for BDs of this type. LSO is not supported with
+ * inline BDs.
+ */
+ #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
+ /* Since LSO is not supported with inline BDs, this bit is not used. */
+ #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
+ /* Since LSO is not supported with inline BDs, this bit is not used. */
+ #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
+ /*
+ * If set to '1', then the RoCE ICRC will be appended to the
+ * packet. Packet must be a valid RoCE format packet.
+ */
+ #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
+ /*
+ * If set to '1', then the FCoE CRC will be appended to the
+ * packet. Packet must be a valid FCoE format packet.
+ */
+ #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
+ uint16_t unused2;
+ uint32_t unused3;
+ uint16_t unused4;
+ /*
+ * This value selects a CFA action to perform on the packet.
+ * Set this value to zero if no CFA action is desired.
+ *
+ * This value must be valid on the first BD of a packet.
+ */
+ uint16_t cfa_action;
+ /*
+ * This value is action meta-data that defines CFA edit operations
+ * that are done in addition to any action editing.
+ */
+ uint32_t cfa_meta;
+ /* When key = 1, this is the VLAN tag VID value. */
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
+ /* When key = 1, this is the VLAN tag DE value. */
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
+ /* When key = 1, this is the VLAN tag PRI value. */
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
+ /* When key = 1, this is the VLAN tag TPID select value. */
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
+ /* 0x88a8 */
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
+ (UINT32_C(0x0) << 16)
+ /* 0x8100 */
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
+ (UINT32_C(0x1) << 16)
+ /* 0x9100 */
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
+ (UINT32_C(0x2) << 16)
+ /* 0x9200 */
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
+ (UINT32_C(0x3) << 16)
+ /* 0x9300 */
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
+ (UINT32_C(0x4) << 16)
+ /* Value programmed in CFA VLANTPID register. */
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
+ (UINT32_C(0x5) << 16)
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
+ TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
+ UINT32_C(0xff80000)
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
+ /*
+ * This field identifies the type of edit to be performed
+ * on the packet.
+ *
+ * This value must be valid on the first BD of a packet.
+ */
+ #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
+ UINT32_C(0xf0000000)
+ #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
+ /* No editing */
+ #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
+ (UINT32_C(0x0) << 28)
+ /*
+ * - meta[17:16] - TPID select value (0 = 0x8100).
+ * - meta[15:12] - PRI/DE value.
+ * - meta[11:0] - VID value.
+ */
+ #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
+ (UINT32_C(0x1) << 28)
+ #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
+ TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
+} __attribute__((packed));
+
/* tx_bd_empty (size:128b/16B) */
struct tx_bd_empty {
/* This value identifies the type of buffer descriptor. */
uint32_t rss_hash;
} __attribute__((packed));
+/* Last 16 bytes of rx_pkt_cmpl. */
/* rx_pkt_cmpl_hi (size:128b/16B) */
struct rx_pkt_cmpl_hi {
uint32_t flags2;
uint32_t rss_hash;
} __attribute__((packed));
+/* Last 16 bytes of rx_tpq_start_cmpl. */
/* rx_tpa_start_cmpl_hi (size:128b/16B) */
struct rx_tpa_start_cmpl_hi {
uint32_t flags2;
uint32_t tsdelta;
} __attribute__((packed));
+/* Last 16 bytes of rx_tpa_end_cmpl. */
/* rx_tpa_end_cmpl_hi (size:128b/16B) */
struct rx_tpa_end_cmpl_hi {
/*
/* Port PHY configuration change */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
UINT32_C(0x7)
+ /* Reset notification to clients */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
+ UINT32_C(0x8)
/* Function driver unloaded */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
UINT32_C(0x10)
UINT32_C(0x40000)
} __attribute__((packed));
+/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
+struct hwrm_async_event_cmpl_reset_notify {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notify clients of imminent reset. */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
+ UINT32_C(0x8)
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates driver action requested */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
+ 0
+ /*
+ * If set to 1, it indicates that the l2 client should
+ * stop sending in band traffic to Nitro.
+ * if set to 0, there is no change in L2 client behavior.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, it indicates that the L2 client should
+ * bring down the interface.
+ * If set to 0, then there is no change in L2 client behavior.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
+ UINT32_C(0x2)
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
+ /* Indicates reason for reset. */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
+ 8
+ /* A management client has requested reset. */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
+ (UINT32_C(0x1) << 8)
+ /* A fatal firmware exception has occurred. */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
+ (UINT32_C(0x2) << 8)
+ /* A non-fatal firmware exception has occurred. */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
+ (UINT32_C(0x3) << 8)
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
+ /*
+ * Minimum time before driver should attempt access - units 100ms ticks.
+ * Range 0-65535
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
+ UINT32_C(0xffff0000)
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
+ 16
+} __attribute__((packed));
+
/* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
struct hwrm_async_event_cmpl_func_drvr_unload {
uint16_t type;
*/
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
UINT32_C(0x8)
+ /*
+ * If this bit is set to 1, then the value of trusted VF enable
+ * was changed on this VF.
+ * If set to 0, then this bit should be ignored.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
+ UINT32_C(0x10)
} __attribute__((packed));
/* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
UINT32_C(0x40000)
+ /*
+ * If the query is for a VF, then this flag shall be ignored.
+ * If this query is for a PF and this flag is set to 1, then
+ * the PF will know that the firmware has the capability to track
+ * the virtual link status.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
+ UINT32_C(0x80000)
+ /*
+ * If 1, then this function supports the push mode that uses
+ * write combine buffers and the long inline tx buffer descriptor.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
+ UINT32_C(0x100000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
*/
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
UINT32_C(0x20)
+ /*
+ * If the function that is being queried is a PF, then the HWRM shall
+ * set this field to 0 and the HWRM client shall ignore this field.
+ * If the function that is being queried is a VF, then the HWRM shall
+ * set this field to 1 if the queried VF is trusted, otherwise the HWRM
+ * shall set this field to 0.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
+ UINT32_C(0x40)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
*/
#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
UINT32_C(0x3)
- #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
+ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
/* Cache Line Size 64 bytes */
#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
UINT32_C(0x0)
UINT32_C(0x1)
#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
+ /* This value is the virtual link admin state setting. */
+ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
+ UINT32_C(0xc)
+ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
+ /* Admin link state is in forced down mode. */
+ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
+ (UINT32_C(0x0) << 2)
+ /* Admin link state is in forced up mode. */
+ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
+ (UINT32_C(0x1) << 2)
+ /* Admin link state is in auto mode - follows the physical link state. */
+ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
+ (UINT32_C(0x2) << 2)
+ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
+ HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
/* Reserved for future. */
#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
- UINT32_C(0xfc)
- #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 2
+ UINT32_C(0xf0)
+ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
/*
* The number of VFs that are allocated to the function.
* This is valid only on the PF with SR-IOV enabled.
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_func_vlan_qcfg *
- ***********************/
+/*****************
+ * hwrm_func_cfg *
+ *****************/
-/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
-struct hwrm_func_vlan_qcfg_input {
+/* hwrm_func_cfg_input (size:704b/88B) */
+struct hwrm_func_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
/*
* Function ID of the function that is being
* configured.
- * If set to 0xFF... (All Fs), then the configuration is
+ * If set to 0xFF... (All Fs), then the the configuration is
* for the requesting function.
*/
uint16_t fid;
- uint8_t unused_0[6];
-} __attribute__((packed));
-
-/* hwrm_func_vlan_qcfg_output (size:320b/40B) */
-struct hwrm_func_vlan_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * This field specifies how many NQs will be reserved for the PF.
+ * Remaining NQs that belong to the PF become available for VFs.
+ * Once a PF has created VFs, it cannot change how many NQs are
+ * reserved for itself (since the NQs must be contiguous in HW).
*/
- uint8_t valid;
- /* S-TAG VLAN identifier configured for the function. */
- uint16_t stag_vid;
- /* S-TAG PCP value configured for the function. */
- uint8_t stag_pcp;
- uint8_t unused_1;
+ uint16_t num_msix;
+ uint32_t flags;
/*
- * S-TAG TPID value configured for the function. This field is specified in
- * network byte order.
- */
- uint16_t stag_tpid;
- /* C-TAG VLAN identifier configured for the function. */
- uint16_t ctag_vid;
- /* C-TAG PCP value configured for the function. */
- uint8_t ctag_pcp;
- uint8_t unused_2;
- /*
- * C-TAG TPID value configured for the function. This field is specified in
- * network byte order.
- */
- uint16_t ctag_tpid;
- /* Future use. */
- uint32_t rsvd2;
- /* Future use. */
- uint32_t rsvd3;
- uint32_t unused_3;
-} __attribute__((packed));
-
-/**********************
- * hwrm_func_vlan_cfg *
- **********************/
-
-
-/* hwrm_func_vlan_cfg_input (size:384b/48B) */
-struct hwrm_func_vlan_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- /*
- * Function ID of the function that is being
- * configured.
- * If set to 0xFF... (All Fs), then the configuration is
- * for the requesting function.
- */
- uint16_t fid;
- uint8_t unused_0[2];
- uint32_t enables;
- /*
- * This bit must be '1' for the stag_vid field to be
- * configured.
- */
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
- /*
- * This bit must be '1' for the ctag_vid field to be
- * configured.
- */
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
- /*
- * This bit must be '1' for the stag_pcp field to be
- * configured.
- */
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
- /*
- * This bit must be '1' for the ctag_pcp field to be
- * configured.
- */
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
- /*
- * This bit must be '1' for the stag_tpid field to be
- * configured.
- */
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
- /*
- * This bit must be '1' for the ctag_tpid field to be
- * configured.
- */
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
- /* S-TAG VLAN identifier configured for the function. */
- uint16_t stag_vid;
- /* S-TAG PCP value configured for the function. */
- uint8_t stag_pcp;
- uint8_t unused_1;
- /*
- * S-TAG TPID value configured for the function. This field is specified in
- * network byte order.
- */
- uint16_t stag_tpid;
- /* C-TAG VLAN identifier configured for the function. */
- uint16_t ctag_vid;
- /* C-TAG PCP value configured for the function. */
- uint8_t ctag_pcp;
- uint8_t unused_2;
- /*
- * C-TAG TPID value configured for the function. This field is specified in
- * network byte order.
- */
- uint16_t ctag_tpid;
- /* Future use. */
- uint32_t rsvd1;
- /* Future use. */
- uint32_t rsvd2;
- uint8_t unused_3[4];
-} __attribute__((packed));
-
-/* hwrm_func_vlan_cfg_output (size:128b/16B) */
-struct hwrm_func_vlan_cfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/*****************
- * hwrm_func_cfg *
- *****************/
-
-
-/* hwrm_func_cfg_input (size:704b/88B) */
-struct hwrm_func_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- /*
- * Function ID of the function that is being
- * configured.
- * If set to 0xFF... (All Fs), then the the configuration is
- * for the requesting function.
- */
- uint16_t fid;
- /*
- * This field specifies how many NQs will be reserved for the PF.
- * Remaining NQs that belong to the PF become available for VFs.
- * Once a PF has created VFs, it cannot change how many NQs are
- * reserved for itself (since the NQs must be contiguous in HW).
- */
- uint16_t num_msix;
- uint32_t flags;
- /*
- * When this bit is '1', the function is disabled with
- * source MAC address check.
- * This is an anti-spoofing check. If this flag is set,
- * then the function shall be configured to disallow
- * transmission of frames with the source MAC address that
- * is configured for this function.
+ * When this bit is '1', the function is disabled with
+ * source MAC address check.
+ * This is an anti-spoofing check. If this flag is set,
+ * then the function shall be configured to disallow
+ * transmission of frames with the source MAC address that
+ * is configured for this function.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
UINT32_C(0x1)
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
UINT32_C(0x100000)
+ /*
+ * This configuration change can be initiated by a PF driver. This
+ * configuration request shall be targeted to a VF. From local host
+ * resident HWRM clients, only the parent PF driver shall be allowed
+ * to initiate this change on one of its children VFs. If this bit is
+ * set to 1, then the VF that is being configured is requested to be
+ * trusted. If this bit is set to 0, then the VF that is being configured
+ * is requested to be not trusted.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
+ UINT32_C(0x200000)
uint32_t enables;
/*
* This bit must be '1' for the mtu field to be
*/
#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
UINT32_C(0x200000)
+ /*
+ * This bit must be '1' for the link admin state field to be
+ * configured.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
+ UINT32_C(0x400000)
/*
* The maximum transmission unit of the function.
* The HWRM should make sure that the mtu of
*/
#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
UINT32_C(0x3)
- #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
+ #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
/* Cache Line Size 64 bytes */
#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
UINT32_C(0x0)
UINT32_C(0x1)
#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
+ /* This value is the virtual link admin state setting. */
+ #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
+ UINT32_C(0xc)
+ #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
+ /* Admin state is forced down. */
+ #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
+ (UINT32_C(0x0) << 2)
+ /* Admin state is forced up. */
+ #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
+ (UINT32_C(0x1) << 2)
+ /* Admin state is in auto mode - is to follow the physical link state. */
+ #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
+ (UINT32_C(0x2) << 2)
+ #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
+ HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
/* Reserved for future. */
#define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
- UINT32_C(0xfc)
- #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 2
+ UINT32_C(0xf0)
+ #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
/*
* The number of multicast filters that should
* be reserved for this function on the RX side.
uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_func_vf_vnic_ids_query *
- *******************************/
+/**********************
+ * hwrm_func_drv_rgtr *
+ **********************/
-/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
-struct hwrm_func_vf_vnic_ids_query_input {
+/* hwrm_func_drv_rgtr_input (size:896b/112B) */
+struct hwrm_func_drv_rgtr_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ uint32_t flags;
/*
- * This value is used to identify a Virtual Function (VF).
- * The scope of VF ID is local within a PF.
+ * When this bit is '1', the function driver is requesting
+ * all requests from its children VF drivers to be
+ * forwarded to itself.
+ * This flag can only be set by the PF driver.
+ * If a VF driver sets this flag, it should be ignored
+ * by the HWRM.
*/
- uint16_t vf_id;
- uint8_t unused_0[2];
- /* Max number of vnic ids in vnic id table */
- uint32_t max_vnic_id_cnt;
- /* This is the address for VF VNIC ID table */
- uint64_t vnic_id_tbl_addr;
-} __attribute__((packed));
-
-/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
-struct hwrm_func_vf_vnic_ids_query_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
+ UINT32_C(0x1)
/*
- * Actual number of vnic ids
- *
- * Each VNIC ID is written as a 32-bit number.
+ * When this bit is '1', the function is requesting none of
+ * the requests from its children VF drivers to be
+ * forwarded to itself.
+ * This flag can only be set by the PF driver.
+ * If a VF driver sets this flag, it should be ignored
+ * by the HWRM.
*/
- uint32_t vnic_id_cnt;
- uint8_t unused_0[3];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/**********************
- * hwrm_func_drv_rgtr *
- **********************/
-
-
-/* hwrm_func_drv_rgtr_input (size:896b/112B) */
-struct hwrm_func_drv_rgtr_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- uint32_t flags;
- /*
- * When this bit is '1', the function driver is requesting
- * all requests from its children VF drivers to be
- * forwarded to itself.
- * This flag can only be set by the PF driver.
- * If a VF driver sets this flag, it should be ignored
- * by the HWRM.
- */
- #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1)
- /*
- * When this bit is '1', the function is requesting none of
- * the requests from its children VF drivers to be
- * forwarded to itself.
- * This flag can only be set by the PF driver.
- * If a VF driver sets this flag, it should be ignored
- * by the HWRM.
- */
- #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2)
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
+ UINT32_C(0x2)
/*
* When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
* fields shall be ignored and ver_maj, ver_min, ver_upd
* fields shall be used for the driver version information and
* ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
*/
- #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE UINT32_C(0x4)
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
+ UINT32_C(0x4)
+ /*
+ * When this bit is '1', the function is indicating support of
+ * 64bit flow handle. The firmware that only supports 64bit flow
+ * handle should check this bit before allowing processing of
+ * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
+ * with 64bit flow handle support can only be compatible with drivers
+ * that support 64bit flow handle. The legacy drivers that don't support
+ * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
+ * running with new firmware that only supports 64bit flow handle. The new
+ * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
+ * status to the legacy driver when encounters these commands.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
+ UINT32_C(0x8)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ uint32_t flags;
+ /*
+ * When this bit is '1', it indicates that the
+ * HWRM_FUNC_DRV_IF_CHANGE call is supported.
+ */
+ #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
+ UINT32_C(0x1)
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t unused_0[2];
} __attribute__((packed));
-/* hwrm_func_drv_qver_output (size:192b/24B) */
+/* hwrm_func_drv_qver_output (size:256b/32B) */
struct hwrm_func_drv_qver_output {
/* The specific error status for the command. */
uint16_t error_code;
uint8_t ver_min_8b;
/* This is the 8bit update version of the driver. */
uint8_t ver_upd_8b;
- uint8_t unused_0[2];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
+ uint8_t unused_0[3];
/* This is the 16bit major version of the driver. */
uint16_t ver_maj;
/* This is the 16bit minor version of the driver. */
uint16_t ver_upd;
/* This is the 16bit patch version of the driver. */
uint16_t ver_patch;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
} __attribute__((packed));
/****************************
* The number of TX rings assigned to the function cannot exceed this value.
*/
uint16_t max_tx_scheduler_inputs;
- uint8_t unused_0[7];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/*****************************
- * hwrm_func_vf_resource_cfg *
- *****************************/
-
-
-/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
-struct hwrm_func_vf_resource_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
+ uint16_t flags;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
+ * feature to reserve all minimum resources when minimum >= 1, otherwise
+ * returns an error.
*/
- uint64_t resp_addr;
- /* VF ID that is being configured by PF */
- uint16_t vf_id;
- /* Maximum guaranteed number of MSI-X vectors for the function */
- uint16_t max_msix;
- /* Minimum guaranteed number of RSS/COS contexts */
- uint16_t min_rsscos_ctx;
- /* Maximum non-guaranteed number of RSS/COS contexts */
- uint16_t max_rsscos_ctx;
- /* Minimum guaranteed number of completion rings */
- uint16_t min_cmpl_rings;
- /* Maximum non-guaranteed number of completion rings */
- uint16_t max_cmpl_rings;
- /* Minimum guaranteed number of transmit rings */
- uint16_t min_tx_rings;
- /* Maximum non-guaranteed number of transmit rings */
- uint16_t max_tx_rings;
- /* Minimum guaranteed number of receive rings */
- uint16_t min_rx_rings;
- /* Maximum non-guaranteed number of receive rings */
- uint16_t max_rx_rings;
- /* Minimum guaranteed number of L2 contexts */
- uint16_t min_l2_ctxs;
- /* Maximum non-guaranteed number of L2 contexts */
- uint16_t max_l2_ctxs;
- /* Minimum guaranteed number of VNICs */
- uint16_t min_vnics;
- /* Maximum non-guaranteed number of VNICs */
- uint16_t max_vnics;
- /* Minimum guaranteed number of statistic contexts */
- uint16_t min_stat_ctx;
- /* Maximum non-guaranteed number of statistic contexts */
- uint16_t max_stat_ctx;
- /* Minimum guaranteed number of ring groups */
- uint16_t min_hw_ring_grps;
- /* Maximum non-guaranteed number of ring groups */
- uint16_t max_hw_ring_grps;
- uint8_t unused_0[4];
-} __attribute__((packed));
-
-/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
-struct hwrm_func_vf_resource_cfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* Reserved number of RSS/COS contexts */
- uint16_t reserved_rsscos_ctx;
- /* Reserved number of completion rings */
- uint16_t reserved_cmpl_rings;
- /* Reserved number of transmit rings */
- uint16_t reserved_tx_rings;
- /* Reserved number of receive rings */
- uint16_t reserved_rx_rings;
- /* Reserved number of L2 contexts */
- uint16_t reserved_l2_ctxs;
- /* Reserved number of VNICs */
- uint16_t reserved_vnics;
- /* Reserved number of statistic contexts */
- uint16_t reserved_stat_ctx;
- /* Reserved number of ring groups */
- uint16_t reserved_hw_ring_grps;
- uint8_t unused_0[7];
+ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
+ UINT32_C(0x1)
+ uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint64_t resp_addr;
} __attribute__((packed));
-/* hwrm_func_backing_store_qcaps_output (size:512b/64B) */
+/* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
struct hwrm_func_backing_store_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
uint32_t stat_max_entries;
/* Number of bytes that must be allocated for each context entry. */
uint16_t stat_entry_size;
- /* Maximum number of TQM context entries supported per ring. */
- uint16_t tqm_max_entries_per_ring;
/* Number of bytes that must be allocated for each context entry. */
uint16_t tqm_entry_size;
- /* Number of bytes that must be allocated for each context entry. */
- uint16_t mrav_entry_size;
+ /* Minimum number of TQM context entries required per ring. */
+ uint32_t tqm_min_entries_per_ring;
+ /*
+ * Maximum number of TQM context entries supported per ring. This is
+ * actually a recommended TQM queue size based on worst case usage of
+ * the TQM queue.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * TQM slowpath rings should be sized as follows:
+ *
+ * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
+ *
+ * Where:
+ * num_vnics is the number of VNICs allocated in the VNIC backing store
+ * num_l2_tx_rings is the number of L2 rings in the QP backing store
+ * num_roce_qps is the number of RoCE QPs in the QP backing store
+ * tqm_min_size is tqm_min_entries_per_ring reported by
+ * HWRM_FUNC_BACKING_STORE_QCAPS
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
+ * the backing store.
+ */
+ uint32_t tqm_max_entries_per_ring;
/* Maximum number of MR/AV context entries supported for this function. */
uint32_t mrav_max_entries;
- /* Maximum number of Timer context entries supported for this function. */
- uint32_t tim_max_entries;
+ /* Number of bytes that must be allocated for each context entry. */
+ uint16_t mrav_entry_size;
/* Number of bytes that must be allocated for each context entry. */
uint16_t tim_entry_size;
- uint8_t unused_0;
+ /* Maximum number of Timer context entries supported for this function. */
+ uint32_t tim_max_entries;
+ uint8_t unused_0[2];
+ /*
+ * The number of entries specified for any TQM ring must be a
+ * multiple of this value to prevent any resource allocation
+ * limitations.
+ */
+ uint8_t tqm_entries_multiple;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint32_t cq_num_entries;
/* Number of Stats. */
uint32_t stat_num_entries;
- /* Number of TQM slowpath entries. */
+ /*
+ * Number of TQM slowpath entries.
+ *
+ * TQM slowpath rings should be sized as follows:
+ *
+ * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
+ *
+ * Where:
+ * num_vnics is the number of VNICs allocated in the VNIC backing store
+ * num_l2_tx_rings is the number of L2 rings in the QP backing store
+ * num_roce_qps is the number of RoCE QPs in the QP backing store
+ * tqm_min_size is tqm_min_entries_per_ring reported by
+ * HWRM_FUNC_BACKING_STORE_QCAPS
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
+ * the backing store.
+ */
uint32_t tqm_sp_num_entries;
- /* Number of TQM ring 0 entries. */
+ /*
+ * Number of TQM ring 0 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
+ * the backing store.
+ */
uint32_t tqm_ring0_num_entries;
- /* Number of TQM ring 1 entries. */
+ /*
+ * Number of TQM ring 1 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
+ * the backing store.
+ */
uint32_t tqm_ring1_num_entries;
- /* Number of TQM ring 2 entries. */
+ /*
+ * Number of TQM ring 2 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
+ * the backing store.
+ */
uint32_t tqm_ring2_num_entries;
- /* Number of TQM ring 3 entries. */
+ /*
+ * Number of TQM ring 3 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
+ * the backing store.
+ */
uint32_t tqm_ring3_num_entries;
- /* Number of TQM ring 4 entries. */
+ /*
+ * Number of TQM ring 4 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
+ * the backing store.
+ */
uint32_t tqm_ring4_num_entries;
- /* Number of TQM ring 5 entries. */
+ /*
+ * Number of TQM ring 5 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
+ * the backing store.
+ */
uint32_t tqm_ring5_num_entries;
- /* Number of TQM ring 6 entries. */
+ /*
+ * Number of TQM ring 6 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
+ * the backing store.
+ */
uint32_t tqm_ring6_num_entries;
- /* Number of TQM ring 7 entries. */
+ /*
+ * Number of TQM ring 7 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
+ * the backing store.
+ */
uint32_t tqm_ring7_num_entries;
/* Number of MR/AV entries. */
uint32_t mrav_num_entries;
uint8_t valid;
} __attribute__((packed));
-/*********************
- * hwrm_port_phy_cfg *
- *********************/
+/***********************
+ * hwrm_func_vlan_qcfg *
+ ***********************/
-/* hwrm_port_phy_cfg_input (size:448b/56B) */
-struct hwrm_port_phy_cfg_input {
+/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
+struct hwrm_func_vlan_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
/*
- * When this bit is set to '1', the PHY for the port shall
- * be reset.
- *
- * # If this bit is set to 1, then the HWRM shall reset the
- * PHY after applying PHY configuration changes specified
- * in this command.
- * # In order to guarantee that PHY configuration changes
- * specified in this command take effect, the HWRM
- * client should set this flag to 1.
- * # If this bit is not set to 1, then the HWRM may reset
- * the PHY depending on the current PHY configuration and
- * settings specified in this command.
- */
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
- UINT32_C(0x1)
- /* deprecated bit. Do not use!!! */
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
- UINT32_C(0x2)
- /*
- * When this bit is set to '1', the link shall be forced to
- * the force_link_speed value.
- *
- * When this bit is set to '1', the HWRM client should
- * not enable any of the auto negotiation related
- * fields represented by auto_XXX fields in this command.
- * When this bit is set to '1' and the HWRM client has
- * enabled a auto_XXX field in this command, then the
- * HWRM shall ignore the enabled auto_XXX field.
- *
- * When this bit is set to zero, the link
- * shall be allowed to autoneg.
- */
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
- UINT32_C(0x4)
- /*
- * When this bit is set to '1', the auto-negotiation process
- * shall be restarted on the link.
- */
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
- UINT32_C(0x8)
- /*
- * When this bit is set to '1', Energy Efficient Ethernet
- * (EEE) is requested to be enabled on this link.
- * If EEE is not supported on this port, then this flag
- * shall be ignored by the HWRM.
- */
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
- UINT32_C(0x10)
- /*
- * When this bit is set to '1', Energy Efficient Ethernet
- * (EEE) is requested to be disabled on this link.
- * If EEE is not supported on this port, then this flag
- * shall be ignored by the HWRM.
- */
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
- UINT32_C(0x20)
- /*
- * When this bit is set to '1' and EEE is enabled on this
- * link, then TX LPI is requested to be enabled on the link.
- * If EEE is not supported on this port, then this flag
- * shall be ignored by the HWRM.
- * If EEE is disabled on this port, then this flag shall be
- * ignored by the HWRM.
- */
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
- UINT32_C(0x40)
- /*
- * When this bit is set to '1' and EEE is enabled on this
- * link, then TX LPI is requested to be disabled on the link.
- * If EEE is not supported on this port, then this flag
- * shall be ignored by the HWRM.
- * If EEE is disabled on this port, then this flag shall be
- * ignored by the HWRM.
+ * Function ID of the function that is being
+ * configured.
+ * If set to 0xFF... (All Fs), then the configuration is
+ * for the requesting function.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
- UINT32_C(0x80)
+ uint16_t fid;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_func_vlan_qcfg_output (size:320b/40B) */
+struct hwrm_func_vlan_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint64_t unused_0;
+ /* S-TAG VLAN identifier configured for the function. */
+ uint16_t stag_vid;
+ /* S-TAG PCP value configured for the function. */
+ uint8_t stag_pcp;
+ uint8_t unused_1;
/*
- * When set to 1, then the HWRM shall enable FEC autonegotitation
- * on this port if supported.
- * When set to 0, then this flag shall be ignored.
- * If FEC autonegotiation is not supported, then the HWRM shall ignore this
- * flag.
+ * S-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
- UINT32_C(0x100)
+ uint16_t stag_tpid;
+ /* C-TAG VLAN identifier configured for the function. */
+ uint16_t ctag_vid;
+ /* C-TAG PCP value configured for the function. */
+ uint8_t ctag_pcp;
+ uint8_t unused_2;
/*
- * When set to 1, then the HWRM shall disable FEC autonegotiation
- * on this port if supported.
- * When set to 0, then this flag shall be ignored.
- * If FEC autonegotiation is not supported, then the HWRM shall ignore this
- * flag.
+ * C-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
- UINT32_C(0x200)
+ uint16_t ctag_tpid;
+ /* Future use. */
+ uint32_t rsvd2;
+ /* Future use. */
+ uint32_t rsvd3;
+ uint8_t unused_3[3];
/*
- * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
- * on this port if supported.
- * When set to 0, then this flag shall be ignored.
- * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
- * flag.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
- UINT32_C(0x400)
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_func_vlan_cfg *
+ **********************/
+
+
+/* hwrm_func_vlan_cfg_input (size:384b/48B) */
+struct hwrm_func_vlan_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
- * on this port if supported.
- * When set to 0, then this flag shall be ignored.
- * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
- * flag.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
- UINT32_C(0x800)
+ uint16_t cmpl_ring;
/*
- * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
- * on this port if supported.
- * When set to 0, then this flag shall be ignored.
- * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
- * flag.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
- UINT32_C(0x1000)
+ uint16_t seq_id;
/*
- * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
- * on this port if supported.
- * When set to 0, then this flag shall be ignored.
- * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
- * flag.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
- UINT32_C(0x2000)
+ uint16_t target_id;
/*
- * When this bit is set to '1', the link shall be forced to
- * be taken down.
- *
- * # When this bit is set to '1", all other
- * command input settings related to the link speed shall
- * be ignored.
- * Once the link state is forced down, it can be
- * explicitly cleared from that state by setting this flag
- * to '0'.
- * # If this flag is set to '0', then the link shall be
- * cleared from forced down state if the link is in forced
- * down state.
- * There may be conditions (e.g. out-of-band or sideband
- * configuration changes for the link) outside the scope
- * of the HWRM implementation that may clear forced down
- * link state.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
- UINT32_C(0x4000)
- uint32_t enables;
+ uint64_t resp_addr;
/*
- * This bit must be '1' for the auto_mode field to be
+ * Function ID of the function that is being
* configured.
+ * If set to 0xFF... (All Fs), then the configuration is
+ * for the requesting function.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
- UINT32_C(0x1)
+ uint16_t fid;
+ uint8_t unused_0[2];
+ uint32_t enables;
/*
- * This bit must be '1' for the auto_duplex field to be
+ * This bit must be '1' for the stag_vid field to be
* configured.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
- UINT32_C(0x2)
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
/*
- * This bit must be '1' for the auto_pause field to be
+ * This bit must be '1' for the ctag_vid field to be
* configured.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
- UINT32_C(0x4)
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
/*
- * This bit must be '1' for the auto_link_speed field to be
+ * This bit must be '1' for the stag_pcp field to be
* configured.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
- UINT32_C(0x8)
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
/*
- * This bit must be '1' for the auto_link_speed_mask field to be
+ * This bit must be '1' for the ctag_pcp field to be
* configured.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
- UINT32_C(0x10)
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
/*
- * This bit must be '1' for the wirespeed field to be
+ * This bit must be '1' for the stag_tpid field to be
* configured.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
- UINT32_C(0x20)
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
/*
- * This bit must be '1' for the lpbk field to be
+ * This bit must be '1' for the ctag_tpid field to be
* configured.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
- UINT32_C(0x40)
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
+ /* S-TAG VLAN identifier configured for the function. */
+ uint16_t stag_vid;
+ /* S-TAG PCP value configured for the function. */
+ uint8_t stag_pcp;
+ uint8_t unused_1;
/*
- * This bit must be '1' for the preemphasis field to be
- * configured.
+ * S-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
- UINT32_C(0x80)
- /*
- * This bit must be '1' for the force_pause field to be
- * configured.
- */
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
- UINT32_C(0x100)
+ uint16_t stag_tpid;
+ /* C-TAG VLAN identifier configured for the function. */
+ uint16_t ctag_vid;
+ /* C-TAG PCP value configured for the function. */
+ uint8_t ctag_pcp;
+ uint8_t unused_2;
/*
- * This bit must be '1' for the eee_link_speed_mask field to be
- * configured.
+ * C-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
- UINT32_C(0x200)
+ uint16_t ctag_tpid;
+ /* Future use. */
+ uint32_t rsvd1;
+ /* Future use. */
+ uint32_t rsvd2;
+ uint8_t unused_3[4];
+} __attribute__((packed));
+
+/* hwrm_func_vlan_cfg_output (size:128b/16B) */
+struct hwrm_func_vlan_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * This bit must be '1' for the tx_lpi_timer field to be
- * configured.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
- UINT32_C(0x400)
- /* Port ID of port that is to be configured. */
- uint16_t port_id;
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_func_vf_vnic_ids_query *
+ *******************************/
+
+
+/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
+struct hwrm_func_vf_vnic_ids_query_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This is the speed that will be used if the force
- * bit is '1'. If unsupported speed is selected, an error
- * will be generated.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t force_link_speed;
- /* 100Mb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
- /* 1Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
- /* 20Mb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
- /* 10Mb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
- HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
+ uint16_t cmpl_ring;
/*
- * This value is used to identify what autoneg mode is
- * used when the link speed is not being forced.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t auto_mode;
- /* Disable autoneg or autoneg disabled. No speeds are selected. */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
- /* Select all possible speeds for autoneg mode. */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
+ uint16_t seq_id;
/*
- * Select only the auto_link_speed speed for autoneg mode. This mode has
- * been DEPRECATED. An HWRM client should not use this mode.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
+ uint16_t target_id;
/*
- * Select the auto_link_speed or any speed below that speed for autoneg.
- * This mode has been DEPRECATED. An HWRM client should not use this mode.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
+ uint64_t resp_addr;
/*
- * Select the speeds based on the corresponding link speed mask value
- * that is provided.
+ * This value is used to identify a Virtual Function (VF).
+ * The scope of VF ID is local within a PF.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
- HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
+ uint16_t vf_id;
+ uint8_t unused_0[2];
+ /* Max number of vnic ids in vnic id table */
+ uint32_t max_vnic_id_cnt;
+ /* This is the address for VF VNIC ID table */
+ uint64_t vnic_id_tbl_addr;
+} __attribute__((packed));
+
+/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
+struct hwrm_func_vf_vnic_ids_query_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
/*
- * This is the duplex setting that will be used if the autoneg_mode
- * is "one_speed" or "one_or_below".
+ * Actual number of vnic ids
+ *
+ * Each VNIC ID is written as a 32-bit number.
*/
- uint8_t auto_duplex;
- /* Half Duplex will be requested. */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
- /* Full duplex will be requested. */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
- /* Both Half and Full dupex will be requested. */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
- HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
+ uint32_t vnic_id_cnt;
+ uint8_t unused_0[3];
/*
- * This value is used to configure the pause that will be
- * used for autonegotiation.
- * Add text on the usage of auto_pause and force_pause.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t auto_pause;
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_func_vf_bw_cfg *
+ ***********************/
+
+
+/* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
+struct hwrm_func_vf_bw_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * When this bit is '1', Generation of tx pause messages
- * has been requested. Disabled otherwise.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
- UINT32_C(0x1)
+ uint16_t cmpl_ring;
/*
- * When this bit is '1', Reception of rx pause messages
- * has been requested. Disabled otherwise.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
- UINT32_C(0x2)
+ uint16_t seq_id;
/*
- * When set to 1, the advertisement of pause is enabled.
- *
- * # When the auto_mode is not set to none and this flag is
- * set to 1, then the auto_pause bits on this port are being
- * advertised and autoneg pause results are being interpreted.
- * # When the auto_mode is not set to none and this
- * flag is set to 0, the pause is forced as indicated in
- * force_pause, and also advertised as auto_pause bits, but
- * the autoneg results are not interpreted since the pause
- * configuration is being forced.
- * # When the auto_mode is set to none and this flag is set to
- * 1, auto_pause bits should be ignored and should be set to 0.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
- UINT32_C(0x4)
- uint8_t unused_0;
+ uint16_t target_id;
/*
- * This is the speed that will be used if the autoneg_mode
- * is "one_speed" or "one_or_below". If an unsupported speed
- * is selected, an error will be generated.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t auto_link_speed;
- /* 100Mb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
- /* 1Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
- /* 20Mb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
- /* 10Mb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
- HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
+ uint64_t resp_addr;
/*
- * This is a mask of link speeds that will be used if
- * autoneg_mode is "mask". If unsupported speed is enabled
- * an error will be generated.
+ * The number of VF functions that are being configured.
+ * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
*/
- uint16_t auto_link_speed_mask;
- /* 100Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
- UINT32_C(0x2)
- /* 1Gb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
- UINT32_C(0x8)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
- UINT32_C(0x10)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
- UINT32_C(0x40)
- /* 20Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
- UINT32_C(0x80)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
- UINT32_C(0x100)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
- UINT32_C(0x200)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
- UINT32_C(0x400)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
- UINT32_C(0x800)
- /* 10Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
- UINT32_C(0x1000)
- /* 10Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
- UINT32_C(0x2000)
- /* This value controls the wirespeed feature. */
- uint8_t wirespeed;
- /* Wirespeed feature is disabled. */
- #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
- /* Wirespeed feature is enabled. */
- #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
- #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
- HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
- /* This value controls the loopback setting for the PHY. */
- uint8_t lpbk;
- /* No loopback is selected. Normal operation. */
- #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
- /*
- * The HW will be configured with local loopback such that
- * host data is sent back to the host without modification.
- */
- #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
- /*
- * The HW will be configured with remote loopback such that
- * port logic will send packets back out the transmitter that
- * are received.
- */
- #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
- /*
- * The HW will be configured with external loopback such that
- * host data is sent on the trasmitter and based on the external
- * loopback connection the data will be received without modification.
- */
- #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
- #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
- HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
+ uint16_t num_vfs;
+ uint16_t unused[3];
+ /* These 16-bit fields contain the VF fid and the rate scale percentage. */
+ uint16_t vfn[48];
+ /* The physical VF id the adjustment will be made to. */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
+ /*
+ * This field configures the rate scale percentage of the VF as specified
+ * by the physical VF id.
+ */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
+ /* 0% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
+ (UINT32_C(0x0) << 12)
+ /* 6.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
+ (UINT32_C(0x1) << 12)
+ /* 13.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
+ (UINT32_C(0x2) << 12)
+ /* 20% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
+ (UINT32_C(0x3) << 12)
+ /* 26.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
+ (UINT32_C(0x4) << 12)
+ /* 33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
+ (UINT32_C(0x5) << 12)
+ /* 40% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
+ (UINT32_C(0x6) << 12)
+ /* 46.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
+ (UINT32_C(0x7) << 12)
+ /* 53.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
+ (UINT32_C(0x8) << 12)
+ /* 60% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
+ (UINT32_C(0x9) << 12)
+ /* 66.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
+ (UINT32_C(0xa) << 12)
+ /* 53.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
+ (UINT32_C(0xb) << 12)
+ /* 80% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
+ (UINT32_C(0xc) << 12)
+ /* 86.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
+ (UINT32_C(0xd) << 12)
+ /* 93.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
+ (UINT32_C(0xe) << 12)
+ /* 100% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
+ (UINT32_C(0xf) << 12)
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
+ HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
+} __attribute__((packed));
+
+/* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
+struct hwrm_func_vf_bw_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * This value is used to configure the pause that will be
- * used for force mode.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t force_pause;
+ uint8_t valid;
+} __attribute__((packed));
+
+/************************
+ * hwrm_func_vf_bw_qcfg *
+ ************************/
+
+
+/* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
+struct hwrm_func_vf_bw_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * When this bit is '1', Generation of tx pause messages
- * is supported. Disabled otherwise.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
+ uint16_t cmpl_ring;
/*
- * When this bit is '1', Reception of rx pause messages
- * is supported. Disabled otherwise.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
- uint8_t unused_1;
+ uint16_t seq_id;
/*
- * This value controls the pre-emphasis to be used for the
- * link. Driver should not set this value (use
- * enable.preemphasis = 0) unless driver is sure of setting.
- * Normally HWRM FW will determine proper pre-emphasis.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint32_t preemphasis;
+ uint16_t target_id;
/*
- * Setting for link speed mask that is used to
- * advertise speeds during autonegotiation when EEE is enabled.
- * This field is valid only when EEE is enabled.
- * The speeds specified in this field shall be a subset of
- * speeds specified in auto_link_speed_mask.
- * If EEE is enabled,then at least one speed shall be provided
- * in this mask.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t eee_link_speed_mask;
- /* Reserved */
- #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
- UINT32_C(0x2)
- /* Reserved */
- #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
- UINT32_C(0x8)
- /* Reserved */
- #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
- UINT32_C(0x10)
- /* Reserved */
- #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
- UINT32_C(0x40)
- uint8_t unused_2[2];
+ uint64_t resp_addr;
/*
- * Reuested setting of TX LPI timer in microseconds.
- * This field is valid only when EEE is enabled and TX LPI is
- * enabled.
+ * The number of VF functions that are being queried.
+ * The inline response space allows the host to query up to 50 VFs'
+ * rate scale percentage
*/
- uint32_t tx_lpi_timer;
- #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
- #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
- uint32_t unused_3;
+ uint16_t num_vfs;
+ uint16_t unused[3];
+ /* These 16-bit fields contain the VF fid */
+ uint16_t vfn[48];
+ /* The physical VF id of interest */
+ #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
+ #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
} __attribute__((packed));
-/* hwrm_port_phy_cfg_output (size:128b/16B) */
-struct hwrm_port_phy_cfg_output {
+/* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
+struct hwrm_func_vf_bw_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ /*
+ * The number of VF functions that are being queried.
+ * The inline response space allows the host to query up to 50 VFs' rate
+ * scale percentage
+ */
+ uint16_t num_vfs;
+ uint16_t unused[3];
+ /* These 16-bit fields contain the VF fid and the rate scale percentage. */
+ uint16_t vfn[48];
+ /* The physical VF id the adjustment will be made to. */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
+ /*
+ * This field configures the rate scale percentage of the VF as specified
+ * by the physical VF id.
+ */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
+ /* 0% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
+ (UINT32_C(0x0) << 12)
+ /* 6.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
+ (UINT32_C(0x1) << 12)
+ /* 13.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
+ (UINT32_C(0x2) << 12)
+ /* 20% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
+ (UINT32_C(0x3) << 12)
+ /* 26.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
+ (UINT32_C(0x4) << 12)
+ /* 33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
+ (UINT32_C(0x5) << 12)
+ /* 40% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
+ (UINT32_C(0x6) << 12)
+ /* 46.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
+ (UINT32_C(0x7) << 12)
+ /* 53.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
+ (UINT32_C(0x8) << 12)
+ /* 60% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
+ (UINT32_C(0x9) << 12)
+ /* 66.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
+ (UINT32_C(0xa) << 12)
+ /* 53.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
+ (UINT32_C(0xb) << 12)
+ /* 80% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
+ (UINT32_C(0xc) << 12)
+ /* 86.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
+ (UINT32_C(0xd) << 12)
+ /* 93.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
+ (UINT32_C(0xe) << 12)
+ /* 100% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
+ (UINT32_C(0xf) << 12)
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
+ HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
uint8_t valid;
} __attribute__((packed));
-/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
-struct hwrm_port_phy_cfg_cmd_err {
- /*
- * command specific error codes that goes to
- * the cmd_err field in Common HWRM Error Response.
- */
- uint8_t code;
- /* Unknown error */
- #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
- /* Unable to complete operation due to invalid speed */
- #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
- /*
- * retry the command since the phy is not ready.
- * retry count is returned in opaque_0.
- * This is only valid for the first command and
- * this value will not change for successive calls.
- * but if a 0 is returned at any time then this should
- * be treated as an un recoverable failure,
- *
- * retry interval in milli seconds is returned in opaque_1.
- * This specifies the time that user should wait before
- * issuing the next port_phy_cfg command.
- */
- #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
- #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
- HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
- uint8_t unused_0[7];
-} __attribute__((packed));
-
-/**********************
- * hwrm_port_phy_qcfg *
- **********************/
+/***************************
+ * hwrm_func_drv_if_change *
+ ***************************/
-/* hwrm_port_phy_qcfg_input (size:192b/24B) */
-struct hwrm_port_phy_qcfg_input {
+/* hwrm_func_drv_if_change_input (size:192b/24B) */
+struct hwrm_func_drv_if_change_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Port ID of port that is to be queried. */
- uint16_t port_id;
- uint8_t unused_0[6];
+ uint32_t flags;
+ /*
+ * When this bit is '1', the function driver is indicating
+ * that the IF state is changing to UP state. The call should
+ * be made at the beginning of the driver's open call before
+ * resources are allocated. After making the call, the driver
+ * should check the response to see if any resources may have
+ * changed (see the response below). If the driver fails
+ * the open call, the driver should make this call again with
+ * this bit cleared to indicate that the IF state is not UP.
+ * During the driver's close call when the IF state is changing
+ * to DOWN, the driver should make this call with the bit cleared
+ * after all resources have been freed.
+ */
+ #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
+ uint32_t unused;
} __attribute__((packed));
-/* hwrm_port_phy_qcfg_output (size:768b/96B) */
-struct hwrm_port_phy_qcfg_output {
+/* hwrm_func_drv_if_change_output (size:128b/16B) */
+struct hwrm_func_drv_if_change_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* This value indicates the current link status. */
- uint8_t link;
- /* There is no link or cable detected. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
- /* There is no link, but a cable has been detected. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
- /* There is a link. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
- uint8_t unused_0;
- /* This value indicates the current link speed of the connection. */
- uint16_t link_speed;
- /* 100Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
- /* 1Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
- /* 20Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
- /* 10Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
+ uint32_t flags;
/*
- * This value is indicates the duplex of the current
- * configuration.
+ * When this bit is '1', it indicates that the resources reserved
+ * for this function may have changed. The driver should check
+ * resource capabilities and reserve resources again before
+ * allocating resources.
*/
- uint8_t duplex_cfg;
- /* Half Duplex connection. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
- /* Full duplex connection. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
+ #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
+ UINT32_C(0x1)
+ uint8_t unused_0[3];
/*
- * This value is used to indicate the current
- * pause configuration. When autoneg is enabled, this value
- * represents the autoneg results of pause configuration.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t pause;
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************
+ * hwrm_port_phy_cfg *
+ *********************/
+
+
+/* hwrm_port_phy_cfg_input (size:448b/56B) */
+struct hwrm_port_phy_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * When this bit is '1', Generation of tx pause messages
- * is supported. Disabled otherwise.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
+ uint16_t cmpl_ring;
/*
- * When this bit is '1', Reception of rx pause messages
- * is supported. Disabled otherwise.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
+ uint16_t seq_id;
/*
- * The supported speeds for the port. This is a bit mask.
- * For each speed that is supported, the corrresponding
- * bit will be set to '1'.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint16_t support_speeds;
- /* 100Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When this bit is set to '1', the PHY for the port shall
+ * be reset.
+ *
+ * # If this bit is set to 1, then the HWRM shall reset the
+ * PHY after applying PHY configuration changes specified
+ * in this command.
+ * # In order to guarantee that PHY configuration changes
+ * specified in this command take effect, the HWRM
+ * client should set this flag to 1.
+ * # If this bit is not set to 1, then the HWRM may reset
+ * the PHY depending on the current PHY configuration and
+ * settings specified in this command.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
+ /* deprecated bit. Do not use!!! */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
UINT32_C(0x2)
- /* 1Gb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
+ /*
+ * When this bit is set to '1', the link shall be forced to
+ * the force_link_speed value.
+ *
+ * When this bit is set to '1', the HWRM client should
+ * not enable any of the auto negotiation related
+ * fields represented by auto_XXX fields in this command.
+ * When this bit is set to '1' and the HWRM client has
+ * enabled a auto_XXX field in this command, then the
+ * HWRM shall ignore the enabled auto_XXX field.
+ *
+ * When this bit is set to zero, the link
+ * shall be allowed to autoneg.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
- UINT32_C(0x8)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
- UINT32_C(0x10)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
- UINT32_C(0x40)
- /* 20Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
- UINT32_C(0x80)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
- UINT32_C(0x100)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
- UINT32_C(0x200)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
- UINT32_C(0x400)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
- UINT32_C(0x800)
- /* 10Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
- UINT32_C(0x1000)
- /* 10Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
- UINT32_C(0x2000)
/*
- * Current setting of forced link speed.
- * When the link speed is not being forced, this
- * value shall be set to 0.
+ * When this bit is set to '1', the auto-negotiation process
+ * shall be restarted on the link.
*/
- uint16_t force_link_speed;
- /* 100Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
- /* 1Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
- /* 20Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
- UINT32_C(0x190)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
- UINT32_C(0x1f4)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
- UINT32_C(0x3e8)
- /* 10Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
- UINT32_C(0xffff)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
- /* Current setting of auto negotiation mode. */
- uint8_t auto_mode;
- /* Disable autoneg or autoneg disabled. No speeds are selected. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
- /* Select all possible speeds for autoneg mode. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
+ UINT32_C(0x8)
/*
- * Select only the auto_link_speed speed for autoneg mode. This mode has
- * been DEPRECATED. An HWRM client should not use this mode.
+ * When this bit is set to '1', Energy Efficient Ethernet
+ * (EEE) is requested to be enabled on this link.
+ * If EEE is not supported on this port, then this flag
+ * shall be ignored by the HWRM.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
+ UINT32_C(0x10)
/*
- * Select the auto_link_speed or any speed below that speed for autoneg.
- * This mode has been DEPRECATED. An HWRM client should not use this mode.
+ * When this bit is set to '1', Energy Efficient Ethernet
+ * (EEE) is requested to be disabled on this link.
+ * If EEE is not supported on this port, then this flag
+ * shall be ignored by the HWRM.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
+ UINT32_C(0x20)
/*
- * Select the speeds based on the corresponding link speed mask value
- * that is provided.
+ * When this bit is set to '1' and EEE is enabled on this
+ * link, then TX LPI is requested to be enabled on the link.
+ * If EEE is not supported on this port, then this flag
+ * shall be ignored by the HWRM.
+ * If EEE is disabled on this port, then this flag shall be
+ * ignored by the HWRM.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
+ UINT32_C(0x40)
/*
- * Current setting of pause autonegotiation.
- * Move autoneg_pause flag here.
+ * When this bit is set to '1' and EEE is enabled on this
+ * link, then TX LPI is requested to be disabled on the link.
+ * If EEE is not supported on this port, then this flag
+ * shall be ignored by the HWRM.
+ * If EEE is disabled on this port, then this flag shall be
+ * ignored by the HWRM.
*/
- uint8_t auto_pause;
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
+ UINT32_C(0x80)
/*
- * When this bit is '1', Generation of tx pause messages
- * has been requested. Disabled otherwise.
+ * When set to 1, then the HWRM shall enable FEC autonegotitation
+ * on this port if supported.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC autonegotiation is not supported, then the HWRM shall ignore this
+ * flag.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
- UINT32_C(0x1)
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
+ UINT32_C(0x100)
/*
- * When this bit is '1', Reception of rx pause messages
- * has been requested. Disabled otherwise.
+ * When set to 1, then the HWRM shall disable FEC autonegotiation
+ * on this port if supported.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC autonegotiation is not supported, then the HWRM shall ignore this
+ * flag.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
- UINT32_C(0x2)
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
+ UINT32_C(0x200)
/*
- * When set to 1, the advertisement of pause is enabled.
- *
- * # When the auto_mode is not set to none and this flag is
- * set to 1, then the auto_pause bits on this port are being
- * advertised and autoneg pause results are being interpreted.
- * # When the auto_mode is not set to none and this
- * flag is set to 0, the pause is forced as indicated in
- * force_pause, and also advertised as auto_pause bits, but
- * the autoneg results are not interpreted since the pause
- * configuration is being forced.
- * # When the auto_mode is set to none and this flag is set to
- * 1, auto_pause bits should be ignored and should be set to 0.
+ * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
+ * on this port if supported.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
+ * flag.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
- UINT32_C(0x4)
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
+ UINT32_C(0x400)
/*
- * Current setting for auto_link_speed. This field is only
- * valid when auto_mode is set to "one_speed" or "one_or_below".
+ * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
+ * on this port if supported.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
+ * flag.
*/
- uint16_t auto_link_speed;
- /* 100Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
- /* 1Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
- /* 20Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
- /* 10Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
- UINT32_C(0xffff)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
+ UINT32_C(0x800)
/*
- * Current setting for auto_link_speed_mask that is used to
- * advertise speeds during autonegotiation.
- * This field is only valid when auto_mode is set to "mask".
- * The speeds specified in this field shall be a subset of
- * supported speeds on this port.
+ * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
+ * on this port if supported.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
+ * flag.
*/
- uint16_t auto_link_speed_mask;
- /* 100Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
+ UINT32_C(0x1000)
+ /*
+ * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
+ * on this port if supported.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
+ * flag.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
+ UINT32_C(0x2000)
+ /*
+ * When this bit is set to '1', the link shall be forced to
+ * be taken down.
+ *
+ * # When this bit is set to '1", all other
+ * command input settings related to the link speed shall
+ * be ignored.
+ * Once the link state is forced down, it can be
+ * explicitly cleared from that state by setting this flag
+ * to '0'.
+ * # If this flag is set to '0', then the link shall be
+ * cleared from forced down state if the link is in forced
+ * down state.
+ * There may be conditions (e.g. out-of-band or sideband
+ * configuration changes for the link) outside the scope
+ * of the HWRM implementation that may clear forced down
+ * link state.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
+ UINT32_C(0x4000)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the auto_mode field to be
+ * configured.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
+ /*
+ * This bit must be '1' for the auto_duplex field to be
+ * configured.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
UINT32_C(0x2)
- /* 1Gb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
+ /*
+ * This bit must be '1' for the auto_pause field to be
+ * configured.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
+ /*
+ * This bit must be '1' for the auto_link_speed field to be
+ * configured.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
UINT32_C(0x8)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
+ /*
+ * This bit must be '1' for the auto_link_speed_mask field to be
+ * configured.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
UINT32_C(0x10)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
+ /*
+ * This bit must be '1' for the wirespeed field to be
+ * configured.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
+ /*
+ * This bit must be '1' for the lpbk field to be
+ * configured.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
UINT32_C(0x40)
- /* 20Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
+ /*
+ * This bit must be '1' for the preemphasis field to be
+ * configured.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
UINT32_C(0x80)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
- UINT32_C(0x100)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
- UINT32_C(0x200)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
- UINT32_C(0x400)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
- UINT32_C(0x800)
- /* 10Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
- UINT32_C(0x1000)
- /* 10Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
- UINT32_C(0x2000)
- /* Current setting for wirespeed. */
- uint8_t wirespeed;
- /* Wirespeed feature is disabled. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
- /* Wirespeed feature is enabled. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
- /* Current setting for loopback. */
- uint8_t lpbk;
- /* No loopback is selected. Normal operation. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
/*
- * The HW will be configured with local loopback such that
- * host data is sent back to the host without modification.
+ * This bit must be '1' for the force_pause field to be
+ * configured.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
+ UINT32_C(0x100)
/*
- * The HW will be configured with remote loopback such that
- * port logic will send packets back out the transmitter that
- * are received.
+ * This bit must be '1' for the eee_link_speed_mask field to be
+ * configured.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
+ UINT32_C(0x200)
/*
- * The HW will be configured with external loopback such that
- * host data is sent on the trasmitter and based on the external
- * loopback connection the data will be received without modification.
+ * This bit must be '1' for the tx_lpi_timer field to be
+ * configured.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
+ UINT32_C(0x400)
+ /* Port ID of port that is to be configured. */
+ uint16_t port_id;
/*
- * Current setting of forced pause.
- * When the pause configuration is not being forced, then
- * this value shall be set to 0.
+ * This is the speed that will be used if the force
+ * bit is '1'. If unsupported speed is selected, an error
+ * will be generated.
*/
- uint8_t force_pause;
+ uint16_t force_link_speed;
+ /* 100Mb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
+ /* 1Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
+ /* 20Mb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 10Mb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
+ HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
/*
- * When this bit is '1', Generation of tx pause messages
- * is supported. Disabled otherwise.
+ * This value is used to identify what autoneg mode is
+ * used when the link speed is not being forced.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
+ uint8_t auto_mode;
+ /* Disable autoneg or autoneg disabled. No speeds are selected. */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
+ /* Select all possible speeds for autoneg mode. */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
/*
- * When this bit is '1', Reception of rx pause messages
- * is supported. Disabled otherwise.
+ * Select only the auto_link_speed speed for autoneg mode. This mode has
+ * been DEPRECATED. An HWRM client should not use this mode.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
/*
- * This value indicates the current status of the optics module on
- * this port.
+ * Select the auto_link_speed or any speed below that speed for autoneg.
+ * This mode has been DEPRECATED. An HWRM client should not use this mode.
*/
- uint8_t module_status;
- /* Module is inserted and accepted */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
- UINT32_C(0x0)
- /* Module is rejected and transmit side Laser is disabled. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
- UINT32_C(0x1)
- /* Module mismatch warning. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
- UINT32_C(0x2)
- /* Module is rejected and powered down. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
- UINT32_C(0x3)
- /* Module is not inserted. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
- UINT32_C(0x4)
- /* Module status is not applicable. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
- UINT32_C(0xff)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
- /* Current setting for preemphasis. */
- uint32_t preemphasis;
- /* This field represents the major version of the PHY. */
- uint8_t phy_maj;
- /* This field represents the minor version of the PHY. */
- uint8_t phy_min;
- /* This field represents the build version of the PHY. */
- uint8_t phy_bld;
- /* This value represents a PHY type. */
- uint8_t phy_type;
- /* Unknown */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
- UINT32_C(0x0)
- /* BASE-CR */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
- UINT32_C(0x1)
- /* BASE-KR4 (Deprecated) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
- UINT32_C(0x2)
- /* BASE-LR */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
- UINT32_C(0x3)
- /* BASE-SR */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
- UINT32_C(0x4)
- /* BASE-KR2 (Deprecated) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
- UINT32_C(0x5)
- /* BASE-KX */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
- UINT32_C(0x6)
- /* BASE-KR */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
- UINT32_C(0x7)
- /* BASE-T */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
- UINT32_C(0x8)
- /* EEE capable BASE-T */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
- UINT32_C(0x9)
- /* SGMII connected external PHY */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
- UINT32_C(0xa)
- /* 25G_BASECR_CA_L */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
- UINT32_C(0xb)
- /* 25G_BASECR_CA_S */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
- UINT32_C(0xc)
- /* 25G_BASECR_CA_N */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
- UINT32_C(0xd)
- /* 25G_BASESR */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
- UINT32_C(0xe)
- /* 100G_BASECR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
- UINT32_C(0xf)
- /* 100G_BASESR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
- UINT32_C(0x10)
- /* 100G_BASELR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
- UINT32_C(0x11)
- /* 100G_BASEER4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
- UINT32_C(0x12)
- /* 100G_BASESR10 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
- UINT32_C(0x13)
- /* 40G_BASECR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
- UINT32_C(0x14)
- /* 40G_BASESR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
- UINT32_C(0x15)
- /* 40G_BASELR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
- UINT32_C(0x16)
- /* 40G_BASEER4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
- UINT32_C(0x17)
- /* 40G_ACTIVE_CABLE */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
- UINT32_C(0x18)
- /* 1G_baseT */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
- UINT32_C(0x19)
- /* 1G_baseSX */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
- UINT32_C(0x1a)
- /* 1G_baseCX */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
- UINT32_C(0x1b)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX
- /* This value represents a media type. */
- uint8_t media_type;
- /* Unknown */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
- /* Twisted Pair */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
- /* Direct Attached Copper */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
- /* Fiber */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
- /* This value represents a transceiver type. */
- uint8_t xcvr_pkg_type;
- /* PHY and MAC are in the same package */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
- UINT32_C(0x1)
- /* PHY and MAC are in different packages */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
- UINT32_C(0x2)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
- uint8_t eee_config_phy_addr;
- /* This field represents PHY address. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
- UINT32_C(0x1f)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
/*
- * This field represents flags related to EEE configuration.
- * These EEE configuration flags are valid only when the
- * auto_mode is not set to none (in other words autonegotiation
- * is enabled).
+ * Select the speeds based on the corresponding link speed mask value
+ * that is provided.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
- UINT32_C(0xe0)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
+ HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
/*
- * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
- * Speeds for autoneg with EEE mode enabled
- * are based on eee_link_speed_mask.
+ * This is the duplex setting that will be used if the autoneg_mode
+ * is "one_speed" or "one_or_below".
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
- UINT32_C(0x20)
+ uint8_t auto_duplex;
+ /* Half Duplex will be requested. */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
+ /* Full duplex will be requested. */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
+ /* Both Half and Full dupex will be requested. */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
+ HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
/*
- * This flag is valid only when eee_enabled is set to 1.
- *
- * # If eee_enabled is set to 0, then EEE mode is disabled
- * and this flag shall be ignored.
- * # If eee_enabled is set to 1 and this flag is set to 1,
- * then Energy Efficient Ethernet (EEE) mode is enabled
- * and in use.
- * # If eee_enabled is set to 1 and this flag is set to 0,
- * then Energy Efficient Ethernet (EEE) mode is enabled
- * but is currently not in use.
+ * This value is used to configure the pause that will be
+ * used for autonegotiation.
+ * Add text on the usage of auto_pause and force_pause.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
- UINT32_C(0x40)
+ uint8_t auto_pause;
/*
- * This flag is valid only when eee_enabled is set to 1.
- *
- * # If eee_enabled is set to 0, then EEE mode is disabled
- * and this flag shall be ignored.
- * # If eee_enabled is set to 1 and this flag is set to 1,
- * then Energy Efficient Ethernet (EEE) mode is enabled
- * and TX LPI is enabled.
- * # If eee_enabled is set to 1 and this flag is set to 0,
- * then Energy Efficient Ethernet (EEE) mode is enabled
- * but TX LPI is disabled.
+ * When this bit is '1', Generation of tx pause messages
+ * has been requested. Disabled otherwise.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
- UINT32_C(0x80)
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
+ UINT32_C(0x1)
/*
- * When set to 1, the parallel detection is used to determine
- * the speed of the link partner.
- *
- * Parallel detection is used when a autonegotiation capable
- * device is connected to a link parter that is not capable
- * of autonegotiation.
+ * When this bit is '1', Reception of rx pause messages
+ * has been requested. Disabled otherwise.
*/
- uint8_t parallel_detect;
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
+ UINT32_C(0x2)
/*
- * When set to 1, the parallel detection is used to determine
- * the speed of the link partner.
+ * When set to 1, the advertisement of pause is enabled.
*
- * Parallel detection is used when a autonegotiation capable
- * device is connected to a link parter that is not capable
- * of autonegotiation.
+ * # When the auto_mode is not set to none and this flag is
+ * set to 1, then the auto_pause bits on this port are being
+ * advertised and autoneg pause results are being interpreted.
+ * # When the auto_mode is not set to none and this
+ * flag is set to 0, the pause is forced as indicated in
+ * force_pause, and also advertised as auto_pause bits, but
+ * the autoneg results are not interpreted since the pause
+ * configuration is being forced.
+ * # When the auto_mode is set to none and this flag is set to
+ * 1, auto_pause bits should be ignored and should be set to 0.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
+ UINT32_C(0x4)
+ uint8_t unused_0;
/*
- * The advertised speeds for the port by the link partner.
- * Each advertised speed will be set to '1'.
+ * This is the speed that will be used if the autoneg_mode
+ * is "one_speed" or "one_or_below". If an unsupported speed
+ * is selected, an error will be generated.
*/
- uint16_t link_partner_adv_speeds;
- /* 100Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
- UINT32_C(0x2)
- /* 1Gb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
+ uint16_t auto_link_speed;
+ /* 100Mb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
+ /* 1Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
+ /* 20Mb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 10Mb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
+ HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
+ /*
+ * This is a mask of link speeds that will be used if
+ * autoneg_mode is "mask". If unsupported speed is enabled
+ * an error will be generated.
+ */
+ uint16_t auto_link_speed_mask;
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
+ UINT32_C(0x2)
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
UINT32_C(0x8)
/* 2Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
UINT32_C(0x10)
/* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
UINT32_C(0x20)
/* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
UINT32_C(0x40)
/* 20Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
UINT32_C(0x80)
/* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
UINT32_C(0x100)
/* 40Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
UINT32_C(0x200)
/* 50Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
UINT32_C(0x400)
/* 100Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
UINT32_C(0x800)
/* 10Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
UINT32_C(0x1000)
/* 10Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
UINT32_C(0x2000)
+ /* This value controls the wirespeed feature. */
+ uint8_t wirespeed;
+ /* Wirespeed feature is disabled. */
+ #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
+ /* Wirespeed feature is enabled. */
+ #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
+ #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
+ HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
+ /* This value controls the loopback setting for the PHY. */
+ uint8_t lpbk;
+ /* No loopback is selected. Normal operation. */
+ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
/*
- * The advertised autoneg for the port by the link partner.
- * This field is deprecated and should be set to 0.
+ * The HW will be configured with local loopback such that
+ * host data is sent back to the host without modification.
*/
- uint8_t link_partner_adv_auto_mode;
- /* Disable autoneg or autoneg disabled. No speeds are selected. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
- UINT32_C(0x0)
- /* Select all possible speeds for autoneg mode. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
- UINT32_C(0x1)
+ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
/*
- * Select only the auto_link_speed speed for autoneg mode. This mode has
- * been DEPRECATED. An HWRM client should not use this mode.
+ * The HW will be configured with remote loopback such that
+ * port logic will send packets back out the transmitter that
+ * are received.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
- UINT32_C(0x2)
+ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
/*
- * Select the auto_link_speed or any speed below that speed for autoneg.
- * This mode has been DEPRECATED. An HWRM client should not use this mode.
+ * The HW will be configured with external loopback such that
+ * host data is sent on the trasmitter and based on the external
+ * loopback connection the data will be received without modification.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
- UINT32_C(0x3)
+ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
+ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
+ HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
/*
- * Select the speeds based on the corresponding link speed mask value
- * that is provided.
+ * This value is used to configure the pause that will be
+ * used for force mode.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
- UINT32_C(0x4)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
- /* The advertised pause settings on the port by the link partner. */
- uint8_t link_partner_adv_pause;
+ uint8_t force_pause;
/*
* When this bit is '1', Generation of tx pause messages
* is supported. Disabled otherwise.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
- UINT32_C(0x1)
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
/*
* When this bit is '1', Reception of rx pause messages
* is supported. Disabled otherwise.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
- UINT32_C(0x2)
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
+ uint8_t unused_1;
/*
- * Current setting for link speed mask that is used to
+ * This value controls the pre-emphasis to be used for the
+ * link. Driver should not set this value (use
+ * enable.preemphasis = 0) unless driver is sure of setting.
+ * Normally HWRM FW will determine proper pre-emphasis.
+ */
+ uint32_t preemphasis;
+ /*
+ * Setting for link speed mask that is used to
* advertise speeds during autonegotiation when EEE is enabled.
- * This field is valid only when eee_enabled flags is set to 1.
+ * This field is valid only when EEE is enabled.
* The speeds specified in this field shall be a subset of
* speeds specified in auto_link_speed_mask.
+ * If EEE is enabled,then at least one speed shall be provided
+ * in this mask.
*/
- uint16_t adv_eee_link_speed_mask;
+ uint16_t eee_link_speed_mask;
/* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
+ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
UINT32_C(0x1)
/* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
+ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
UINT32_C(0x2)
/* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
+ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
UINT32_C(0x4)
/* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
+ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
UINT32_C(0x8)
/* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
+ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
UINT32_C(0x10)
/* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
+ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
UINT32_C(0x20)
/* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
+ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
UINT32_C(0x40)
+ uint8_t unused_2[2];
/*
- * Current setting for link speed mask that is advertised by
- * the link partner when EEE is enabled.
- * This field is valid only when eee_enabled flags is set to 1.
+ * Reuested setting of TX LPI timer in microseconds.
+ * This field is valid only when EEE is enabled and TX LPI is
+ * enabled.
*/
- uint16_t link_partner_adv_eee_link_speed_mask;
- /* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
- UINT32_C(0x2)
- /* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
- UINT32_C(0x8)
- /* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
- UINT32_C(0x10)
- /* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
- UINT32_C(0x40)
- uint32_t xcvr_identifier_type_tx_lpi_timer;
+ uint32_t tx_lpi_timer;
+ #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
+ #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
+ uint32_t unused_3;
+} __attribute__((packed));
+
+/* hwrm_port_phy_cfg_output (size:128b/16B) */
+struct hwrm_port_phy_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * Current setting of TX LPI timer in microseconds.
- * This field is valid only when_eee_enabled flag is set to 1
- * and tx_lpi_enabled is set to 1.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
- UINT32_C(0xffffff)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
- /* This value represents transceiver identifier type. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
- UINT32_C(0xff000000)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
- /* Unknown */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
- (UINT32_C(0x0) << 24)
- /* SFP/SFP+/SFP28 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
- (UINT32_C(0x3) << 24)
- /* QSFP+ */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
- (UINT32_C(0xc) << 24)
- /* QSFP+ */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
- (UINT32_C(0xd) << 24)
- /* QSFP28 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
- (UINT32_C(0x11) << 24)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
+ uint8_t valid;
+} __attribute__((packed));
+
+/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
+struct hwrm_port_phy_cfg_cmd_err {
/*
- * This value represents the current configuration of
- * Forward Error Correction (FEC) on the port.
+ * command specific error codes that goes to
+ * the cmd_err field in Common HWRM Error Response.
*/
- uint16_t fec_cfg;
+ uint8_t code;
+ /* Unknown error */
+ #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
+ /* Unable to complete operation due to invalid speed */
+ #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
/*
- * When set to 1, then FEC is not supported on this port. If this flag
- * is set to 1, then all other FEC configuration flags shall be ignored.
- * When set to 0, then FEC is supported as indicated by other
- * configuration flags.
- * If no cable is attached and the HWRM does not yet know the FEC
- * capability, then the HWRM shall set this flag to 1 when reporting
- * FEC capability.
- */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
- UINT32_C(0x1)
- /*
- * When set to 1, then FEC autonegotiation is supported on this port.
- * When set to 0, then FEC autonegotiation is not supported on this port.
- */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
- UINT32_C(0x2)
- /*
- * When set to 1, then FEC autonegotiation is enabled on this port.
- * When set to 0, then FEC autonegotiation is disabled if supported.
- * This flag should be ignored if FEC autonegotiation is not supported on this port.
- */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
- UINT32_C(0x4)
- /*
- * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
- * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
- */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
- UINT32_C(0x8)
- /*
- * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
- * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
- * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
- */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
- UINT32_C(0x10)
- /*
- * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
- * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
- */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
- UINT32_C(0x20)
- /*
- * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
- * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
- * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
- */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
- UINT32_C(0x40)
- /*
- * This value is indicates the duplex of the current
- * connection state.
- */
- uint8_t duplex_state;
- /* Half Duplex connection. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
- /* Full duplex connection. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
- /* Option flags fields. */
- uint8_t option_flags;
- /* When this bit is '1', Media auto detect is enabled. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
- UINT32_C(0x1)
- /*
- * Up to 16 bytes of null padded ASCII string representing
- * PHY vendor.
- * If the string is set to null, then the vendor name is not
- * available.
- */
- char phy_vendor_name[16];
- /*
- * Up to 16 bytes of null padded ASCII string that
- * identifies vendor specific part number of the PHY.
- * If the string is set to null, then the vendor specific
- * part number is not available.
- */
- char phy_vendor_partnumber[16];
- uint8_t unused_2[7];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * retry the command since the phy is not ready.
+ * retry count is returned in opaque_0.
+ * This is only valid for the first command and
+ * this value will not change for successive calls.
+ * but if a 0 is returned at any time then this should
+ * be treated as an un recoverable failure,
+ *
+ * retry interval in milli seconds is returned in opaque_1.
+ * This specifies the time that user should wait before
+ * issuing the next port_phy_cfg command.
*/
- uint8_t valid;
+ #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
+ #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
+ HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
+ uint8_t unused_0[7];
} __attribute__((packed));
-/*********************
- * hwrm_port_mac_cfg *
- *********************/
+/**********************
+ * hwrm_port_phy_qcfg *
+ **********************/
-/* hwrm_port_mac_cfg_input (size:320b/40B) */
-struct hwrm_port_mac_cfg_input {
+/* hwrm_port_phy_qcfg_input (size:192b/24B) */
+struct hwrm_port_phy_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ /* Port ID of port that is to be queried. */
+ uint16_t port_id;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_port_phy_qcfg_output (size:768b/96B) */
+struct hwrm_port_phy_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value indicates the current link status. */
+ uint8_t link;
+ /* There is no link or cable detected. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
+ /* There is no link, but a cable has been detected. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
+ /* There is a link. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
+ uint8_t unused_0;
+ /* This value indicates the current link speed of the connection. */
+ uint16_t link_speed;
+ /* 100Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
+ /* 1Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
+ /* 20Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 10Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
/*
- * In this field, there are a number of CoS mappings related flags
- * that are used to configure CoS mappings and their corresponding
- * priorities in the hardware.
- * For the priorities of CoS mappings, the HWRM uses the following
- * priority order (high to low) by default:
- * # vlan pri
- * # ip_dscp
- * # tunnel_vlan_pri
- * # default cos
- *
- * A subset of CoS mappings can be enabled.
- * If a priority is not specified for an enabled CoS mapping, the
- * priority will be assigned in the above order for the enabled CoS
- * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
- * enabled and their priorities are not specified, the following
- * priority order (high to low) will be used by the HWRM:
- * # vlan_pri
- * # ip_dscp
- * # default cos
- *
- * vlan_pri CoS mapping together with default CoS with lower priority
- * are enabled by default by the HWRM.
+ * This value is indicates the duplex of the current
+ * configuration.
*/
- uint32_t flags;
+ uint8_t duplex_cfg;
+ /* Half Duplex connection. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
+ /* Full duplex connection. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
/*
- * When this bit is '1', this command will configure
- * the MAC to match the current link state of the PHY.
- * If the link is not established on the PHY, then this
- * bit has no effect.
+ * This value is used to indicate the current
+ * pause configuration. When autoneg is enabled, this value
+ * represents the autoneg results of pause configuration.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
- UINT32_C(0x1)
+ uint8_t pause;
/*
- * When this bit is set to '1', the inner VLAN PRI to CoS mapping
- * is requested to be enabled.
+ * When this bit is '1', Generation of tx pause messages
+ * is supported. Disabled otherwise.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
- UINT32_C(0x2)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
/*
- * When this bit is set to '1', tunnel VLAN PRI field to
- * CoS mapping is requested to be enabled.
+ * When this bit is '1', Reception of rx pause messages
+ * is supported. Disabled otherwise.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
- UINT32_C(0x4)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
/*
- * When this bit is set to '1', the IP DSCP to CoS mapping is
- * requested to be enabled.
+ * The supported speeds for the port. This is a bit mask.
+ * For each speed that is supported, the corrresponding
+ * bit will be set to '1'.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
+ uint16_t support_speeds;
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
+ UINT32_C(0x2)
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
UINT32_C(0x8)
- /*
- * When this bit is '1', the HWRM is requested to
- * enable timestamp capture capability on the receive side
- * of this port.
- */
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
UINT32_C(0x10)
- /*
- * When this bit is '1', the HWRM is requested to
- * disable timestamp capture capability on the receive side
- * of this port.
- */
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
UINT32_C(0x20)
- /*
- * When this bit is '1', the HWRM is requested to
- * enable timestamp capture capability on the transmit side
- * of this port.
- */
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
UINT32_C(0x40)
- /*
- * When this bit is '1', the HWRM is requested to
- * disable timestamp capture capability on the transmit side
- * of this port.
- */
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
+ /* 20Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
UINT32_C(0x80)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
+ UINT32_C(0x100)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
+ UINT32_C(0x200)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
+ UINT32_C(0x400)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
+ UINT32_C(0x800)
+ /* 10Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
+ UINT32_C(0x1000)
+ /* 10Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
+ UINT32_C(0x2000)
/*
- * When this bit is '1', the Out-Of-Box WoL is requested to
- * be enabled on this port.
+ * Current setting of forced link speed.
+ * When the link speed is not being forced, this
+ * value shall be set to 0.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
- UINT32_C(0x100)
+ uint16_t force_link_speed;
+ /* 100Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
+ /* 1Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
+ /* 20Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
+ UINT32_C(0x190)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
+ UINT32_C(0x1f4)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
+ UINT32_C(0x3e8)
+ /* 10Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
+ UINT32_C(0xffff)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
+ /* Current setting of auto negotiation mode. */
+ uint8_t auto_mode;
+ /* Disable autoneg or autoneg disabled. No speeds are selected. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
+ /* Select all possible speeds for autoneg mode. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
/*
- * When this bit is '1', the the Out-Of-Box WoL is requested to
- * be disabled on this port.
+ * Select only the auto_link_speed speed for autoneg mode. This mode has
+ * been DEPRECATED. An HWRM client should not use this mode.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
- UINT32_C(0x200)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
/*
- * When this bit is set to '1', the inner VLAN PRI to CoS mapping
- * is requested to be disabled.
+ * Select the auto_link_speed or any speed below that speed for autoneg.
+ * This mode has been DEPRECATED. An HWRM client should not use this mode.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
- UINT32_C(0x400)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
/*
- * When this bit is set to '1', tunnel VLAN PRI field to
- * CoS mapping is requested to be disabled.
+ * Select the speeds based on the corresponding link speed mask value
+ * that is provided.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
- UINT32_C(0x800)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
/*
- * When this bit is set to '1', the IP DSCP to CoS mapping is
- * requested to be disabled.
+ * Current setting of pause autonegotiation.
+ * Move autoneg_pause flag here.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
- UINT32_C(0x1000)
- uint32_t enables;
+ uint8_t auto_pause;
/*
- * This bit must be '1' for the ipg field to be
- * configured.
+ * When this bit is '1', Generation of tx pause messages
+ * has been requested. Disabled otherwise.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
UINT32_C(0x1)
/*
- * This bit must be '1' for the lpbk field to be
- * configured.
+ * When this bit is '1', Reception of rx pause messages
+ * has been requested. Disabled otherwise.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
UINT32_C(0x2)
/*
- * This bit must be '1' for the vlan_pri2cos_map_pri field to be
- * configured.
+ * When set to 1, the advertisement of pause is enabled.
+ *
+ * # When the auto_mode is not set to none and this flag is
+ * set to 1, then the auto_pause bits on this port are being
+ * advertised and autoneg pause results are being interpreted.
+ * # When the auto_mode is not set to none and this
+ * flag is set to 0, the pause is forced as indicated in
+ * force_pause, and also advertised as auto_pause bits, but
+ * the autoneg results are not interpreted since the pause
+ * configuration is being forced.
+ * # When the auto_mode is set to none and this flag is set to
+ * 1, auto_pause bits should be ignored and should be set to 0.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
UINT32_C(0x4)
/*
- * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
- * configured.
+ * Current setting for auto_link_speed. This field is only
+ * valid when auto_mode is set to "one_speed" or "one_or_below".
*/
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
- UINT32_C(0x10)
+ uint16_t auto_link_speed;
+ /* 100Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
+ /* 1Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
+ /* 20Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 10Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
+ UINT32_C(0xffff)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
/*
- * This bit must be '1' for the dscp2cos_map_pri field to be
- * configured.
+ * Current setting for auto_link_speed_mask that is used to
+ * advertise speeds during autonegotiation.
+ * This field is only valid when auto_mode is set to "mask".
+ * The speeds specified in this field shall be a subset of
+ * supported speeds on this port.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
+ uint16_t auto_link_speed_mask;
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
+ UINT32_C(0x2)
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
+ UINT32_C(0x8)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
+ UINT32_C(0x10)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
UINT32_C(0x20)
- /*
- * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
- * configured.
- */
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
UINT32_C(0x40)
- /*
- * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
- * configured.
- */
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
+ /* 20Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
UINT32_C(0x80)
- /*
- * This bit must be '1' for the cos_field_cfg field to be
- * configured.
- */
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
UINT32_C(0x100)
- /* Port ID of port that is to be configured. */
- uint16_t port_id;
- /*
- * This value is used to configure the minimum IPG that will
- * be sent between packets by this port.
- */
- uint8_t ipg;
- /* This value controls the loopback setting for the MAC. */
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
+ UINT32_C(0x200)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
+ UINT32_C(0x400)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
+ UINT32_C(0x800)
+ /* 10Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
+ UINT32_C(0x1000)
+ /* 10Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
+ UINT32_C(0x2000)
+ /* Current setting for wirespeed. */
+ uint8_t wirespeed;
+ /* Wirespeed feature is disabled. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
+ /* Wirespeed feature is enabled. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
+ /* Current setting for loopback. */
uint8_t lpbk;
/* No loopback is selected. Normal operation. */
- #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
/*
* The HW will be configured with local loopback such that
* host data is sent back to the host without modification.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
/*
* The HW will be configured with remote loopback such that
* port logic will send packets back out the transmitter that
* are received.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
- #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
- HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
/*
- * This value controls the priority setting of VLAN PRI to CoS
- * mapping based on VLAN Tags of inner packet headers of
- * tunneled packets or packet headers of non-tunneled packets.
- *
- * # Each XXX_pri variable shall have a unique priority value
- * when it is being specified.
- * # When comparing priorities of mappings, higher value
- * indicates higher priority.
- * For example, a value of 0-3 is returned where 0 is being
- * the lowest priority and 3 is being the highest priority.
+ * The HW will be configured with external loopback such that
+ * host data is sent on the trasmitter and based on the external
+ * loopback connection the data will be received without modification.
*/
- uint8_t vlan_pri2cos_map_pri;
- /* Reserved field. */
- uint8_t reserved1;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
/*
- * This value controls the priority setting of VLAN PRI to CoS
- * mapping based on VLAN Tags of tunneled header.
- * This mapping only applies when tunneled headers
- * are present.
- *
- * # Each XXX_pri variable shall have a unique priority value
- * when it is being specified.
- * # When comparing priorities of mappings, higher value
- * indicates higher priority.
- * For example, a value of 0-3 is returned where 0 is being
- * the lowest priority and 3 is being the highest priority.
+ * Current setting of forced pause.
+ * When the pause configuration is not being forced, then
+ * this value shall be set to 0.
*/
- uint8_t tunnel_pri2cos_map_pri;
+ uint8_t force_pause;
/*
- * This value controls the priority setting of IP DSCP to CoS
- * mapping based on inner IP header of tunneled packets or
- * IP header of non-tunneled packets.
- *
- * # Each XXX_pri variable shall have a unique priority value
- * when it is being specified.
- * # When comparing priorities of mappings, higher value
- * indicates higher priority.
- * For example, a value of 0-3 is returned where 0 is being
- * the lowest priority and 3 is being the highest priority.
+ * When this bit is '1', Generation of tx pause messages
+ * is supported. Disabled otherwise.
*/
- uint8_t dscp2pri_map_pri;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
/*
- * This is a 16-bit bit mask that is used to request a
- * specific configuration of time stamp capture of PTP messages
- * on the receive side of this port.
- * This field shall be ignored if the ptp_rx_ts_capture_enable
- * flag is not set in this command.
- * Otherwise, if bit 'i' is set, then the HWRM is being
- * requested to configure the receive side of the port to
- * capture the time stamp of every received PTP message
- * with messageType field value set to i.
+ * When this bit is '1', Reception of rx pause messages
+ * is supported. Disabled otherwise.
*/
- uint16_t rx_ts_capture_ptp_msg_type;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
/*
- * This is a 16-bit bit mask that is used to request a
- * specific configuration of time stamp capture of PTP messages
- * on the transmit side of this port.
- * This field shall be ignored if the ptp_tx_ts_capture_enable
- * flag is not set in this command.
- * Otherwise, if bit 'i' is set, then the HWRM is being
- * requested to configure the transmit sied of the port to
- * capture the time stamp of every transmitted PTP message
- * with messageType field value set to i.
+ * This value indicates the current status of the optics module on
+ * this port.
*/
- uint16_t tx_ts_capture_ptp_msg_type;
- /* Configuration of CoS fields. */
- uint8_t cos_field_cfg;
- /* Reserved */
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
+ uint8_t module_status;
+ /* Module is inserted and accepted */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
+ UINT32_C(0x0)
+ /* Module is rejected and transmit side Laser is disabled. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
UINT32_C(0x1)
- /*
- * This field is used to specify selection of VLAN PRI value
- * based on whether one or two VLAN Tags are present in
- * the inner packet headers of tunneled packets or
- * non-tunneled packets.
- * This field is valid only if inner VLAN PRI to CoS mapping
- * is enabled.
- * If VLAN PRI to CoS mapping is not enabled, then this
- * field shall be ignored.
- */
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
+ /* Module mismatch warning. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
+ UINT32_C(0x2)
+ /* Module is rejected and powered down. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
+ UINT32_C(0x3)
+ /* Module is not inserted. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
+ UINT32_C(0x4)
+ /* Module status is not applicable. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
+ UINT32_C(0xff)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
+ /* Current setting for preemphasis. */
+ uint32_t preemphasis;
+ /* This field represents the major version of the PHY. */
+ uint8_t phy_maj;
+ /* This field represents the minor version of the PHY. */
+ uint8_t phy_min;
+ /* This field represents the build version of the PHY. */
+ uint8_t phy_bld;
+ /* This value represents a PHY type. */
+ uint8_t phy_type;
+ /* Unknown */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
+ UINT32_C(0x0)
+ /* BASE-CR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
+ UINT32_C(0x1)
+ /* BASE-KR4 (Deprecated) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
+ UINT32_C(0x2)
+ /* BASE-LR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
+ UINT32_C(0x3)
+ /* BASE-SR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
+ UINT32_C(0x4)
+ /* BASE-KR2 (Deprecated) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
+ UINT32_C(0x5)
+ /* BASE-KX */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
UINT32_C(0x6)
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
- 1
+ /* BASE-KR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
+ UINT32_C(0x7)
+ /* BASE-T */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
+ UINT32_C(0x8)
+ /* EEE capable BASE-T */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
+ UINT32_C(0x9)
+ /* SGMII connected external PHY */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
+ UINT32_C(0xa)
+ /* 25G_BASECR_CA_L */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
+ UINT32_C(0xb)
+ /* 25G_BASECR_CA_S */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
+ UINT32_C(0xc)
+ /* 25G_BASECR_CA_N */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
+ UINT32_C(0xd)
+ /* 25G_BASESR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
+ UINT32_C(0xe)
+ /* 100G_BASECR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
+ UINT32_C(0xf)
+ /* 100G_BASESR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
+ UINT32_C(0x10)
+ /* 100G_BASELR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
+ UINT32_C(0x11)
+ /* 100G_BASEER4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
+ UINT32_C(0x12)
+ /* 100G_BASESR10 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
+ UINT32_C(0x13)
+ /* 40G_BASECR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
+ UINT32_C(0x14)
+ /* 40G_BASESR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
+ UINT32_C(0x15)
+ /* 40G_BASELR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
+ UINT32_C(0x16)
+ /* 40G_BASEER4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
+ UINT32_C(0x17)
+ /* 40G_ACTIVE_CABLE */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
+ UINT32_C(0x18)
+ /* 1G_baseT */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
+ UINT32_C(0x19)
+ /* 1G_baseSX */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
+ UINT32_C(0x1a)
+ /* 1G_baseCX */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
+ UINT32_C(0x1b)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX
+ /* This value represents a media type. */
+ uint8_t media_type;
+ /* Unknown */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
+ /* Twisted Pair */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
+ /* Direct Attached Copper */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
+ /* Fiber */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
+ /* This value represents a transceiver type. */
+ uint8_t xcvr_pkg_type;
+ /* PHY and MAC are in the same package */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
+ UINT32_C(0x1)
+ /* PHY and MAC are in different packages */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
+ UINT32_C(0x2)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
+ uint8_t eee_config_phy_addr;
+ /* This field represents PHY address. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
+ UINT32_C(0x1f)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
/*
- * Select inner VLAN PRI when 1 or 2 VLAN Tags are
- * present in the inner packet headers
+ * This field represents flags related to EEE configuration.
+ * These EEE configuration flags are valid only when the
+ * auto_mode is not set to none (in other words autonegotiation
+ * is enabled).
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
- (UINT32_C(0x0) << 1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
+ UINT32_C(0xe0)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
/*
- * Select outer VLAN Tag PRI when 2 VLAN Tags are
- * present in the inner packet headers.
- * No VLAN PRI shall be selected for this configuration
- * if only one VLAN Tag is present in the inner
- * packet headers.
+ * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
+ * Speeds for autoneg with EEE mode enabled
+ * are based on eee_link_speed_mask.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
- (UINT32_C(0x1) << 1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
+ UINT32_C(0x20)
/*
- * Select outermost VLAN PRI when 1 or 2 VLAN Tags
- * are present in the inner packet headers
+ * This flag is valid only when eee_enabled is set to 1.
+ *
+ * # If eee_enabled is set to 0, then EEE mode is disabled
+ * and this flag shall be ignored.
+ * # If eee_enabled is set to 1 and this flag is set to 1,
+ * then Energy Efficient Ethernet (EEE) mode is enabled
+ * and in use.
+ * # If eee_enabled is set to 1 and this flag is set to 0,
+ * then Energy Efficient Ethernet (EEE) mode is enabled
+ * but is currently not in use.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
- (UINT32_C(0x2) << 1)
- /* Unspecified */
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
- (UINT32_C(0x3) << 1)
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
- HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
- /*
- * This field is used to specify selection of tunnel VLAN
- * PRI value based on whether one or two VLAN Tags are
- * present in tunnel headers.
- * This field is valid only if tunnel VLAN PRI to CoS mapping
- * is enabled.
- * If tunnel VLAN PRI to CoS mapping is not enabled, then this
- * field shall be ignored.
- */
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
- UINT32_C(0x18)
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
- 3
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
+ UINT32_C(0x40)
/*
- * Select inner VLAN PRI when 1 or 2 VLAN Tags are
- * present in the tunnel packet headers
+ * This flag is valid only when eee_enabled is set to 1.
+ *
+ * # If eee_enabled is set to 0, then EEE mode is disabled
+ * and this flag shall be ignored.
+ * # If eee_enabled is set to 1 and this flag is set to 1,
+ * then Energy Efficient Ethernet (EEE) mode is enabled
+ * and TX LPI is enabled.
+ * # If eee_enabled is set to 1 and this flag is set to 0,
+ * then Energy Efficient Ethernet (EEE) mode is enabled
+ * but TX LPI is disabled.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
- (UINT32_C(0x0) << 3)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
+ UINT32_C(0x80)
/*
- * Select outer VLAN Tag PRI when 2 VLAN Tags are
- * present in the tunnel packet headers.
- * No tunnel VLAN PRI shall be selected for this
- * configuration if only one VLAN Tag is present in
- * the tunnel packet headers.
+ * When set to 1, the parallel detection is used to determine
+ * the speed of the link partner.
+ *
+ * Parallel detection is used when a autonegotiation capable
+ * device is connected to a link parter that is not capable
+ * of autonegotiation.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
- (UINT32_C(0x1) << 3)
+ uint8_t parallel_detect;
/*
- * Select outermost VLAN PRI when 1 or 2 VLAN Tags
- * are present in the tunnel packet headers
+ * When set to 1, the parallel detection is used to determine
+ * the speed of the link partner.
+ *
+ * Parallel detection is used when a autonegotiation capable
+ * device is connected to a link parter that is not capable
+ * of autonegotiation.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
- (UINT32_C(0x2) << 3)
- /* Unspecified */
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
- (UINT32_C(0x3) << 3)
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
- HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
/*
- * This field shall be used to provide default CoS value
- * that has been configured on this port.
- * This field is valid only if default CoS mapping
- * is enabled.
- * If default CoS mapping is not enabled, then this
- * field shall be ignored.
+ * The advertised speeds for the port by the link partner.
+ * Each advertised speed will be set to '1'.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
- UINT32_C(0xe0)
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
- 5
- uint8_t unused_0[3];
-} __attribute__((packed));
-
-/* hwrm_port_mac_cfg_output (size:128b/16B) */
-struct hwrm_port_mac_cfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
+ uint16_t link_partner_adv_speeds;
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
+ UINT32_C(0x2)
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
+ UINT32_C(0x8)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
+ UINT32_C(0x10)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
+ UINT32_C(0x40)
+ /* 20Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
+ UINT32_C(0x80)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
+ UINT32_C(0x100)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
+ UINT32_C(0x200)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
+ UINT32_C(0x400)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
+ UINT32_C(0x800)
+ /* 10Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
+ UINT32_C(0x1000)
+ /* 10Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
+ UINT32_C(0x2000)
/*
- * This is the configured maximum length of Ethernet packet
- * payload that is allowed to be received on the port.
- * This value does not include the number of bytes used by
- * Ethernet header and trailer (CRC).
+ * The advertised autoneg for the port by the link partner.
+ * This field is deprecated and should be set to 0.
*/
- uint16_t mru;
+ uint8_t link_partner_adv_auto_mode;
+ /* Disable autoneg or autoneg disabled. No speeds are selected. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
+ UINT32_C(0x0)
+ /* Select all possible speeds for autoneg mode. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
+ UINT32_C(0x1)
/*
- * This is the configured maximum length of Ethernet packet
- * payload that is allowed to be transmitted on the port.
- * This value does not include the number of bytes used by
- * Ethernet header and trailer (CRC).
+ * Select only the auto_link_speed speed for autoneg mode. This mode has
+ * been DEPRECATED. An HWRM client should not use this mode.
*/
- uint16_t mtu;
- /* Current configuration of the IPG value. */
- uint8_t ipg;
- /* Current value of the loopback value. */
- uint8_t lpbk;
- /* No loopback is selected. Normal operation. */
- #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
+ UINT32_C(0x2)
/*
- * The HW will be configured with local loopback such that
- * host data is sent back to the host without modification.
+ * Select the auto_link_speed or any speed below that speed for autoneg.
+ * This mode has been DEPRECATED. An HWRM client should not use this mode.
*/
- #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
+ UINT32_C(0x3)
/*
- * The HW will be configured with remote loopback such that
- * port logic will send packets back out the transmitter that
- * are received.
+ * Select the speeds based on the corresponding link speed mask value
+ * that is provided.
*/
- #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
- #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
- HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
- uint8_t unused_0;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
+ UINT32_C(0x4)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
+ /* The advertised pause settings on the port by the link partner. */
+ uint8_t link_partner_adv_pause;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When this bit is '1', Generation of tx pause messages
+ * is supported. Disabled otherwise.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/**********************
- * hwrm_port_mac_qcfg *
- **********************/
-
-
-/* hwrm_port_mac_qcfg_input (size:192b/24B) */
-struct hwrm_port_mac_qcfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
+ UINT32_C(0x1)
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * When this bit is '1', Reception of rx pause messages
+ * is supported. Disabled otherwise.
*/
- uint16_t cmpl_ring;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
+ UINT32_C(0x2)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Current setting for link speed mask that is used to
+ * advertise speeds during autonegotiation when EEE is enabled.
+ * This field is valid only when eee_enabled flags is set to 1.
+ * The speeds specified in this field shall be a subset of
+ * speeds specified in auto_link_speed_mask.
*/
- uint16_t seq_id;
+ uint16_t adv_eee_link_speed_mask;
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
+ UINT32_C(0x2)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
+ UINT32_C(0x8)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
+ UINT32_C(0x10)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
+ UINT32_C(0x40)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * Current setting for link speed mask that is advertised by
+ * the link partner when EEE is enabled.
+ * This field is valid only when eee_enabled flags is set to 1.
*/
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ uint16_t link_partner_adv_eee_link_speed_mask;
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
+ UINT32_C(0x2)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
+ UINT32_C(0x8)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
+ UINT32_C(0x10)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
+ UINT32_C(0x40)
+ uint32_t xcvr_identifier_type_tx_lpi_timer;
+ /*
+ * Current setting of TX LPI timer in microseconds.
+ * This field is valid only when_eee_enabled flag is set to 1
+ * and tx_lpi_enabled is set to 1.
*/
- uint64_t resp_addr;
- /* Port ID of port that is to be configured. */
- uint16_t port_id;
- uint8_t unused_0[6];
-} __attribute__((packed));
-
-/* hwrm_port_mac_qcfg_output (size:192b/24B) */
-struct hwrm_port_mac_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
+ UINT32_C(0xffffff)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
+ /* This value represents transceiver identifier type. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
+ /* Unknown */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
+ (UINT32_C(0x0) << 24)
+ /* SFP/SFP+/SFP28 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
+ (UINT32_C(0x3) << 24)
+ /* QSFP+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
+ (UINT32_C(0xc) << 24)
+ /* QSFP+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
+ (UINT32_C(0xd) << 24)
+ /* QSFP28 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
+ (UINT32_C(0x11) << 24)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
/*
- * This is the configured maximum length of Ethernet packet
- * payload that is allowed to be received on the port.
- * This value does not include the number of bytes used by the
- * Ethernet header and trailer (CRC).
+ * This value represents the current configuration of
+ * Forward Error Correction (FEC) on the port.
*/
- uint16_t mru;
+ uint16_t fec_cfg;
/*
- * This is the configured maximum length of Ethernet packet
- * payload that is allowed to be transmitted on the port.
- * This value does not include the number of bytes used by the
- * Ethernet header and trailer (CRC).
+ * When set to 1, then FEC is not supported on this port. If this flag
+ * is set to 1, then all other FEC configuration flags shall be ignored.
+ * When set to 0, then FEC is supported as indicated by other
+ * configuration flags.
+ * If no cable is attached and the HWRM does not yet know the FEC
+ * capability, then the HWRM shall set this flag to 1 when reporting
+ * FEC capability.
*/
- uint16_t mtu;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
+ UINT32_C(0x1)
/*
- * The minimum IPG that will
- * be sent between packets by this port.
+ * When set to 1, then FEC autonegotiation is supported on this port.
+ * When set to 0, then FEC autonegotiation is not supported on this port.
*/
- uint8_t ipg;
- /* The loopback setting for the MAC. */
- uint8_t lpbk;
- /* No loopback is selected. Normal operation. */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
+ UINT32_C(0x2)
/*
- * The HW will be configured with local loopback such that
- * host data is sent back to the host without modification.
+ * When set to 1, then FEC autonegotiation is enabled on this port.
+ * When set to 0, then FEC autonegotiation is disabled if supported.
+ * This flag should be ignored if FEC autonegotiation is not supported on this port.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
+ UINT32_C(0x4)
/*
- * The HW will be configured with remote loopback such that
- * port logic will send packets back out the transmitter that
- * are received.
+ * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
+ * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
- #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
- HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
+ UINT32_C(0x8)
/*
- * Priority setting for VLAN PRI to CoS mapping.
- * # Each XXX_pri variable shall have a unique priority value
- * when it is being used.
- * # When comparing priorities of mappings, higher value
- * indicates higher priority.
- * For example, a value of 0-3 is returned where 0 is being
- * the lowest priority and 3 is being the highest priority.
- * # If the correspoding CoS mapping is not enabled, then this
- * field should be ignored.
- * # This value indicates the normalized priority value retained
- * in the HWRM.
+ * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
+ * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
+ * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
*/
- uint8_t vlan_pri2cos_map_pri;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
+ UINT32_C(0x10)
/*
- * In this field, a number of CoS mappings related flags
- * are used to indicate configured CoS mappings.
+ * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
+ * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
*/
- uint8_t flags;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
+ UINT32_C(0x20)
/*
- * When this bit is set to '1', the inner VLAN PRI to CoS mapping
- * is enabled.
+ * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
+ * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
+ * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
- UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
+ UINT32_C(0x40)
/*
- * When this bit is set to '1', tunnel VLAN PRI field to
- * CoS mapping is enabled.
+ * This value is indicates the duplex of the current
+ * connection state.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
- UINT32_C(0x2)
+ uint8_t duplex_state;
+ /* Half Duplex connection. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
+ /* Full duplex connection. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
+ /* Option flags fields. */
+ uint8_t option_flags;
+ /* When this bit is '1', Media auto detect is enabled. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
+ UINT32_C(0x1)
/*
- * When this bit is set to '1', the IP DSCP to CoS mapping is
- * enabled.
+ * Up to 16 bytes of null padded ASCII string representing
+ * PHY vendor.
+ * If the string is set to null, then the vendor name is not
+ * available.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
- UINT32_C(0x4)
+ char phy_vendor_name[16];
/*
- * When this bit is '1', the Out-Of-Box WoL is enabled on this
- * port.
+ * Up to 16 bytes of null padded ASCII string that
+ * identifies vendor specific part number of the PHY.
+ * If the string is set to null, then the vendor specific
+ * part number is not available.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
- UINT32_C(0x8)
- /* When this bit is '1', PTP is enabled for RX on this port. */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
- UINT32_C(0x10)
- /* When this bit is '1', PTP is enabled for TX on this port. */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
- UINT32_C(0x20)
+ char phy_vendor_partnumber[16];
+ uint8_t unused_2[7];
/*
- * Priority setting for tunnel VLAN PRI to CoS mapping.
- * # Each XXX_pri variable shall have a unique priority value
- * when it is being used.
- * # When comparing priorities of mappings, higher value
- * indicates higher priority.
- * For example, a value of 0-3 is returned where 0 is being
- * the lowest priority and 3 is being the highest priority.
- * # If the correspoding CoS mapping is not enabled, then this
- * field should be ignored.
- * # This value indicates the normalized priority value retained
- * in the HWRM.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t tunnel_pri2cos_map_pri;
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************
+ * hwrm_port_mac_cfg *
+ *********************/
+
+
+/* hwrm_port_mac_cfg_input (size:320b/40B) */
+struct hwrm_port_mac_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * Priority setting for DSCP to PRI mapping.
- * # Each XXX_pri variable shall have a unique priority value
- * when it is being used.
- * # When comparing priorities of mappings, higher value
- * indicates higher priority.
- * For example, a value of 0-3 is returned where 0 is being
- * the lowest priority and 3 is being the highest priority.
- * # If the correspoding CoS mapping is not enabled, then this
- * field should be ignored.
- * # This value indicates the normalized priority value retained
- * in the HWRM.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint8_t dscp2pri_map_pri;
+ uint16_t cmpl_ring;
/*
- * This is a 16-bit bit mask that represents the
- * current configuration of time stamp capture of PTP messages
- * on the receive side of this port.
- * If bit 'i' is set, then the receive side of the port
- * is configured to capture the time stamp of every
- * received PTP message with messageType field value set
- * to i.
- * If all bits are set to 0 (i.e. field value set 0),
- * then the receive side of the port is not configured
- * to capture timestamp for PTP messages.
- * If all bits are set to 1, then the receive side of the
- * port is configured to capture timestamp for all PTP
- * messages.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint16_t rx_ts_capture_ptp_msg_type;
+ uint16_t seq_id;
/*
- * This is a 16-bit bit mask that represents the
- * current configuration of time stamp capture of PTP messages
- * on the transmit side of this port.
- * If bit 'i' is set, then the transmit side of the port
- * is configured to capture the time stamp of every
- * received PTP message with messageType field value set
- * to i.
- * If all bits are set to 0 (i.e. field value set 0),
- * then the transmit side of the port is not configured
- * to capture timestamp for PTP messages.
- * If all bits are set to 1, then the transmit side of the
- * port is configured to capture timestamp for all PTP
- * messages.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint16_t tx_ts_capture_ptp_msg_type;
- /* Configuration of CoS fields. */
- uint8_t cos_field_cfg;
- /* Reserved */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
- UINT32_C(0x1)
+ uint16_t target_id;
/*
- * This field is used for selecting VLAN PRI value
- * based on whether one or two VLAN Tags are present in
- * the inner packet headers of tunneled packets or
- * non-tunneled packets.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
- UINT32_C(0x6)
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
- 1
+ uint64_t resp_addr;
/*
- * Select inner VLAN PRI when 1 or 2 VLAN Tags are
- * present in the inner packet headers
+ * In this field, there are a number of CoS mappings related flags
+ * that are used to configure CoS mappings and their corresponding
+ * priorities in the hardware.
+ * For the priorities of CoS mappings, the HWRM uses the following
+ * priority order (high to low) by default:
+ * # vlan pri
+ * # ip_dscp
+ * # tunnel_vlan_pri
+ * # default cos
+ *
+ * A subset of CoS mappings can be enabled.
+ * If a priority is not specified for an enabled CoS mapping, the
+ * priority will be assigned in the above order for the enabled CoS
+ * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
+ * enabled and their priorities are not specified, the following
+ * priority order (high to low) will be used by the HWRM:
+ * # vlan_pri
+ * # ip_dscp
+ * # default cos
+ *
+ * vlan_pri CoS mapping together with default CoS with lower priority
+ * are enabled by default by the HWRM.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
- (UINT32_C(0x0) << 1)
+ uint32_t flags;
/*
- * Select outer VLAN Tag PRI when 2 VLAN Tags are
- * present in the inner packet headers.
- * No VLAN PRI is selected for this configuration
- * if only one VLAN Tag is present in the inner
- * packet headers.
+ * When this bit is '1', this command will configure
+ * the MAC to match the current link state of the PHY.
+ * If the link is not established on the PHY, then this
+ * bit has no effect.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
- (UINT32_C(0x1) << 1)
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
+ UINT32_C(0x1)
/*
- * Select outermost VLAN PRI when 1 or 2 VLAN Tags
- * are present in the inner packet headers
+ * When this bit is set to '1', the inner VLAN PRI to CoS mapping
+ * is requested to be enabled.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
- (UINT32_C(0x2) << 1)
- /* Unspecified */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
- (UINT32_C(0x3) << 1)
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
- HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
+ UINT32_C(0x2)
/*
- * This field is used for selecting tunnel VLAN PRI value
- * based on whether one or two VLAN Tags are present in
- * the tunnel headers of tunneled packets. This selection
- * does not apply to non-tunneled packets.
+ * When this bit is set to '1', tunnel VLAN PRI field to
+ * CoS mapping is requested to be enabled.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
- UINT32_C(0x18)
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
- 3
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
+ UINT32_C(0x4)
/*
- * Select inner VLAN PRI when 1 or 2 VLAN Tags are
- * present in the tunnel packet headers
+ * When this bit is set to '1', the IP DSCP to CoS mapping is
+ * requested to be enabled.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
- (UINT32_C(0x0) << 3)
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
+ UINT32_C(0x8)
/*
- * Select outer VLAN Tag PRI when 2 VLAN Tags are
- * present in the tunnel packet headers.
- * No VLAN PRI is selected for this configuration
- * if only one VLAN Tag is present in the tunnel
- * packet headers.
+ * When this bit is '1', the HWRM is requested to
+ * enable timestamp capture capability on the receive side
+ * of this port.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
- (UINT32_C(0x1) << 3)
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
+ UINT32_C(0x10)
/*
- * Select outermost VLAN PRI when 1 or 2 VLAN Tags
- * are present in the tunnel packet headers
+ * When this bit is '1', the HWRM is requested to
+ * disable timestamp capture capability on the receive side
+ * of this port.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
- (UINT32_C(0x2) << 3)
- /* Unspecified */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
- (UINT32_C(0x3) << 3)
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
- HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
+ UINT32_C(0x20)
/*
- * This field is used to provide default CoS value that
- * has been configured on this port.
+ * When this bit is '1', the HWRM is requested to
+ * enable timestamp capture capability on the transmit side
+ * of this port.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
- UINT32_C(0xe0)
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
- 5
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
+ UINT32_C(0x40)
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When this bit is '1', the HWRM is requested to
+ * disable timestamp capture capability on the transmit side
+ * of this port.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/**************************
- * hwrm_port_mac_ptp_qcfg *
- **************************/
-
-
-/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
-struct hwrm_port_mac_ptp_qcfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
+ UINT32_C(0x80)
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * When this bit is '1', the Out-Of-Box WoL is requested to
+ * be enabled on this port.
*/
- uint16_t cmpl_ring;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
+ UINT32_C(0x100)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * When this bit is '1', the the Out-Of-Box WoL is requested to
+ * be disabled on this port.
*/
- uint16_t seq_id;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
+ UINT32_C(0x200)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * When this bit is set to '1', the inner VLAN PRI to CoS mapping
+ * is requested to be disabled.
*/
- uint16_t target_id;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
+ UINT32_C(0x400)
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * When this bit is set to '1', tunnel VLAN PRI field to
+ * CoS mapping is requested to be disabled.
*/
- uint64_t resp_addr;
- /* Port ID of port that is being queried. */
- uint16_t port_id;
- uint8_t unused_0[6];
-} __attribute__((packed));
-
-/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
-struct hwrm_port_mac_ptp_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
+ UINT32_C(0x800)
/*
- * In this field, a number of PTP related flags
- * are used to indicate configured PTP capabilities.
+ * When this bit is set to '1', the IP DSCP to CoS mapping is
+ * requested to be disabled.
*/
- uint8_t flags;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
+ UINT32_C(0x1000)
+ uint32_t enables;
/*
- * When this bit is set to '1', the PTP related registers are
- * directly accessible by the host.
+ * This bit must be '1' for the ipg field to be
+ * configured.
*/
- #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
UINT32_C(0x1)
/*
- * When this bit is set to '1', the PTP information is accessible
- * via HWRM commands.
+ * This bit must be '1' for the lpbk field to be
+ * configured.
*/
- #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
UINT32_C(0x2)
- uint8_t unused_0[3];
- /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
- uint32_t rx_ts_reg_off_lower;
- /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
- uint32_t rx_ts_reg_off_upper;
- /* Offset of the PTP register for the sequence ID for RX. */
- uint32_t rx_ts_reg_off_seq_id;
- /* Offset of the first PTP source ID for RX. */
- uint32_t rx_ts_reg_off_src_id_0;
- /* Offset of the second PTP source ID for RX. */
- uint32_t rx_ts_reg_off_src_id_1;
- /* Offset of the third PTP source ID for RX. */
- uint32_t rx_ts_reg_off_src_id_2;
- /* Offset of the domain ID for RX. */
- uint32_t rx_ts_reg_off_domain_id;
- /* Offset of the PTP FIFO register for RX. */
- uint32_t rx_ts_reg_off_fifo;
- /* Offset of the PTP advance FIFO register for RX. */
- uint32_t rx_ts_reg_off_fifo_adv;
- /* PTP timestamp granularity for RX. */
- uint32_t rx_ts_reg_off_granularity;
- /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
- uint32_t tx_ts_reg_off_lower;
- /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
- uint32_t tx_ts_reg_off_upper;
- /* Offset of the PTP register for the sequence ID for TX. */
- uint32_t tx_ts_reg_off_seq_id;
- /* Offset of the PTP FIFO register for TX. */
- uint32_t tx_ts_reg_off_fifo;
- /* PTP timestamp granularity for TX. */
- uint32_t tx_ts_reg_off_granularity;
- uint8_t unused_1[7];
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * This bit must be '1' for the vlan_pri2cos_map_pri field to be
+ * configured.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/********************
- * hwrm_port_qstats *
- ********************/
-
-
-/* hwrm_port_qstats_input (size:320b/40B) */
-struct hwrm_port_qstats_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
+ UINT32_C(0x4)
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
+ * configured.
*/
- uint16_t cmpl_ring;
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
+ UINT32_C(0x10)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * This bit must be '1' for the dscp2cos_map_pri field to be
+ * configured.
*/
- uint16_t seq_id;
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
+ UINT32_C(0x20)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
+ * configured.
*/
- uint16_t target_id;
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
+ UINT32_C(0x40)
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
+ * configured.
*/
- uint64_t resp_addr;
- /* Port ID of port that is being queried. */
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
+ UINT32_C(0x80)
+ /*
+ * This bit must be '1' for the cos_field_cfg field to be
+ * configured.
+ */
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
+ UINT32_C(0x100)
+ /* Port ID of port that is to be configured. */
uint16_t port_id;
- uint8_t unused_0[6];
/*
- * This is the host address where
- * Tx port statistics will be stored
+ * This value is used to configure the minimum IPG that will
+ * be sent between packets by this port.
*/
- uint64_t tx_stat_host_addr;
+ uint8_t ipg;
+ /* This value controls the loopback setting for the MAC. */
+ uint8_t lpbk;
+ /* No loopback is selected. Normal operation. */
+ #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
/*
- * This is the host address where
- * Rx port statistics will be stored
+ * The HW will be configured with local loopback such that
+ * host data is sent back to the host without modification.
*/
- uint64_t rx_stat_host_addr;
-} __attribute__((packed));
-
-/* hwrm_port_qstats_output (size:128b/16B) */
-struct hwrm_port_qstats_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* The size of TX port statistics block in bytes. */
- uint16_t tx_stat_size;
- /* The size of RX port statistics block in bytes. */
- uint16_t rx_stat_size;
- uint8_t unused_0[3];
+ #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * The HW will be configured with remote loopback such that
+ * port logic will send packets back out the transmitter that
+ * are received.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/************************
- * hwrm_port_qstats_ext *
- ************************/
-
-
-/* hwrm_port_qstats_ext_input (size:320b/40B) */
-struct hwrm_port_qstats_ext_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
+ #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
+ HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This value controls the priority setting of VLAN PRI to CoS
+ * mapping based on VLAN Tags of inner packet headers of
+ * tunneled packets or packet headers of non-tunneled packets.
+ *
+ * # Each XXX_pri variable shall have a unique priority value
+ * when it is being specified.
+ * # When comparing priorities of mappings, higher value
+ * indicates higher priority.
+ * For example, a value of 0-3 is returned where 0 is being
+ * the lowest priority and 3 is being the highest priority.
*/
- uint16_t cmpl_ring;
+ uint8_t vlan_pri2cos_map_pri;
+ /* Reserved field. */
+ uint8_t reserved1;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * This value controls the priority setting of VLAN PRI to CoS
+ * mapping based on VLAN Tags of tunneled header.
+ * This mapping only applies when tunneled headers
+ * are present.
+ *
+ * # Each XXX_pri variable shall have a unique priority value
+ * when it is being specified.
+ * # When comparing priorities of mappings, higher value
+ * indicates higher priority.
+ * For example, a value of 0-3 is returned where 0 is being
+ * the lowest priority and 3 is being the highest priority.
*/
- uint16_t seq_id;
+ uint8_t tunnel_pri2cos_map_pri;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * This value controls the priority setting of IP DSCP to CoS
+ * mapping based on inner IP header of tunneled packets or
+ * IP header of non-tunneled packets.
+ *
+ * # Each XXX_pri variable shall have a unique priority value
+ * when it is being specified.
+ * # When comparing priorities of mappings, higher value
+ * indicates higher priority.
+ * For example, a value of 0-3 is returned where 0 is being
+ * the lowest priority and 3 is being the highest priority.
*/
- uint16_t target_id;
+ uint8_t dscp2pri_map_pri;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * This is a 16-bit bit mask that is used to request a
+ * specific configuration of time stamp capture of PTP messages
+ * on the receive side of this port.
+ * This field shall be ignored if the ptp_rx_ts_capture_enable
+ * flag is not set in this command.
+ * Otherwise, if bit 'i' is set, then the HWRM is being
+ * requested to configure the receive side of the port to
+ * capture the time stamp of every received PTP message
+ * with messageType field value set to i.
*/
- uint64_t resp_addr;
- /* Port ID of port that is being queried. */
- uint16_t port_id;
+ uint16_t rx_ts_capture_ptp_msg_type;
/*
- * The size of TX port extended
- * statistics block in bytes.
+ * This is a 16-bit bit mask that is used to request a
+ * specific configuration of time stamp capture of PTP messages
+ * on the transmit side of this port.
+ * This field shall be ignored if the ptp_tx_ts_capture_enable
+ * flag is not set in this command.
+ * Otherwise, if bit 'i' is set, then the HWRM is being
+ * requested to configure the transmit sied of the port to
+ * capture the time stamp of every transmitted PTP message
+ * with messageType field value set to i.
*/
- uint16_t tx_stat_size;
+ uint16_t tx_ts_capture_ptp_msg_type;
+ /* Configuration of CoS fields. */
+ uint8_t cos_field_cfg;
+ /* Reserved */
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
+ UINT32_C(0x1)
/*
- * The size of RX port extended
- * statistics block in bytes
+ * This field is used to specify selection of VLAN PRI value
+ * based on whether one or two VLAN Tags are present in
+ * the inner packet headers of tunneled packets or
+ * non-tunneled packets.
+ * This field is valid only if inner VLAN PRI to CoS mapping
+ * is enabled.
+ * If VLAN PRI to CoS mapping is not enabled, then this
+ * field shall be ignored.
*/
- uint16_t rx_stat_size;
- uint8_t unused_0[2];
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
+ UINT32_C(0x6)
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
+ 1
/*
- * This is the host address where
- * Tx port statistics will be stored
+ * Select inner VLAN PRI when 1 or 2 VLAN Tags are
+ * present in the inner packet headers
*/
- uint64_t tx_stat_host_addr;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
+ (UINT32_C(0x0) << 1)
/*
- * This is the host address where
- * Rx port statistics will be stored
+ * Select outer VLAN Tag PRI when 2 VLAN Tags are
+ * present in the inner packet headers.
+ * No VLAN PRI shall be selected for this configuration
+ * if only one VLAN Tag is present in the inner
+ * packet headers.
*/
- uint64_t rx_stat_host_addr;
-} __attribute__((packed));
-
-/* hwrm_port_qstats_ext_output (size:128b/16B) */
-struct hwrm_port_qstats_ext_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* The size of TX port statistics block in bytes. */
- uint16_t tx_stat_size;
- /* The size of RX port statistics block in bytes. */
- uint16_t rx_stat_size;
- uint8_t unused_0[3];
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
+ (UINT32_C(0x1) << 1)
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * Select outermost VLAN PRI when 1 or 2 VLAN Tags
+ * are present in the inner packet headers
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/*************************
- * hwrm_port_lpbk_qstats *
- *************************/
-
-
-/* hwrm_port_lpbk_qstats_input (size:128b/16B) */
-struct hwrm_port_lpbk_qstats_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
+ (UINT32_C(0x2) << 1)
+ /* Unspecified */
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
+ (UINT32_C(0x3) << 1)
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
+ HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This field is used to specify selection of tunnel VLAN
+ * PRI value based on whether one or two VLAN Tags are
+ * present in tunnel headers.
+ * This field is valid only if tunnel VLAN PRI to CoS mapping
+ * is enabled.
+ * If tunnel VLAN PRI to CoS mapping is not enabled, then this
+ * field shall be ignored.
*/
- uint16_t cmpl_ring;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
+ UINT32_C(0x18)
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
+ 3
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Select inner VLAN PRI when 1 or 2 VLAN Tags are
+ * present in the tunnel packet headers
*/
- uint16_t seq_id;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
+ (UINT32_C(0x0) << 3)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * Select outer VLAN Tag PRI when 2 VLAN Tags are
+ * present in the tunnel packet headers.
+ * No tunnel VLAN PRI shall be selected for this
+ * configuration if only one VLAN Tag is present in
+ * the tunnel packet headers.
*/
- uint16_t target_id;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
+ (UINT32_C(0x1) << 3)
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Select outermost VLAN PRI when 1 or 2 VLAN Tags
+ * are present in the tunnel packet headers
*/
- uint64_t resp_addr;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
+ (UINT32_C(0x2) << 3)
+ /* Unspecified */
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
+ (UINT32_C(0x3) << 3)
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
+ HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
+ /*
+ * This field shall be used to provide default CoS value
+ * that has been configured on this port.
+ * This field is valid only if default CoS mapping
+ * is enabled.
+ * If default CoS mapping is not enabled, then this
+ * field shall be ignored.
+ */
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
+ UINT32_C(0xe0)
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
+ 5
+ uint8_t unused_0[3];
} __attribute__((packed));
-/* hwrm_port_lpbk_qstats_output (size:768b/96B) */
-struct hwrm_port_lpbk_qstats_output {
+/* hwrm_port_mac_cfg_output (size:128b/16B) */
+struct hwrm_port_mac_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Number of transmitted unicast frames */
- uint64_t lpbk_ucast_frames;
- /* Number of transmitted multicast frames */
- uint64_t lpbk_mcast_frames;
- /* Number of transmitted broadcast frames */
- uint64_t lpbk_bcast_frames;
- /* Number of transmitted bytes for unicast traffic */
- uint64_t lpbk_ucast_bytes;
- /* Number of transmitted bytes for multicast traffic */
- uint64_t lpbk_mcast_bytes;
- /* Number of transmitted bytes for broadcast traffic */
- uint64_t lpbk_bcast_bytes;
- /* Total Tx Drops for loopback traffic reported by STATS block */
- uint64_t tx_stat_discard;
- /* Total Tx Error Drops for loopback traffic reported by STATS block */
- uint64_t tx_stat_error;
- /* Total Rx Drops for loopback traffic reported by STATS block */
- uint64_t rx_stat_discard;
- /* Total Rx Error Drops for loopback traffic reported by STATS block */
- uint64_t rx_stat_error;
- uint8_t unused_0[7];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/***********************
- * hwrm_port_clr_stats *
- ***********************/
-
-
-/* hwrm_port_clr_stats_input (size:192b/24B) */
-struct hwrm_port_clr_stats_input {
- /* The HWRM command request type. */
- uint16_t req_type;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This is the configured maximum length of Ethernet packet
+ * payload that is allowed to be received on the port.
+ * This value does not include the number of bytes used by
+ * Ethernet header and trailer (CRC).
*/
- uint16_t cmpl_ring;
+ uint16_t mru;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * This is the configured maximum length of Ethernet packet
+ * payload that is allowed to be transmitted on the port.
+ * This value does not include the number of bytes used by
+ * Ethernet header and trailer (CRC).
*/
- uint16_t seq_id;
+ uint16_t mtu;
+ /* Current configuration of the IPG value. */
+ uint8_t ipg;
+ /* Current value of the loopback value. */
+ uint8_t lpbk;
+ /* No loopback is selected. Normal operation. */
+ #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * The HW will be configured with local loopback such that
+ * host data is sent back to the host without modification.
*/
- uint16_t target_id;
+ #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * The HW will be configured with remote loopback such that
+ * port logic will send packets back out the transmitter that
+ * are received.
*/
- uint64_t resp_addr;
- /* Port ID of port that is being queried. */
- uint16_t port_id;
- uint8_t unused_0[6];
-} __attribute__((packed));
-
-/* hwrm_port_clr_stats_output (size:128b/16B) */
-struct hwrm_port_clr_stats_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
+ #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
+ #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
+ HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
+ uint8_t unused_0;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/****************************
- * hwrm_port_lpbk_clr_stats *
- ****************************/
+/**********************
+ * hwrm_port_mac_qcfg *
+ **********************/
-/* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
-struct hwrm_port_lpbk_clr_stats_input {
+/* hwrm_port_mac_qcfg_input (size:192b/24B) */
+struct hwrm_port_mac_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ /* Port ID of port that is to be configured. */
+ uint16_t port_id;
+ uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
-struct hwrm_port_lpbk_clr_stats_output {
+/* hwrm_port_mac_qcfg_output (size:192b/24B) */
+struct hwrm_port_mac_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * This is the configured maximum length of Ethernet packet
+ * payload that is allowed to be received on the port.
+ * This value does not include the number of bytes used by the
+ * Ethernet header and trailer (CRC).
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/**********************
- * hwrm_port_ts_query *
- **********************/
-
-
-/* hwrm_port_ts_query_input (size:192b/24B) */
-struct hwrm_port_ts_query_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint16_t mru;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This is the configured maximum length of Ethernet packet
+ * payload that is allowed to be transmitted on the port.
+ * This value does not include the number of bytes used by the
+ * Ethernet header and trailer (CRC).
*/
- uint16_t cmpl_ring;
+ uint16_t mtu;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * The minimum IPG that will
+ * be sent between packets by this port.
*/
- uint16_t seq_id;
+ uint8_t ipg;
+ /* The loopback setting for the MAC. */
+ uint8_t lpbk;
+ /* No loopback is selected. Normal operation. */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * The HW will be configured with local loopback such that
+ * host data is sent back to the host without modification.
*/
- uint16_t target_id;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * The HW will be configured with remote loopback such that
+ * port logic will send packets back out the transmitter that
+ * are received.
*/
- uint64_t resp_addr;
- uint32_t flags;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
+ HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
/*
- * Enumeration denoting the RX, TX type of the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
+ * Priority setting for VLAN PRI to CoS mapping.
+ * # Each XXX_pri variable shall have a unique priority value
+ * when it is being used.
+ * # When comparing priorities of mappings, higher value
+ * indicates higher priority.
+ * For example, a value of 0-3 is returned where 0 is being
+ * the lowest priority and 3 is being the highest priority.
+ * # If the correspoding CoS mapping is not enabled, then this
+ * field should be ignored.
+ * # This value indicates the normalized priority value retained
+ * in the HWRM.
*/
- #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH UINT32_C(0x1)
- /* tx path */
- #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* rx path */
- #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
- HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
- /* Port ID of port that is being queried. */
- uint16_t port_id;
- uint8_t unused_0[2];
-} __attribute__((packed));
-
-/* hwrm_port_ts_query_output (size:192b/24B) */
-struct hwrm_port_ts_query_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* Timestamp value of PTP message captured. */
- uint64_t ptp_msg_ts;
- /* Sequence ID of the PTP message captured. */
- uint16_t ptp_msg_seqid;
- uint8_t unused_0[5];
+ uint8_t vlan_pri2cos_map_pri;
+ /*
+ * In this field, a number of CoS mappings related flags
+ * are used to indicate configured CoS mappings.
+ */
+ uint8_t flags;
+ /*
+ * When this bit is set to '1', the inner VLAN PRI to CoS mapping
+ * is enabled.
+ */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
+ UINT32_C(0x1)
+ /*
+ * When this bit is set to '1', tunnel VLAN PRI field to
+ * CoS mapping is enabled.
+ */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
+ UINT32_C(0x2)
+ /*
+ * When this bit is set to '1', the IP DSCP to CoS mapping is
+ * enabled.
+ */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
+ UINT32_C(0x4)
+ /*
+ * When this bit is '1', the Out-Of-Box WoL is enabled on this
+ * port.
+ */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
+ UINT32_C(0x8)
+ /* When this bit is '1', PTP is enabled for RX on this port. */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
+ UINT32_C(0x10)
+ /* When this bit is '1', PTP is enabled for TX on this port. */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
+ UINT32_C(0x20)
+ /*
+ * Priority setting for tunnel VLAN PRI to CoS mapping.
+ * # Each XXX_pri variable shall have a unique priority value
+ * when it is being used.
+ * # When comparing priorities of mappings, higher value
+ * indicates higher priority.
+ * For example, a value of 0-3 is returned where 0 is being
+ * the lowest priority and 3 is being the highest priority.
+ * # If the correspoding CoS mapping is not enabled, then this
+ * field should be ignored.
+ * # This value indicates the normalized priority value retained
+ * in the HWRM.
+ */
+ uint8_t tunnel_pri2cos_map_pri;
+ /*
+ * Priority setting for DSCP to PRI mapping.
+ * # Each XXX_pri variable shall have a unique priority value
+ * when it is being used.
+ * # When comparing priorities of mappings, higher value
+ * indicates higher priority.
+ * For example, a value of 0-3 is returned where 0 is being
+ * the lowest priority and 3 is being the highest priority.
+ * # If the correspoding CoS mapping is not enabled, then this
+ * field should be ignored.
+ * # This value indicates the normalized priority value retained
+ * in the HWRM.
+ */
+ uint8_t dscp2pri_map_pri;
+ /*
+ * This is a 16-bit bit mask that represents the
+ * current configuration of time stamp capture of PTP messages
+ * on the receive side of this port.
+ * If bit 'i' is set, then the receive side of the port
+ * is configured to capture the time stamp of every
+ * received PTP message with messageType field value set
+ * to i.
+ * If all bits are set to 0 (i.e. field value set 0),
+ * then the receive side of the port is not configured
+ * to capture timestamp for PTP messages.
+ * If all bits are set to 1, then the receive side of the
+ * port is configured to capture timestamp for all PTP
+ * messages.
+ */
+ uint16_t rx_ts_capture_ptp_msg_type;
+ /*
+ * This is a 16-bit bit mask that represents the
+ * current configuration of time stamp capture of PTP messages
+ * on the transmit side of this port.
+ * If bit 'i' is set, then the transmit side of the port
+ * is configured to capture the time stamp of every
+ * received PTP message with messageType field value set
+ * to i.
+ * If all bits are set to 0 (i.e. field value set 0),
+ * then the transmit side of the port is not configured
+ * to capture timestamp for PTP messages.
+ * If all bits are set to 1, then the transmit side of the
+ * port is configured to capture timestamp for all PTP
+ * messages.
+ */
+ uint16_t tx_ts_capture_ptp_msg_type;
+ /* Configuration of CoS fields. */
+ uint8_t cos_field_cfg;
+ /* Reserved */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
+ UINT32_C(0x1)
+ /*
+ * This field is used for selecting VLAN PRI value
+ * based on whether one or two VLAN Tags are present in
+ * the inner packet headers of tunneled packets or
+ * non-tunneled packets.
+ */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
+ UINT32_C(0x6)
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
+ 1
+ /*
+ * Select inner VLAN PRI when 1 or 2 VLAN Tags are
+ * present in the inner packet headers
+ */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
+ (UINT32_C(0x0) << 1)
+ /*
+ * Select outer VLAN Tag PRI when 2 VLAN Tags are
+ * present in the inner packet headers.
+ * No VLAN PRI is selected for this configuration
+ * if only one VLAN Tag is present in the inner
+ * packet headers.
+ */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
+ (UINT32_C(0x1) << 1)
+ /*
+ * Select outermost VLAN PRI when 1 or 2 VLAN Tags
+ * are present in the inner packet headers
+ */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
+ (UINT32_C(0x2) << 1)
+ /* Unspecified */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
+ (UINT32_C(0x3) << 1)
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
+ HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
+ /*
+ * This field is used for selecting tunnel VLAN PRI value
+ * based on whether one or two VLAN Tags are present in
+ * the tunnel headers of tunneled packets. This selection
+ * does not apply to non-tunneled packets.
+ */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
+ UINT32_C(0x18)
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
+ 3
+ /*
+ * Select inner VLAN PRI when 1 or 2 VLAN Tags are
+ * present in the tunnel packet headers
+ */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
+ (UINT32_C(0x0) << 3)
+ /*
+ * Select outer VLAN Tag PRI when 2 VLAN Tags are
+ * present in the tunnel packet headers.
+ * No VLAN PRI is selected for this configuration
+ * if only one VLAN Tag is present in the tunnel
+ * packet headers.
+ */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
+ (UINT32_C(0x1) << 3)
+ /*
+ * Select outermost VLAN PRI when 1 or 2 VLAN Tags
+ * are present in the tunnel packet headers
+ */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
+ (UINT32_C(0x2) << 3)
+ /* Unspecified */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
+ (UINT32_C(0x3) << 3)
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
+ HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
+ /*
+ * This field is used to provide default CoS value that
+ * has been configured on this port.
+ */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
+ UINT32_C(0xe0)
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
+ 5
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_port_phy_qcaps *
- ***********************/
+/**************************
+ * hwrm_port_mac_ptp_qcfg *
+ **************************/
-/* hwrm_port_phy_qcaps_input (size:192b/24B) */
-struct hwrm_port_phy_qcaps_input {
+/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
+struct hwrm_port_mac_ptp_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_port_phy_qcaps_output (size:192b/24B) */
-struct hwrm_port_phy_qcaps_output {
+/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
+struct hwrm_port_mac_ptp_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* PHY capability flags */
+ /*
+ * In this field, a number of PTP related flags
+ * are used to indicate configured PTP capabilities.
+ */
uint8_t flags;
/*
- * If set to 1, then this field indicates that the
- * link is capable of supporting EEE.
+ * When this bit is set to '1', the PTP related registers are
+ * directly accessible by the host.
*/
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
+ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
UINT32_C(0x1)
/*
- * If set to 1, then this field indicates that the
- * PHY is capable of supporting external loopback.
+ * When this bit is set to '1', the PTP information is accessible
+ * via HWRM commands.
*/
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
+ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
UINT32_C(0x2)
- /*
- * Reserved field. The HWRM shall set this field to 0.
- * An HWRM client shall ignore this field.
- */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
- UINT32_C(0xfc)
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2
- /* Number of front panel ports for this device. */
- uint8_t port_cnt;
- /* Not supported or unknown */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
- /* single port device */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
- /* 2-port device */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
- /* 3-port device */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
- /* 4-port device */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
- HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
- /*
- * This is a bit mask to indicate what speeds are supported
- * as forced speeds on this link.
- * For each speed that can be forced on this link, the
- * corresponding mask bit shall be set to '1'.
- */
- uint16_t supported_speeds_force_mode;
- /* 100Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
- UINT32_C(0x2)
- /* 1Gb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
- UINT32_C(0x8)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
- UINT32_C(0x10)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
- UINT32_C(0x40)
- /* 20Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
- UINT32_C(0x80)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
- UINT32_C(0x100)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
- UINT32_C(0x200)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
- UINT32_C(0x400)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
- UINT32_C(0x800)
- /* 10Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
- UINT32_C(0x1000)
- /* 10Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
- UINT32_C(0x2000)
- /*
- * This is a bit mask to indicate what speeds are supported
- * for autonegotiation on this link.
- * For each speed that can be autonegotiated on this link, the
- * corresponding mask bit shall be set to '1'.
- */
- uint16_t supported_speeds_auto_mode;
- /* 100Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
- UINT32_C(0x2)
- /* 1Gb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
- UINT32_C(0x8)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
- UINT32_C(0x10)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
- UINT32_C(0x40)
- /* 20Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
- UINT32_C(0x80)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
- UINT32_C(0x100)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
- UINT32_C(0x200)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
- UINT32_C(0x400)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
- UINT32_C(0x800)
- /* 10Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
- UINT32_C(0x1000)
- /* 10Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
- UINT32_C(0x2000)
- /*
- * This is a bit mask to indicate what speeds are supported
- * for EEE on this link.
- * For each speed that can be autonegotiated when EEE is enabled
- * on this link, the corresponding mask bit shall be set to '1'.
- * This field is only valid when the eee_suppotred is set to '1'.
- */
- uint16_t supported_speeds_eee_mode;
- /* Reserved */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
- UINT32_C(0x2)
- /* Reserved */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
- UINT32_C(0x8)
- /* Reserved */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
- UINT32_C(0x10)
- /* Reserved */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
- UINT32_C(0x40)
- uint32_t tx_lpi_timer_low;
- /*
- * The lowest value of TX LPI timer that can be set on this link
- * when EEE is enabled. This value is in microseconds.
- * This field is valid only when_eee_supported is set to '1'.
- */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
- UINT32_C(0xffffff)
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
- /*
- * Reserved field. The HWRM shall set this field to 0.
- * An HWRM client shall ignore this field.
- */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
- UINT32_C(0xff000000)
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
- uint32_t valid_tx_lpi_timer_high;
- /*
- * The highest value of TX LPI timer that can be set on this link
- * when EEE is enabled. This value is in microseconds.
- * This field is valid only when_eee_supported is set to '1'.
- */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
- UINT32_C(0xffffff)
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
+ uint8_t unused_0[3];
+ /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
+ uint32_t rx_ts_reg_off_lower;
+ /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
+ uint32_t rx_ts_reg_off_upper;
+ /* Offset of the PTP register for the sequence ID for RX. */
+ uint32_t rx_ts_reg_off_seq_id;
+ /* Offset of the first PTP source ID for RX. */
+ uint32_t rx_ts_reg_off_src_id_0;
+ /* Offset of the second PTP source ID for RX. */
+ uint32_t rx_ts_reg_off_src_id_1;
+ /* Offset of the third PTP source ID for RX. */
+ uint32_t rx_ts_reg_off_src_id_2;
+ /* Offset of the domain ID for RX. */
+ uint32_t rx_ts_reg_off_domain_id;
+ /* Offset of the PTP FIFO register for RX. */
+ uint32_t rx_ts_reg_off_fifo;
+ /* Offset of the PTP advance FIFO register for RX. */
+ uint32_t rx_ts_reg_off_fifo_adv;
+ /* PTP timestamp granularity for RX. */
+ uint32_t rx_ts_reg_off_granularity;
+ /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
+ uint32_t tx_ts_reg_off_lower;
+ /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
+ uint32_t tx_ts_reg_off_upper;
+ /* Offset of the PTP register for the sequence ID for TX. */
+ uint32_t tx_ts_reg_off_seq_id;
+ /* Offset of the PTP FIFO register for TX. */
+ uint32_t tx_ts_reg_off_fifo;
+ /* PTP timestamp granularity for TX. */
+ uint32_t tx_ts_reg_off_granularity;
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
*/
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
- UINT32_C(0xff000000)
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
+ uint8_t valid;
} __attribute__((packed));
-/***************************
- * hwrm_port_phy_i2c_write *
- ***************************/
-
-
-/* hwrm_port_phy_i2c_write_input (size:832b/104B) */
-struct hwrm_port_phy_i2c_write_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+/* Port Tx Statistics Formats */
+/* tx_port_stats (size:3264b/408B) */
+struct tx_port_stats {
+ /* Total Number of 64 Bytes frames transmitted */
+ uint64_t tx_64b_frames;
+ /* Total Number of 65-127 Bytes frames transmitted */
+ uint64_t tx_65b_127b_frames;
+ /* Total Number of 128-255 Bytes frames transmitted */
+ uint64_t tx_128b_255b_frames;
+ /* Total Number of 256-511 Bytes frames transmitted */
+ uint64_t tx_256b_511b_frames;
+ /* Total Number of 512-1023 Bytes frames transmitted */
+ uint64_t tx_512b_1023b_frames;
+ /* Total Number of 1024-1518 Bytes frames transmitted */
+ uint64_t tx_1024b_1518b_frames;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Total Number of each good VLAN (exludes FCS errors)
+ * frame transmitted which is 1519 to 1522 bytes in length
+ * inclusive (excluding framing bits but including FCS bytes).
*/
- uint16_t cmpl_ring;
+ uint64_t tx_good_vlan_frames;
+ /* Total Number of 1519-2047 Bytes frames transmitted */
+ uint64_t tx_1519b_2047b_frames;
+ /* Total Number of 2048-4095 Bytes frames transmitted */
+ uint64_t tx_2048b_4095b_frames;
+ /* Total Number of 4096-9216 Bytes frames transmitted */
+ uint64_t tx_4096b_9216b_frames;
+ /* Total Number of 9217-16383 Bytes frames transmitted */
+ uint64_t tx_9217b_16383b_frames;
+ /* Total Number of good frames transmitted */
+ uint64_t tx_good_frames;
+ /* Total Number of frames transmitted */
+ uint64_t tx_total_frames;
+ /* Total number of unicast frames transmitted */
+ uint64_t tx_ucast_frames;
+ /* Total number of multicast frames transmitted */
+ uint64_t tx_mcast_frames;
+ /* Total number of broadcast frames transmitted */
+ uint64_t tx_bcast_frames;
+ /* Total number of PAUSE control frames transmitted */
+ uint64_t tx_pause_frames;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Total number of PFC/per-priority PAUSE
+ * control frames transmitted
*/
- uint64_t resp_addr;
- uint32_t flags;
- uint32_t enables;
+ uint64_t tx_pfc_frames;
+ /* Total number of jabber frames transmitted */
+ uint64_t tx_jabber_frames;
+ /* Total number of frames transmitted with FCS error */
+ uint64_t tx_fcs_err_frames;
+ /* Total number of control frames transmitted */
+ uint64_t tx_control_frames;
+ /* Total number of over-sized frames transmitted */
+ uint64_t tx_oversz_frames;
+ /* Total number of frames with single deferral */
+ uint64_t tx_single_dfrl_frames;
+ /* Total number of frames with multiple deferrals */
+ uint64_t tx_multi_dfrl_frames;
+ /* Total number of frames with single collision */
+ uint64_t tx_single_coll_frames;
+ /* Total number of frames with multiple collisions */
+ uint64_t tx_multi_coll_frames;
+ /* Total number of frames with late collisions */
+ uint64_t tx_late_coll_frames;
+ /* Total number of frames with excessive collisions */
+ uint64_t tx_excessive_coll_frames;
+ /* Total number of fragmented frames transmitted */
+ uint64_t tx_frag_frames;
+ /* Total number of transmit errors */
+ uint64_t tx_err;
+ /* Total number of single VLAN tagged frames transmitted */
+ uint64_t tx_tagged_frames;
+ /* Total number of double VLAN tagged frames transmitted */
+ uint64_t tx_dbl_tagged_frames;
+ /* Total number of runt frames transmitted */
+ uint64_t tx_runt_frames;
+ /* Total number of TX FIFO under runs */
+ uint64_t tx_fifo_underruns;
/*
- * This bit must be '1' for the page_offset field to be
- * configured.
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 0 transmitted
*/
- #define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_PAGE_OFFSET \
- UINT32_C(0x1)
- /* Port ID of port. */
- uint16_t port_id;
- /* 8-bit I2C slave address. */
- uint8_t i2c_slave_addr;
- uint8_t unused_0;
- /* The page number that is being accessed over I2C. */
- uint16_t page_number;
- /* Offset within the page that is being accessed over I2C. */
- uint16_t page_offset;
+ uint64_t tx_pfc_ena_frames_pri0;
/*
- * Length of data to write, in bytes starting at the offset
- * specified above. If the offset is not specified, then
- * the data shall be written from the beginning of the page.
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 1 transmitted
*/
- uint8_t data_length;
- uint8_t unused_1[7];
- /* Up to 64B of data. */
- uint32_t data[16];
-} __attribute__((packed));
-
-/* hwrm_port_phy_i2c_write_output (size:128b/16B) */
-struct hwrm_port_phy_i2c_write_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
+ uint64_t tx_pfc_ena_frames_pri1;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 2 transmitted
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/**************************
- * hwrm_port_phy_i2c_read *
- **************************/
-
-
-/* hwrm_port_phy_i2c_read_input (size:320b/40B) */
-struct hwrm_port_phy_i2c_read_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint64_t tx_pfc_ena_frames_pri2;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 3 transmitted
*/
- uint16_t cmpl_ring;
+ uint64_t tx_pfc_ena_frames_pri3;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 4 transmitted
*/
- uint16_t seq_id;
+ uint64_t tx_pfc_ena_frames_pri4;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 5 transmitted
*/
- uint16_t target_id;
+ uint64_t tx_pfc_ena_frames_pri5;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 6 transmitted
*/
- uint64_t resp_addr;
- uint32_t flags;
- uint32_t enables;
+ uint64_t tx_pfc_ena_frames_pri6;
/*
- * This bit must be '1' for the page_offset field to be
- * configured.
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 7 transmitted
*/
- #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET \
- UINT32_C(0x1)
- /* Port ID of port. */
- uint16_t port_id;
- /* 8-bit I2C slave address. */
- uint8_t i2c_slave_addr;
- uint8_t unused_0;
- /* The page number that is being accessed over I2C. */
- uint16_t page_number;
- /* Offset within the page that is being accessed over I2C. */
- uint16_t page_offset;
+ uint64_t tx_pfc_ena_frames_pri7;
+ /* Total number of EEE LPI Events on TX */
+ uint64_t tx_eee_lpi_events;
+ /* EEE LPI Duration Counter on TX */
+ uint64_t tx_eee_lpi_duration;
/*
- * Length of data to read, in bytes starting at the offset
- * specified above. If the offset is not specified, then
- * the data shall be read from the beginning of the page.
+ * Total number of Link Level Flow Control (LLFC) messages
+ * transmitted
*/
- uint8_t data_length;
- uint8_t unused_1[7];
+ uint64_t tx_llfc_logical_msgs;
+ /* Total number of HCFC messages transmitted */
+ uint64_t tx_hcfc_msgs;
+ /* Total number of TX collisions */
+ uint64_t tx_total_collisions;
+ /* Total number of transmitted bytes */
+ uint64_t tx_bytes;
+ /* Total number of end-to-end HOL frames */
+ uint64_t tx_xthol_frames;
+ /* Total Tx Drops per Port reported by STATS block */
+ uint64_t tx_stat_discard;
+ /* Total Tx Error Drops per Port reported by STATS block */
+ uint64_t tx_stat_error;
} __attribute__((packed));
-/* hwrm_port_phy_i2c_read_output (size:640b/80B) */
-struct hwrm_port_phy_i2c_read_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* Up to 64B of data. */
- uint32_t data[16];
- uint8_t unused_0[7];
+/* Port Rx Statistics Formats */
+/* rx_port_stats (size:4224b/528B) */
+struct rx_port_stats {
+ /* Total Number of 64 Bytes frames received */
+ uint64_t rx_64b_frames;
+ /* Total Number of 65-127 Bytes frames received */
+ uint64_t rx_65b_127b_frames;
+ /* Total Number of 128-255 Bytes frames received */
+ uint64_t rx_128b_255b_frames;
+ /* Total Number of 256-511 Bytes frames received */
+ uint64_t rx_256b_511b_frames;
+ /* Total Number of 512-1023 Bytes frames received */
+ uint64_t rx_512b_1023b_frames;
+ /* Total Number of 1024-1518 Bytes frames received */
+ uint64_t rx_1024b_1518b_frames;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * Total Number of each good VLAN (exludes FCS errors)
+ * frame received which is 1519 to 1522 bytes in length
+ * inclusive (excluding framing bits but including FCS bytes).
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/*********************
- * hwrm_port_led_cfg *
- *********************/
-
-
-/* hwrm_port_led_cfg_input (size:512b/64B) */
-struct hwrm_port_led_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint64_t rx_good_vlan_frames;
+ /* Total Number of 1519-2047 Bytes frames received */
+ uint64_t rx_1519b_2047b_frames;
+ /* Total Number of 2048-4095 Bytes frames received */
+ uint64_t rx_2048b_4095b_frames;
+ /* Total Number of 4096-9216 Bytes frames received */
+ uint64_t rx_4096b_9216b_frames;
+ /* Total Number of 9217-16383 Bytes frames received */
+ uint64_t rx_9217b_16383b_frames;
+ /* Total number of frames received */
+ uint64_t rx_total_frames;
+ /* Total number of unicast frames received */
+ uint64_t rx_ucast_frames;
+ /* Total number of multicast frames received */
+ uint64_t rx_mcast_frames;
+ /* Total number of broadcast frames received */
+ uint64_t rx_bcast_frames;
+ /* Total number of received frames with FCS error */
+ uint64_t rx_fcs_err_frames;
+ /* Total number of control frames received */
+ uint64_t rx_ctrl_frames;
+ /* Total number of PAUSE frames received */
+ uint64_t rx_pause_frames;
+ /* Total number of PFC frames received */
+ uint64_t rx_pfc_frames;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Total number of frames received with an unsupported
+ * opcode
*/
- uint16_t cmpl_ring;
+ uint64_t rx_unsupported_opcode_frames;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Total number of frames received with an unsupported
+ * DA for pause and PFC
*/
- uint16_t seq_id;
+ uint64_t rx_unsupported_da_pausepfc_frames;
+ /* Total number of frames received with an unsupported SA */
+ uint64_t rx_wrong_sa_frames;
+ /* Total number of received packets with alignment error */
+ uint64_t rx_align_err_frames;
+ /* Total number of received frames with out-of-range length */
+ uint64_t rx_oor_len_frames;
+ /* Total number of received frames with error termination */
+ uint64_t rx_code_err_frames;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * Total number of received frames with a false carrier is
+ * detected during idle, as defined by RX_ER samples active
+ * and RXD is 0xE. The event is reported along with the
+ * statistics generated on the next received frame. Only
+ * one false carrier condition can be detected and logged
+ * between frames.
+ *
+ * Carrier event, valid for 10M/100M speed modes only.
*/
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- uint32_t enables;
+ uint64_t rx_false_carrier_frames;
+ /* Total number of over-sized frames received */
+ uint64_t rx_ovrsz_frames;
+ /* Total number of jabber packets received */
+ uint64_t rx_jbr_frames;
+ /* Total number of received frames with MTU error */
+ uint64_t rx_mtu_err_frames;
+ /* Total number of received frames with CRC match */
+ uint64_t rx_match_crc_frames;
+ /* Total number of frames received promiscuously */
+ uint64_t rx_promiscuous_frames;
/*
- * This bit must be '1' for the led0_id field to be
- * configured.
+ * Total number of received frames with one or two VLAN
+ * tags
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
- UINT32_C(0x1)
+ uint64_t rx_tagged_frames;
+ /* Total number of received frames with two VLAN tags */
+ uint64_t rx_double_tagged_frames;
+ /* Total number of truncated frames received */
+ uint64_t rx_trunc_frames;
+ /* Total number of good frames (without errors) received */
+ uint64_t rx_good_frames;
/*
- * This bit must be '1' for the led0_state field to be
- * configured.
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 0
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
- UINT32_C(0x2)
+ uint64_t rx_pfc_xon2xoff_frames_pri0;
/*
- * This bit must be '1' for the led0_color field to be
- * configured.
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 1
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
- UINT32_C(0x4)
+ uint64_t rx_pfc_xon2xoff_frames_pri1;
/*
- * This bit must be '1' for the led0_blink_on field to be
- * configured.
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 2
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
- UINT32_C(0x8)
+ uint64_t rx_pfc_xon2xoff_frames_pri2;
/*
- * This bit must be '1' for the led0_blink_off field to be
- * configured.
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 3
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
- UINT32_C(0x10)
+ uint64_t rx_pfc_xon2xoff_frames_pri3;
/*
- * This bit must be '1' for the led0_group_id field to be
- * configured.
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 4
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
- UINT32_C(0x20)
+ uint64_t rx_pfc_xon2xoff_frames_pri4;
/*
- * This bit must be '1' for the led1_id field to be
- * configured.
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 5
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
- UINT32_C(0x40)
+ uint64_t rx_pfc_xon2xoff_frames_pri5;
/*
- * This bit must be '1' for the led1_state field to be
- * configured.
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 6
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
- UINT32_C(0x80)
+ uint64_t rx_pfc_xon2xoff_frames_pri6;
/*
- * This bit must be '1' for the led1_color field to be
- * configured.
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 7
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
- UINT32_C(0x100)
+ uint64_t rx_pfc_xon2xoff_frames_pri7;
/*
- * This bit must be '1' for the led1_blink_on field to be
- * configured.
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 0
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
- UINT32_C(0x200)
+ uint64_t rx_pfc_ena_frames_pri0;
/*
- * This bit must be '1' for the led1_blink_off field to be
- * configured.
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 1
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
- UINT32_C(0x400)
+ uint64_t rx_pfc_ena_frames_pri1;
/*
- * This bit must be '1' for the led1_group_id field to be
- * configured.
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 2
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
- UINT32_C(0x800)
+ uint64_t rx_pfc_ena_frames_pri2;
/*
- * This bit must be '1' for the led2_id field to be
- * configured.
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 3
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
- UINT32_C(0x1000)
+ uint64_t rx_pfc_ena_frames_pri3;
/*
- * This bit must be '1' for the led2_state field to be
- * configured.
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 4
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
- UINT32_C(0x2000)
+ uint64_t rx_pfc_ena_frames_pri4;
/*
- * This bit must be '1' for the led2_color field to be
- * configured.
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 5
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
- UINT32_C(0x4000)
+ uint64_t rx_pfc_ena_frames_pri5;
/*
- * This bit must be '1' for the led2_blink_on field to be
- * configured.
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 6
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
- UINT32_C(0x8000)
+ uint64_t rx_pfc_ena_frames_pri6;
/*
- * This bit must be '1' for the led2_blink_off field to be
- * configured.
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 7
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
- UINT32_C(0x10000)
+ uint64_t rx_pfc_ena_frames_pri7;
+ /* Total Number of frames received with SCH CRC error */
+ uint64_t rx_sch_crc_err_frames;
+ /* Total Number of under-sized frames received */
+ uint64_t rx_undrsz_frames;
+ /* Total Number of fragmented frames received */
+ uint64_t rx_frag_frames;
+ /* Total number of RX EEE LPI Events */
+ uint64_t rx_eee_lpi_events;
+ /* EEE LPI Duration Counter on RX */
+ uint64_t rx_eee_lpi_duration;
/*
- * This bit must be '1' for the led2_group_id field to be
- * configured.
+ * Total number of physical type Link Level Flow Control
+ * (LLFC) messages received
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
- UINT32_C(0x20000)
+ uint64_t rx_llfc_physical_msgs;
/*
- * This bit must be '1' for the led3_id field to be
- * configured.
+ * Total number of logical type Link Level Flow Control
+ * (LLFC) messages received
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
- UINT32_C(0x40000)
+ uint64_t rx_llfc_logical_msgs;
/*
- * This bit must be '1' for the led3_state field to be
- * configured.
+ * Total number of logical type Link Level Flow Control
+ * (LLFC) messages received with CRC error
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
- UINT32_C(0x80000)
+ uint64_t rx_llfc_msgs_with_crc_err;
+ /* Total number of HCFC messages received */
+ uint64_t rx_hcfc_msgs;
+ /* Total number of HCFC messages received with CRC error */
+ uint64_t rx_hcfc_msgs_with_crc_err;
+ /* Total number of received bytes */
+ uint64_t rx_bytes;
+ /* Total number of bytes received in runt frames */
+ uint64_t rx_runt_bytes;
+ /* Total number of runt frames received */
+ uint64_t rx_runt_frames;
+ /* Total Rx Discards per Port reported by STATS block */
+ uint64_t rx_stat_discard;
+ uint64_t rx_stat_err;
+} __attribute__((packed));
+
+/********************
+ * hwrm_port_qstats *
+ ********************/
+
+
+/* hwrm_port_qstats_input (size:320b/40B) */
+struct hwrm_port_qstats_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This bit must be '1' for the led3_color field to be
- * configured.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
- UINT32_C(0x100000)
+ uint16_t cmpl_ring;
/*
- * This bit must be '1' for the led3_blink_on field to be
- * configured.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
- UINT32_C(0x200000)
+ uint16_t seq_id;
/*
- * This bit must be '1' for the led3_blink_off field to be
- * configured.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
- UINT32_C(0x400000)
+ uint16_t target_id;
/*
- * This bit must be '1' for the led3_group_id field to be
- * configured.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
- UINT32_C(0x800000)
- /* Port ID of port whose LEDs are configured. */
+ uint64_t resp_addr;
+ /* Port ID of port that is being queried. */
uint16_t port_id;
+ uint8_t unused_0[6];
/*
- * The number of LEDs that are being configured.
- * Up to 4 LEDs can be configured with this command.
+ * This is the host address where
+ * Tx port statistics will be stored
*/
- uint8_t num_leds;
- /* Reserved field. */
- uint8_t rsvd;
- /* An identifier for the LED #0. */
- uint8_t led0_id;
- /* The requested state of the LED #0. */
- uint8_t led0_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
- /* The requested color of LED #0. */
- uint8_t led0_color;
- /* Default */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
- uint8_t unused_0;
- /*
- * If the LED #0 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
- */
- uint16_t led0_blink_on;
- /*
- * If the LED #0 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
- */
- uint16_t led0_blink_off;
- /*
- * An identifier for the group of LEDs that LED #0 belongs
- * to.
- * If set to 0, then the LED #0 shall not be grouped and
- * shall be treated as an individual resource.
- * For all other non-zero values of this field, LED #0 shall
- * be grouped together with the LEDs with the same group ID
- * value.
- */
- uint8_t led0_group_id;
- /* Reserved field. */
- uint8_t rsvd0;
- /* An identifier for the LED #1. */
- uint8_t led1_id;
- /* The requested state of the LED #1. */
- uint8_t led1_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
- /* The requested color of LED #1. */
- uint8_t led1_color;
- /* Default */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
- uint8_t unused_1;
- /*
- * If the LED #1 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
- */
- uint16_t led1_blink_on;
- /*
- * If the LED #1 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
- */
- uint16_t led1_blink_off;
- /*
- * An identifier for the group of LEDs that LED #1 belongs
- * to.
- * If set to 0, then the LED #1 shall not be grouped and
- * shall be treated as an individual resource.
- * For all other non-zero values of this field, LED #1 shall
- * be grouped together with the LEDs with the same group ID
- * value.
- */
- uint8_t led1_group_id;
- /* Reserved field. */
- uint8_t rsvd1;
- /* An identifier for the LED #2. */
- uint8_t led2_id;
- /* The requested state of the LED #2. */
- uint8_t led2_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
- /* The requested color of LED #2. */
- uint8_t led2_color;
- /* Default */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
- uint8_t unused_2;
- /*
- * If the LED #2 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
- */
- uint16_t led2_blink_on;
- /*
- * If the LED #2 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
- */
- uint16_t led2_blink_off;
- /*
- * An identifier for the group of LEDs that LED #2 belongs
- * to.
- * If set to 0, then the LED #2 shall not be grouped and
- * shall be treated as an individual resource.
- * For all other non-zero values of this field, LED #2 shall
- * be grouped together with the LEDs with the same group ID
- * value.
- */
- uint8_t led2_group_id;
- /* Reserved field. */
- uint8_t rsvd2;
- /* An identifier for the LED #3. */
- uint8_t led3_id;
- /* The requested state of the LED #3. */
- uint8_t led3_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
- /* The requested color of LED #3. */
- uint8_t led3_color;
- /* Default */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
- uint8_t unused_3;
- /*
- * If the LED #3 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
- */
- uint16_t led3_blink_on;
- /*
- * If the LED #3 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
- */
- uint16_t led3_blink_off;
+ uint64_t tx_stat_host_addr;
/*
- * An identifier for the group of LEDs that LED #3 belongs
- * to.
- * If set to 0, then the LED #3 shall not be grouped and
- * shall be treated as an individual resource.
- * For all other non-zero values of this field, LED #3 shall
- * be grouped together with the LEDs with the same group ID
- * value.
+ * This is the host address where
+ * Rx port statistics will be stored
*/
- uint8_t led3_group_id;
- /* Reserved field. */
- uint8_t rsvd3;
+ uint64_t rx_stat_host_addr;
} __attribute__((packed));
-/* hwrm_port_led_cfg_output (size:128b/16B) */
-struct hwrm_port_led_cfg_output {
+/* hwrm_port_qstats_output (size:128b/16B) */
+struct hwrm_port_qstats_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /* The size of TX port statistics block in bytes. */
+ uint16_t tx_stat_size;
+ /* The size of RX port statistics block in bytes. */
+ uint16_t rx_stat_size;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_port_led_qcfg *
- **********************/
+/* Port Tx Statistics extended Formats */
+/* tx_port_stats_ext (size:2048b/256B) */
+struct tx_port_stats_ext {
+ /* Total number of tx bytes count on cos queue 0 */
+ uint64_t tx_bytes_cos0;
+ /* Total number of tx bytes count on cos queue 1 */
+ uint64_t tx_bytes_cos1;
+ /* Total number of tx bytes count on cos queue 2 */
+ uint64_t tx_bytes_cos2;
+ /* Total number of tx bytes count on cos queue 3 */
+ uint64_t tx_bytes_cos3;
+ /* Total number of tx bytes count on cos queue 4 */
+ uint64_t tx_bytes_cos4;
+ /* Total number of tx bytes count on cos queue 5 */
+ uint64_t tx_bytes_cos5;
+ /* Total number of tx bytes count on cos queue 6 */
+ uint64_t tx_bytes_cos6;
+ /* Total number of tx bytes count on cos queue 7 */
+ uint64_t tx_bytes_cos7;
+ /* Total number of tx packets count on cos queue 0 */
+ uint64_t tx_packets_cos0;
+ /* Total number of tx packets count on cos queue 1 */
+ uint64_t tx_packets_cos1;
+ /* Total number of tx packets count on cos queue 2 */
+ uint64_t tx_packets_cos2;
+ /* Total number of tx packets count on cos queue 3 */
+ uint64_t tx_packets_cos3;
+ /* Total number of tx packets count on cos queue 4 */
+ uint64_t tx_packets_cos4;
+ /* Total number of tx packets count on cos queue 5 */
+ uint64_t tx_packets_cos5;
+ /* Total number of tx packets count on cos queue 6 */
+ uint64_t tx_packets_cos6;
+ /* Total number of tx packets count on cos queue 7 */
+ uint64_t tx_packets_cos7;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
+ uint64_t pfc_pri0_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
+ uint64_t pfc_pri0_tx_transitions;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
+ uint64_t pfc_pri1_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
+ uint64_t pfc_pri1_tx_transitions;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
+ uint64_t pfc_pri2_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
+ uint64_t pfc_pri2_tx_transitions;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
+ uint64_t pfc_pri3_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
+ uint64_t pfc_pri3_tx_transitions;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
+ uint64_t pfc_pri4_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
+ uint64_t pfc_pri4_tx_transitions;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
+ uint64_t pfc_pri5_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
+ uint64_t pfc_pri5_tx_transitions;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
+ uint64_t pfc_pri6_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
+ uint64_t pfc_pri6_tx_transitions;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
+ uint64_t pfc_pri7_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
+ uint64_t pfc_pri7_tx_transitions;
+} __attribute__((packed));
+
+/* Port Rx Statistics extended Formats */
+/* rx_port_stats_ext (size:2368b/296B) */
+struct rx_port_stats_ext {
+ /* Number of times link state changed to down */
+ uint64_t link_down_events;
+ /* Number of times the idle rings with pause bit are found */
+ uint64_t continuous_pause_events;
+ /* Number of times the active rings pause bit resumed back */
+ uint64_t resume_pause_events;
+ /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
+ uint64_t continuous_roce_pause_events;
+ /* Number of times, the ROCE cos queue PFC is enabled back */
+ uint64_t resume_roce_pause_events;
+ /* Total number of rx bytes count on cos queue 0 */
+ uint64_t rx_bytes_cos0;
+ /* Total number of rx bytes count on cos queue 1 */
+ uint64_t rx_bytes_cos1;
+ /* Total number of rx bytes count on cos queue 2 */
+ uint64_t rx_bytes_cos2;
+ /* Total number of rx bytes count on cos queue 3 */
+ uint64_t rx_bytes_cos3;
+ /* Total number of rx bytes count on cos queue 4 */
+ uint64_t rx_bytes_cos4;
+ /* Total number of rx bytes count on cos queue 5 */
+ uint64_t rx_bytes_cos5;
+ /* Total number of rx bytes count on cos queue 6 */
+ uint64_t rx_bytes_cos6;
+ /* Total number of rx bytes count on cos queue 7 */
+ uint64_t rx_bytes_cos7;
+ /* Total number of rx packets count on cos queue 0 */
+ uint64_t rx_packets_cos0;
+ /* Total number of rx packets count on cos queue 1 */
+ uint64_t rx_packets_cos1;
+ /* Total number of rx packets count on cos queue 2 */
+ uint64_t rx_packets_cos2;
+ /* Total number of rx packets count on cos queue 3 */
+ uint64_t rx_packets_cos3;
+ /* Total number of rx packets count on cos queue 4 */
+ uint64_t rx_packets_cos4;
+ /* Total number of rx packets count on cos queue 5 */
+ uint64_t rx_packets_cos5;
+ /* Total number of rx packets count on cos queue 6 */
+ uint64_t rx_packets_cos6;
+ /* Total number of rx packets count on cos queue 7 */
+ uint64_t rx_packets_cos7;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
+ uint64_t pfc_pri0_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
+ uint64_t pfc_pri0_rx_transitions;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
+ uint64_t pfc_pri1_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
+ uint64_t pfc_pri1_rx_transitions;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
+ uint64_t pfc_pri2_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
+ uint64_t pfc_pri2_rx_transitions;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
+ uint64_t pfc_pri3_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
+ uint64_t pfc_pri3_rx_transitions;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
+ uint64_t pfc_pri4_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
+ uint64_t pfc_pri4_rx_transitions;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
+ uint64_t pfc_pri5_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
+ uint64_t pfc_pri5_rx_transitions;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
+ uint64_t pfc_pri6_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
+ uint64_t pfc_pri6_rx_transitions;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
+ uint64_t pfc_pri7_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
+ uint64_t pfc_pri7_rx_transitions;
+} __attribute__((packed));
+
+/************************
+ * hwrm_port_qstats_ext *
+ ************************/
-/* hwrm_port_led_qcfg_input (size:192b/24B) */
-struct hwrm_port_led_qcfg_input {
+/* hwrm_port_qstats_ext_input (size:320b/40B) */
+struct hwrm_port_qstats_ext_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Port ID of port whose LED configuration is being queried. */
+ /* Port ID of port that is being queried. */
uint16_t port_id;
- uint8_t unused_0[6];
-} __attribute__((packed));
-
-/* hwrm_port_led_qcfg_output (size:448b/56B) */
-struct hwrm_port_led_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
/*
- * The number of LEDs that are configured on this port.
- * Up to 4 LEDs can be returned in the response.
+ * The size of TX port extended
+ * statistics block in bytes.
*/
- uint8_t num_leds;
- /* An identifier for the LED #0. */
- uint8_t led0_id;
- /* The type of LED #0. */
- uint8_t led0_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
- /* The current state of the LED #0. */
- uint8_t led0_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
- /* The color of LED #0. */
- uint8_t led0_color;
- /* Default */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
- uint8_t unused_0;
+ uint16_t tx_stat_size;
/*
- * If the LED #0 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
+ * The size of RX port extended
+ * statistics block in bytes
*/
- uint16_t led0_blink_on;
+ uint16_t rx_stat_size;
+ uint8_t unused_0[2];
/*
- * If the LED #0 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
+ * This is the host address where
+ * Tx port statistics will be stored
*/
- uint16_t led0_blink_off;
+ uint64_t tx_stat_host_addr;
/*
- * An identifier for the group of LEDs that LED #0 belongs
- * to.
- * If set to 0, then the LED #0 is not grouped.
- * For all other non-zero values of this field, LED #0 is
- * grouped together with the LEDs with the same group ID
- * value.
+ * This is the host address where
+ * Rx port statistics will be stored
*/
- uint8_t led0_group_id;
- /* An identifier for the LED #1. */
- uint8_t led1_id;
- /* The type of LED #1. */
- uint8_t led1_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
- /* The current state of the LED #1. */
- uint8_t led1_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
- /* The color of LED #1. */
- uint8_t led1_color;
- /* Default */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
- uint8_t unused_1;
+ uint64_t rx_stat_host_addr;
+} __attribute__((packed));
+
+/* hwrm_port_qstats_ext_output (size:128b/16B) */
+struct hwrm_port_qstats_ext_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The size of TX port statistics block in bytes. */
+ uint16_t tx_stat_size;
+ /* The size of RX port statistics block in bytes. */
+ uint16_t rx_stat_size;
+ /* Total number of active cos queues available. */
+ uint16_t total_active_cos_queues;
+ uint8_t flags;
/*
- * If the LED #1 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
+ * If set to 1, then this field indicates that clear
+ * roce specific counters is supported.
*/
- uint16_t led1_blink_on;
+ #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
+ UINT32_C(0x1)
/*
- * If the LED #1 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint16_t led1_blink_off;
+ uint8_t valid;
+} __attribute__((packed));
+
+/*************************
+ * hwrm_port_lpbk_qstats *
+ *************************/
+
+
+/* hwrm_port_lpbk_qstats_input (size:128b/16B) */
+struct hwrm_port_lpbk_qstats_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * An identifier for the group of LEDs that LED #1 belongs
- * to.
- * If set to 0, then the LED #1 is not grouped.
- * For all other non-zero values of this field, LED #1 is
- * grouped together with the LEDs with the same group ID
- * value.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint8_t led1_group_id;
- /* An identifier for the LED #2. */
- uint8_t led2_id;
- /* The type of LED #2. */
- uint8_t led2_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
- /* The current state of the LED #2. */
- uint8_t led2_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
- /* The color of LED #2. */
- uint8_t led2_color;
- /* Default */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
- uint8_t unused_2;
+ uint16_t cmpl_ring;
/*
- * If the LED #2 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint16_t led2_blink_on;
+ uint16_t seq_id;
/*
- * If the LED #2 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint16_t led2_blink_off;
+ uint16_t target_id;
/*
- * An identifier for the group of LEDs that LED #2 belongs
- * to.
- * If set to 0, then the LED #2 is not grouped.
- * For all other non-zero values of this field, LED #2 is
- * grouped together with the LEDs with the same group ID
- * value.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint8_t led2_group_id;
- /* An identifier for the LED #3. */
- uint8_t led3_id;
- /* The type of LED #3. */
- uint8_t led3_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
- /* The current state of the LED #3. */
- uint8_t led3_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
- /* The color of LED #3. */
- uint8_t led3_color;
- /* Default */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
- uint8_t unused_3;
- /*
- * If the LED #3 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
- */
- uint16_t led3_blink_on;
- /*
- * If the LED #3 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
- */
- uint16_t led3_blink_off;
- /*
- * An identifier for the group of LEDs that LED #3 belongs
- * to.
- * If set to 0, then the LED #3 is not grouped.
- * For all other non-zero values of this field, LED #3 is
- * grouped together with the LEDs with the same group ID
- * value.
- */
- uint8_t led3_group_id;
- uint8_t unused_4[6];
+ uint64_t resp_addr;
+} __attribute__((packed));
+
+/* hwrm_port_lpbk_qstats_output (size:768b/96B) */
+struct hwrm_port_lpbk_qstats_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Number of transmitted unicast frames */
+ uint64_t lpbk_ucast_frames;
+ /* Number of transmitted multicast frames */
+ uint64_t lpbk_mcast_frames;
+ /* Number of transmitted broadcast frames */
+ uint64_t lpbk_bcast_frames;
+ /* Number of transmitted bytes for unicast traffic */
+ uint64_t lpbk_ucast_bytes;
+ /* Number of transmitted bytes for multicast traffic */
+ uint64_t lpbk_mcast_bytes;
+ /* Number of transmitted bytes for broadcast traffic */
+ uint64_t lpbk_bcast_bytes;
+ /* Total Tx Drops for loopback traffic reported by STATS block */
+ uint64_t tx_stat_discard;
+ /* Total Tx Error Drops for loopback traffic reported by STATS block */
+ uint64_t tx_stat_error;
+ /* Total Rx Drops for loopback traffic reported by STATS block */
+ uint64_t rx_stat_discard;
+ /* Total Rx Error Drops for loopback traffic reported by STATS block */
+ uint64_t rx_stat_error;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
} __attribute__((packed));
/***********************
- * hwrm_port_led_qcaps *
+ * hwrm_port_clr_stats *
***********************/
-/* hwrm_port_led_qcaps_input (size:192b/24B) */
-struct hwrm_port_led_qcaps_input {
+/* hwrm_port_clr_stats_input (size:192b/24B) */
+struct hwrm_port_clr_stats_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Port ID of port whose LED configuration is being queried. */
+ /* Port ID of port that is being queried. */
uint16_t port_id;
- uint8_t unused_0[6];
+ uint8_t flags;
+ /*
+ * If set to 1, then this field indicates clear the following RoCE
+ * specific counters.
+ * RoCE associated TX/RX cos counters
+ * CNP associated TX/RX cos counters
+ * RoCE/CNP specific TX/RX flow counters
+ * Firmware will determine the RoCE/CNP cos queue based on qos profile.
+ * This flag is honored only when RoCE is enabled on that port.
+ */
+ #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
+ uint8_t unused_0[5];
} __attribute__((packed));
-/* hwrm_port_led_qcaps_output (size:384b/48B) */
-struct hwrm_port_led_qcaps_output {
+/* hwrm_port_clr_stats_output (size:128b/16B) */
+struct hwrm_port_clr_stats_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * The number of LEDs that are configured on this port.
- * Up to 4 LEDs can be returned in the response.
- */
- uint8_t num_leds;
- /* Reserved for future use. */
- uint8_t unused[3];
- /* An identifier for the LED #0. */
- uint8_t led0_id;
- /* The type of LED #0. */
- uint8_t led0_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
- HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
- /*
- * An identifier for the group of LEDs that LED #0 belongs
- * to.
- * If set to 0, then the LED #0 cannot be grouped.
- * For all other non-zero values of this field, LED #0 is
- * grouped together with the LEDs with the same group ID
- * value.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t led0_group_id;
- uint8_t unused_0;
- /* The states supported by LED #0. */
- uint16_t led0_state_caps;
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_port_phy_qcaps *
+ ***********************/
+
+
+/* hwrm_port_phy_qcaps_input (size:192b/24B) */
+struct hwrm_port_phy_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * If set to 1, this LED is enabled.
- * If set to 0, this LED is disabled.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
- UINT32_C(0x1)
+ uint16_t cmpl_ring;
/*
- * If set to 1, off state is supported on this LED.
- * If set to 0, off state is not supported on this LED.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
- UINT32_C(0x2)
+ uint16_t seq_id;
/*
- * If set to 1, on state is supported on this LED.
- * If set to 0, on state is not supported on this LED.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
- UINT32_C(0x4)
+ uint16_t target_id;
/*
- * If set to 1, blink state is supported on this LED.
- * If set to 0, blink state is not supported on this LED.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
- UINT32_C(0x8)
+ uint64_t resp_addr;
+ /* Port ID of port that is being queried. */
+ uint16_t port_id;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_port_phy_qcaps_output (size:192b/24B) */
+struct hwrm_port_phy_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* PHY capability flags */
+ uint8_t flags;
/*
- * If set to 1, blink_alt state is supported on this LED.
- * If set to 0, blink_alt state is not supported on this LED.
+ * If set to 1, then this field indicates that the
+ * link is capable of supporting EEE.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
- UINT32_C(0x10)
- /* The colors supported by LED #0. */
- uint16_t led0_color_caps;
- /* reserved. */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
UINT32_C(0x1)
/*
- * If set to 1, Amber color is supported on this LED.
- * If set to 0, Amber color is not supported on this LED.
+ * If set to 1, then this field indicates that the
+ * PHY is capable of supporting external loopback.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
UINT32_C(0x2)
/*
- * If set to 1, Green color is supported on this LED.
- * If set to 0, Green color is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
- UINT32_C(0x4)
- /* An identifier for the LED #1. */
- uint8_t led1_id;
- /* The type of LED #1. */
- uint8_t led1_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
- HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
- /*
- * An identifier for the group of LEDs that LED #1 belongs
- * to.
- * If set to 0, then the LED #0 cannot be grouped.
- * For all other non-zero values of this field, LED #0 is
- * grouped together with the LEDs with the same group ID
- * value.
+ * Reserved field. The HWRM shall set this field to 0.
+ * An HWRM client shall ignore this field.
*/
- uint8_t led1_group_id;
- uint8_t unused_1;
- /* The states supported by LED #1. */
- uint16_t led1_state_caps;
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
+ UINT32_C(0xfc)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2
+ /* Number of front panel ports for this device. */
+ uint8_t port_cnt;
+ /* Not supported or unknown */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
+ /* single port device */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
+ /* 2-port device */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
+ /* 3-port device */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
+ /* 4-port device */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
+ HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
/*
- * If set to 1, this LED is enabled.
- * If set to 0, this LED is disabled.
+ * This is a bit mask to indicate what speeds are supported
+ * as forced speeds on this link.
+ * For each speed that can be forced on this link, the
+ * corresponding mask bit shall be set to '1'.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
+ uint16_t supported_speeds_force_mode;
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
UINT32_C(0x1)
- /*
- * If set to 1, off state is supported on this LED.
- * If set to 0, off state is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
UINT32_C(0x2)
- /*
- * If set to 1, on state is supported on this LED.
- * If set to 0, on state is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
+ UINT32_C(0x8)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
+ UINT32_C(0x10)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
+ UINT32_C(0x40)
+ /* 20Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
+ UINT32_C(0x80)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
+ UINT32_C(0x100)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
+ UINT32_C(0x200)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
+ UINT32_C(0x400)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
+ UINT32_C(0x800)
+ /* 10Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
+ UINT32_C(0x1000)
+ /* 10Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
+ UINT32_C(0x2000)
/*
- * If set to 1, blink state is supported on this LED.
- * If set to 0, blink state is not supported on this LED.
+ * This is a bit mask to indicate what speeds are supported
+ * for autonegotiation on this link.
+ * For each speed that can be autonegotiated on this link, the
+ * corresponding mask bit shall be set to '1'.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
+ uint16_t supported_speeds_auto_mode;
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
+ UINT32_C(0x2)
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
UINT32_C(0x8)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
+ UINT32_C(0x10)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
+ UINT32_C(0x40)
+ /* 20Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
+ UINT32_C(0x80)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
+ UINT32_C(0x100)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
+ UINT32_C(0x200)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
+ UINT32_C(0x400)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
+ UINT32_C(0x800)
+ /* 10Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
+ UINT32_C(0x1000)
+ /* 10Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
+ UINT32_C(0x2000)
/*
- * If set to 1, blink_alt state is supported on this LED.
- * If set to 0, blink_alt state is not supported on this LED.
+ * This is a bit mask to indicate what speeds are supported
+ * for EEE on this link.
+ * For each speed that can be autonegotiated when EEE is enabled
+ * on this link, the corresponding mask bit shall be set to '1'.
+ * This field is only valid when the eee_suppotred is set to '1'.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
- UINT32_C(0x10)
- /* The colors supported by LED #1. */
- uint16_t led1_color_caps;
- /* reserved. */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
+ uint16_t supported_speeds_eee_mode;
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
+ UINT32_C(0x2)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
+ UINT32_C(0x8)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
+ UINT32_C(0x10)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
+ UINT32_C(0x40)
+ uint32_t tx_lpi_timer_low;
/*
- * If set to 1, Amber color is supported on this LED.
- * If set to 0, Amber color is not supported on this LED.
+ * The lowest value of TX LPI timer that can be set on this link
+ * when EEE is enabled. This value is in microseconds.
+ * This field is valid only when_eee_supported is set to '1'.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
- UINT32_C(0x2)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
+ UINT32_C(0xffffff)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
/*
- * If set to 1, Green color is supported on this LED.
- * If set to 0, Green color is not supported on this LED.
+ * Reserved field. The HWRM shall set this field to 0.
+ * An HWRM client shall ignore this field.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
- UINT32_C(0x4)
- /* An identifier for the LED #2. */
- uint8_t led2_id;
- /* The type of LED #2. */
- uint8_t led2_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
- HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
+ uint32_t valid_tx_lpi_timer_high;
/*
- * An identifier for the group of LEDs that LED #0 belongs
- * to.
- * If set to 0, then the LED #0 cannot be grouped.
- * For all other non-zero values of this field, LED #0 is
- * grouped together with the LEDs with the same group ID
- * value.
+ * The highest value of TX LPI timer that can be set on this link
+ * when EEE is enabled. This value is in microseconds.
+ * This field is valid only when_eee_supported is set to '1'.
*/
- uint8_t led2_group_id;
- uint8_t unused_2;
- /* The states supported by LED #2. */
- uint16_t led2_state_caps;
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
+ UINT32_C(0xffffff)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
/*
- * If set to 1, this LED is enabled.
- * If set to 0, this LED is disabled.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
- UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
+} __attribute__((packed));
+
+/*********************
+ * hwrm_port_led_cfg *
+ *********************/
+
+
+/* hwrm_port_led_cfg_input (size:512b/64B) */
+struct hwrm_port_led_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * If set to 1, off state is supported on this LED.
- * If set to 0, off state is not supported on this LED.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
- UINT32_C(0x2)
+ uint16_t cmpl_ring;
/*
- * If set to 1, on state is supported on this LED.
- * If set to 0, on state is not supported on this LED.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
- UINT32_C(0x4)
+ uint16_t seq_id;
/*
- * If set to 1, blink state is supported on this LED.
- * If set to 0, blink state is not supported on this LED.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
- UINT32_C(0x8)
+ uint16_t target_id;
/*
- * If set to 1, blink_alt state is supported on this LED.
- * If set to 0, blink_alt state is not supported on this LED.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
- UINT32_C(0x10)
- /* The colors supported by LED #2. */
- uint16_t led2_color_caps;
- /* reserved. */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
+ uint64_t resp_addr;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the led0_id field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
UINT32_C(0x1)
/*
- * If set to 1, Amber color is supported on this LED.
- * If set to 0, Amber color is not supported on this LED.
+ * This bit must be '1' for the led0_state field to be
+ * configured.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
UINT32_C(0x2)
/*
- * If set to 1, Green color is supported on this LED.
- * If set to 0, Green color is not supported on this LED.
+ * This bit must be '1' for the led0_color field to be
+ * configured.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
UINT32_C(0x4)
- /* An identifier for the LED #3. */
- uint8_t led3_id;
- /* The type of LED #3. */
- uint8_t led3_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
- HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
/*
- * An identifier for the group of LEDs that LED #3 belongs
- * to.
- * If set to 0, then the LED #0 cannot be grouped.
- * For all other non-zero values of this field, LED #0 is
- * grouped together with the LEDs with the same group ID
- * value.
+ * This bit must be '1' for the led0_blink_on field to be
+ * configured.
*/
- uint8_t led3_group_id;
- uint8_t unused_3;
- /* The states supported by LED #3. */
- uint16_t led3_state_caps;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
+ UINT32_C(0x8)
/*
- * If set to 1, this LED is enabled.
- * If set to 0, this LED is disabled.
+ * This bit must be '1' for the led0_blink_off field to be
+ * configured.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
- UINT32_C(0x1)
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
+ UINT32_C(0x10)
/*
- * If set to 1, off state is supported on this LED.
- * If set to 0, off state is not supported on this LED.
+ * This bit must be '1' for the led0_group_id field to be
+ * configured.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
- UINT32_C(0x2)
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
+ UINT32_C(0x20)
/*
- * If set to 1, on state is supported on this LED.
- * If set to 0, on state is not supported on this LED.
+ * This bit must be '1' for the led1_id field to be
+ * configured.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
- UINT32_C(0x4)
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
+ UINT32_C(0x40)
/*
- * If set to 1, blink state is supported on this LED.
- * If set to 0, blink state is not supported on this LED.
+ * This bit must be '1' for the led1_state field to be
+ * configured.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
- UINT32_C(0x8)
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
+ UINT32_C(0x80)
/*
- * If set to 1, blink_alt state is supported on this LED.
- * If set to 0, blink_alt state is not supported on this LED.
+ * This bit must be '1' for the led1_color field to be
+ * configured.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
- UINT32_C(0x10)
- /* The colors supported by LED #3. */
- uint16_t led3_color_caps;
- /* reserved. */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
- UINT32_C(0x1)
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
+ UINT32_C(0x100)
/*
- * If set to 1, Amber color is supported on this LED.
- * If set to 0, Amber color is not supported on this LED.
+ * This bit must be '1' for the led1_blink_on field to be
+ * configured.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
- UINT32_C(0x2)
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
+ UINT32_C(0x200)
/*
- * If set to 1, Green color is supported on this LED.
- * If set to 0, Green color is not supported on this LED.
+ * This bit must be '1' for the led1_blink_off field to be
+ * configured.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
- UINT32_C(0x4)
- uint8_t unused_4[3];
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
+ UINT32_C(0x400)
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * This bit must be '1' for the led1_group_id field to be
+ * configured.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/***********************
- * hwrm_queue_qportcfg *
- ***********************/
-
-
-/* hwrm_queue_qportcfg_input (size:192b/24B) */
-struct hwrm_queue_qportcfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
+ UINT32_C(0x800)
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This bit must be '1' for the led2_id field to be
+ * configured.
*/
- uint16_t cmpl_ring;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
+ UINT32_C(0x1000)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * This bit must be '1' for the led2_state field to be
+ * configured.
*/
- uint16_t seq_id;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
+ UINT32_C(0x2000)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * This bit must be '1' for the led2_color field to be
+ * configured.
*/
- uint16_t target_id;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
+ UINT32_C(0x4000)
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * This bit must be '1' for the led2_blink_on field to be
+ * configured.
*/
- uint64_t resp_addr;
- uint32_t flags;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
+ UINT32_C(0x8000)
/*
- * Enumeration denoting the RX, TX type of the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
+ * This bit must be '1' for the led2_blink_off field to be
+ * configured.
*/
- #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
- /* tx path */
- #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* rx path */
- #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
- HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
+ UINT32_C(0x10000)
/*
- * Port ID of port for which the queue configuration is being
- * queried. This field is only required when sent by IPC.
+ * This bit must be '1' for the led2_group_id field to be
+ * configured.
*/
- uint16_t port_id;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
+ UINT32_C(0x20000)
/*
- * Drivers will set this capability when it can use
- * queue_idx_service_profile to map the queues to application.
+ * This bit must be '1' for the led3_id field to be
+ * configured.
*/
- uint8_t drv_qmap_cap;
- /* disabled */
- #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
- /* enabled */
- #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
- #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
- HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
- uint8_t unused_0;
-} __attribute__((packed));
-
-/* hwrm_queue_qportcfg_output (size:256b/32B) */
-struct hwrm_queue_qportcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
+ UINT32_C(0x40000)
/*
- * The maximum number of queues that can be configured on this
- * port.
- * Valid values range from 1 through 8.
+ * This bit must be '1' for the led3_state field to be
+ * configured.
*/
- uint8_t max_configurable_queues;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
+ UINT32_C(0x80000)
/*
- * The maximum number of lossless queues that can be configured
- * on this port.
- * Valid values range from 0 through 8.
+ * This bit must be '1' for the led3_color field to be
+ * configured.
*/
- uint8_t max_configurable_lossless_queues;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
+ UINT32_C(0x100000)
/*
- * Bitmask indicating which queues can be configured by the
- * hwrm_queue_cfg command.
- *
- * Each bit represents a specific queue where bit 0 represents
- * queue 0 and bit 7 represents queue 7.
- * # A value of 0 indicates that the queue is not configurable
- * by the hwrm_queue_cfg command.
- * # A value of 1 indicates that the queue is configurable.
- * # A hwrm_queue_cfg command shall return error when trying to
- * configure a queue not configurable.
+ * This bit must be '1' for the led3_blink_on field to be
+ * configured.
*/
- uint8_t queue_cfg_allowed;
- /* Information about queue configuration. */
- uint8_t queue_cfg_info;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
+ UINT32_C(0x200000)
/*
- * If this flag is set to '1', then the queues are
- * configured asymmetrically on TX and RX sides.
- * If this flag is set to '0', then the queues are
- * configured symmetrically on TX and RX sides. For
- * symmetric configuration, the queue configuration
- * including queue ids and service profiles on the
- * TX side is the same as the corresponding queue
- * configuration on the RX side.
+ * This bit must be '1' for the led3_blink_off field to be
+ * configured.
*/
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
- UINT32_C(0x1)
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
+ UINT32_C(0x400000)
/*
- * Bitmask indicating which queues can be configured by the
- * hwrm_queue_pfcenable_cfg command.
- *
- * Each bit represents a specific priority where bit 0 represents
- * priority 0 and bit 7 represents priority 7.
- * # A value of 0 indicates that the priority is not configurable by
- * the hwrm_queue_pfcenable_cfg command.
- * # A value of 1 indicates that the priority is configurable.
- * # A hwrm_queue_pfcenable_cfg command shall return error when
- * trying to configure a priority that is not configurable.
+ * This bit must be '1' for the led3_group_id field to be
+ * configured.
*/
- uint8_t queue_pfcenable_cfg_allowed;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
+ UINT32_C(0x800000)
+ /* Port ID of port whose LEDs are configured. */
+ uint16_t port_id;
/*
- * Bitmask indicating which queues can be configured by the
- * hwrm_queue_pri2cos_cfg command.
- *
- * Each bit represents a specific queue where bit 0 represents
- * queue 0 and bit 7 represents queue 7.
- * # A value of 0 indicates that the queue is not configurable
- * by the hwrm_queue_pri2cos_cfg command.
- * # A value of 1 indicates that the queue is configurable.
- * # A hwrm_queue_pri2cos_cfg command shall return error when
- * trying to configure a queue that is not configurable.
+ * The number of LEDs that are being configured.
+ * Up to 4 LEDs can be configured with this command.
*/
- uint8_t queue_pri2cos_cfg_allowed;
+ uint8_t num_leds;
+ /* Reserved field. */
+ uint8_t rsvd;
+ /* An identifier for the LED #0. */
+ uint8_t led0_id;
+ /* The requested state of the LED #0. */
+ uint8_t led0_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
+ /* The requested color of LED #0. */
+ uint8_t led0_color;
+ /* Default */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
+ uint8_t unused_0;
/*
- * Bitmask indicating which queues can be configured by the
- * hwrm_queue_pri2cos_cfg command.
- *
- * Each bit represents a specific queue where bit 0 represents
- * queue 0 and bit 7 represents queue 7.
- * # A value of 0 indicates that the queue is not configurable
- * by the hwrm_queue_pri2cos_cfg command.
- * # A value of 1 indicates that the queue is configurable.
- * # A hwrm_queue_pri2cos_cfg command shall return error when
- * trying to configure a queue not configurable.
+ * If the LED #0 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
*/
- uint8_t queue_cos2bw_cfg_allowed;
+ uint16_t led0_blink_on;
/*
- * ID of CoS Queue 0.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * If the LED #0 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
*/
- uint8_t queue_id0;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id0_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
+ uint16_t led0_blink_off;
/*
- * ID of CoS Queue 1.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * An identifier for the group of LEDs that LED #0 belongs
+ * to.
+ * If set to 0, then the LED #0 shall not be grouped and
+ * shall be treated as an individual resource.
+ * For all other non-zero values of this field, LED #0 shall
+ * be grouped together with the LEDs with the same group ID
+ * value.
*/
- uint8_t queue_id1;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id1_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
+ uint8_t led0_group_id;
+ /* Reserved field. */
+ uint8_t rsvd0;
+ /* An identifier for the LED #1. */
+ uint8_t led1_id;
+ /* The requested state of the LED #1. */
+ uint8_t led1_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
+ /* The requested color of LED #1. */
+ uint8_t led1_color;
+ /* Default */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
+ uint8_t unused_1;
/*
- * ID of CoS Queue 2.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * If the LED #1 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
*/
- uint8_t queue_id2;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id2_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
+ uint16_t led1_blink_on;
/*
- * ID of CoS Queue 3.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * If the LED #1 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
*/
- uint8_t queue_id3;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id3_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
+ uint16_t led1_blink_off;
/*
- * ID of CoS Queue 4.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * An identifier for the group of LEDs that LED #1 belongs
+ * to.
+ * If set to 0, then the LED #1 shall not be grouped and
+ * shall be treated as an individual resource.
+ * For all other non-zero values of this field, LED #1 shall
+ * be grouped together with the LEDs with the same group ID
+ * value.
*/
- uint8_t queue_id4;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id4_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
+ uint8_t led1_group_id;
+ /* Reserved field. */
+ uint8_t rsvd1;
+ /* An identifier for the LED #2. */
+ uint8_t led2_id;
+ /* The requested state of the LED #2. */
+ uint8_t led2_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
+ /* The requested color of LED #2. */
+ uint8_t led2_color;
+ /* Default */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
+ uint8_t unused_2;
/*
- * ID of CoS Queue 5.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * If the LED #2 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
*/
- uint8_t queue_id5;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id5_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
+ uint16_t led2_blink_on;
/*
- * ID of CoS Queue 6.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * If the LED #2 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
*/
- uint8_t queue_id6;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id6_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
+ uint16_t led2_blink_off;
/*
- * ID of CoS Queue 7.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * An identifier for the group of LEDs that LED #2 belongs
+ * to.
+ * If set to 0, then the LED #2 shall not be grouped and
+ * shall be treated as an individual resource.
+ * For all other non-zero values of this field, LED #2 shall
+ * be grouped together with the LEDs with the same group ID
+ * value.
*/
- uint8_t queue_id7;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id7_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
+ uint8_t led2_group_id;
+ /* Reserved field. */
+ uint8_t rsvd2;
+ /* An identifier for the LED #3. */
+ uint8_t led3_id;
+ /* The requested state of the LED #3. */
+ uint8_t led3_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
+ /* The requested color of LED #3. */
+ uint8_t led3_color;
+ /* Default */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
+ uint8_t unused_3;
+ /*
+ * If the LED #3 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
+ */
+ uint16_t led3_blink_on;
+ /*
+ * If the LED #3 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
+ */
+ uint16_t led3_blink_off;
+ /*
+ * An identifier for the group of LEDs that LED #3 belongs
+ * to.
+ * If set to 0, then the LED #3 shall not be grouped and
+ * shall be treated as an individual resource.
+ * For all other non-zero values of this field, LED #3 shall
+ * be grouped together with the LEDs with the same group ID
+ * value.
+ */
+ uint8_t led3_group_id;
+ /* Reserved field. */
+ uint8_t rsvd3;
+} __attribute__((packed));
+
+/* hwrm_port_led_cfg_output (size:128b/16B) */
+struct hwrm_port_led_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/*******************
- * hwrm_queue_qcfg *
- *******************/
+/**********************
+ * hwrm_port_led_qcfg *
+ **********************/
-/* hwrm_queue_qcfg_input (size:192b/24B) */
-struct hwrm_queue_qcfg_input {
+/* hwrm_port_led_qcfg_input (size:192b/24B) */
+struct hwrm_port_led_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /*
- * Enumeration denoting the RX, TX type of the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
- */
- #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
- /* tx path */
- #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* rx path */
- #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
- HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
- /* Queue ID of the queue. */
- uint32_t queue_id;
+ /* Port ID of port whose LED configuration is being queried. */
+ uint16_t port_id;
+ uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_queue_qcfg_output (size:128b/16B) */
-struct hwrm_queue_qcfg_output {
+/* hwrm_port_led_qcfg_output (size:448b/56B) */
+struct hwrm_port_led_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
/* The length of the response data in number of bytes. */
uint16_t resp_len;
/*
- * This value is a the estimate packet length used in the
- * TX arbiter.
- */
- uint32_t queue_len;
- /* This value is applicable to CoS queues only. */
- uint8_t service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
- /* Lossless */
- #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
- #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
- /* Information about queue configuration. */
- uint8_t queue_cfg_info;
- /*
- * If this flag is set to '1', then the queue is
- * configured asymmetrically on TX and RX sides.
- * If this flag is set to '0', then this queue is
- * configured symmetrically on TX and RX sides.
+ * The number of LEDs that are configured on this port.
+ * Up to 4 LEDs can be returned in the response.
*/
- #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
- UINT32_C(0x1)
+ uint8_t num_leds;
+ /* An identifier for the LED #0. */
+ uint8_t led0_id;
+ /* The type of LED #0. */
+ uint8_t led0_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
+ /* The current state of the LED #0. */
+ uint8_t led0_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
+ /* The color of LED #0. */
+ uint8_t led0_color;
+ /* Default */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
uint8_t unused_0;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * If the LED #0 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/******************
- * hwrm_queue_cfg *
- ******************/
-
-
-/* hwrm_queue_cfg_input (size:320b/40B) */
-struct hwrm_queue_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint16_t led0_blink_on;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * If the LED #0 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
*/
- uint16_t cmpl_ring;
+ uint16_t led0_blink_off;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * An identifier for the group of LEDs that LED #0 belongs
+ * to.
+ * If set to 0, then the LED #0 is not grouped.
+ * For all other non-zero values of this field, LED #0 is
+ * grouped together with the LEDs with the same group ID
+ * value.
*/
- uint16_t seq_id;
+ uint8_t led0_group_id;
+ /* An identifier for the LED #1. */
+ uint8_t led1_id;
+ /* The type of LED #1. */
+ uint8_t led1_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
+ /* The current state of the LED #1. */
+ uint8_t led1_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
+ /* The color of LED #1. */
+ uint8_t led1_color;
+ /* Default */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
+ uint8_t unused_1;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * If the LED #1 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
*/
- uint16_t target_id;
+ uint16_t led1_blink_on;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * If the LED #1 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
*/
- uint64_t resp_addr;
- uint32_t flags;
+ uint16_t led1_blink_off;
/*
- * Enumeration denoting the RX, TX, or both directions applicable to the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
+ * An identifier for the group of LEDs that LED #1 belongs
+ * to.
+ * If set to 0, then the LED #1 is not grouped.
+ * For all other non-zero values of this field, LED #1 is
+ * grouped together with the LEDs with the same group ID
+ * value.
*/
- #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
- #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
- /* tx path */
- #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* rx path */
- #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- /* Bi-directional (Symmetrically applicable to TX and RX paths) */
- #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
- #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
- HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
- uint32_t enables;
+ uint8_t led1_group_id;
+ /* An identifier for the LED #2. */
+ uint8_t led2_id;
+ /* The type of LED #2. */
+ uint8_t led2_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
+ /* The current state of the LED #2. */
+ uint8_t led2_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
+ /* The color of LED #2. */
+ uint8_t led2_color;
+ /* Default */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
+ uint8_t unused_2;
/*
- * This bit must be '1' for the dflt_len field to be
- * configured.
+ * If the LED #2 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
*/
- #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
+ uint16_t led2_blink_on;
/*
- * This bit must be '1' for the service_profile field to be
- * configured.
+ * If the LED #2 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
*/
- #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
- /* Queue ID of queue that is to be configured by this function. */
- uint32_t queue_id;
+ uint16_t led2_blink_off;
/*
- * This value is a the estimate packet length used in the
- * TX arbiter.
- * Set to 0xFF... (All Fs) to not adjust this value.
+ * An identifier for the group of LEDs that LED #2 belongs
+ * to.
+ * If set to 0, then the LED #2 is not grouped.
+ * For all other non-zero values of this field, LED #2 is
+ * grouped together with the LEDs with the same group ID
+ * value.
*/
- uint32_t dflt_len;
- /* This value is applicable to CoS queues only. */
- uint8_t service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
- /* Lossless */
- #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
- #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
- uint8_t unused_0[7];
-} __attribute__((packed));
-
-/* hwrm_queue_cfg_output (size:128b/16B) */
-struct hwrm_queue_cfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
+ uint8_t led2_group_id;
+ /* An identifier for the LED #3. */
+ uint8_t led3_id;
+ /* The type of LED #3. */
+ uint8_t led3_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
+ /* The current state of the LED #3. */
+ uint8_t led3_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
+ /* The color of LED #3. */
+ uint8_t led3_color;
+ /* Default */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
+ uint8_t unused_3;
+ /*
+ * If the LED #3 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
+ */
+ uint16_t led3_blink_on;
+ /*
+ * If the LED #3 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
+ */
+ uint16_t led3_blink_off;
+ /*
+ * An identifier for the group of LEDs that LED #3 belongs
+ * to.
+ * If set to 0, then the LED #3 is not grouped.
+ * For all other non-zero values of this field, LED #3 is
+ * grouped together with the LEDs with the same group ID
+ * value.
+ */
+ uint8_t led3_group_id;
+ uint8_t unused_4[6];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/*****************************
- * hwrm_queue_pfcenable_qcfg *
- *****************************/
+/***********************
+ * hwrm_port_led_qcaps *
+ ***********************/
-/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
-struct hwrm_queue_pfcenable_qcfg_input {
+/* hwrm_port_led_qcaps_input (size:192b/24B) */
+struct hwrm_port_led_qcaps_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure pri2cos mapping on this port.
- */
+ /* Port ID of port whose LED configuration is being queried. */
uint16_t port_id;
uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
-struct hwrm_queue_pfcenable_qcfg_output {
+/* hwrm_port_led_qcaps_output (size:384b/48B) */
+struct hwrm_port_led_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint32_t flags;
- /* If set to 1, then PFC is enabled on PRI 0. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
- UINT32_C(0x1)
- /* If set to 1, then PFC is enabled on PRI 1. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
- UINT32_C(0x2)
- /* If set to 1, then PFC is enabled on PRI 2. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
- UINT32_C(0x4)
- /* If set to 1, then PFC is enabled on PRI 3. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
- UINT32_C(0x8)
- /* If set to 1, then PFC is enabled on PRI 4. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
- UINT32_C(0x10)
- /* If set to 1, then PFC is enabled on PRI 5. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
- UINT32_C(0x20)
- /* If set to 1, then PFC is enabled on PRI 6. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
- UINT32_C(0x40)
- /* If set to 1, then PFC is enabled on PRI 7. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
- UINT32_C(0x80)
- uint8_t unused_0[3];
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * The number of LEDs that are configured on this port.
+ * Up to 4 LEDs can be returned in the response.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/****************************
- * hwrm_queue_pfcenable_cfg *
- ****************************/
-
-
-/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
-struct hwrm_queue_pfcenable_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint8_t num_leds;
+ /* Reserved for future use. */
+ uint8_t unused[3];
+ /* An identifier for the LED #0. */
+ uint8_t led0_id;
+ /* The type of LED #0. */
+ uint8_t led0_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
+ HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * An identifier for the group of LEDs that LED #0 belongs
+ * to.
+ * If set to 0, then the LED #0 cannot be grouped.
+ * For all other non-zero values of this field, LED #0 is
+ * grouped together with the LEDs with the same group ID
+ * value.
*/
- uint16_t cmpl_ring;
+ uint8_t led0_group_id;
+ uint8_t unused_0;
+ /* The states supported by LED #0. */
+ uint16_t led0_state_caps;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * If set to 1, this LED is enabled.
+ * If set to 0, this LED is disabled.
*/
- uint16_t seq_id;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
+ UINT32_C(0x1)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * If set to 1, off state is supported on this LED.
+ * If set to 0, off state is not supported on this LED.
*/
- uint16_t target_id;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
+ UINT32_C(0x2)
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * If set to 1, on state is supported on this LED.
+ * If set to 0, on state is not supported on this LED.
*/
- uint64_t resp_addr;
- uint32_t flags;
- /* If set to 1, then PFC is requested to be enabled on PRI 0. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
- UINT32_C(0x1)
- /* If set to 1, then PFC is requested to be enabled on PRI 1. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
- UINT32_C(0x2)
- /* If set to 1, then PFC is requested to be enabled on PRI 2. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
UINT32_C(0x4)
- /* If set to 1, then PFC is requested to be enabled on PRI 3. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
+ /*
+ * If set to 1, blink state is supported on this LED.
+ * If set to 0, blink state is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
UINT32_C(0x8)
- /* If set to 1, then PFC is requested to be enabled on PRI 4. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
+ /*
+ * If set to 1, blink_alt state is supported on this LED.
+ * If set to 0, blink_alt state is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
UINT32_C(0x10)
- /* If set to 1, then PFC is requested to be enabled on PRI 5. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
- UINT32_C(0x20)
- /* If set to 1, then PFC is requested to be enabled on PRI 6. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
- UINT32_C(0x40)
- /* If set to 1, then PFC is requested to be enabled on PRI 7. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
- UINT32_C(0x80)
+ /* The colors supported by LED #0. */
+ uint16_t led0_color_caps;
+ /* reserved. */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
+ UINT32_C(0x1)
/*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure pri2cos mapping on this port.
+ * If set to 1, Amber color is supported on this LED.
+ * If set to 0, Amber color is not supported on this LED.
*/
- uint16_t port_id;
- uint8_t unused_0[2];
-} __attribute__((packed));
-
-/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
-struct hwrm_queue_pfcenable_cfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, Green color is supported on this LED.
+ * If set to 0, Green color is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
+ UINT32_C(0x4)
+ /* An identifier for the LED #1. */
+ uint8_t led1_id;
+ /* The type of LED #1. */
+ uint8_t led1_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
+ HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
+ /*
+ * An identifier for the group of LEDs that LED #1 belongs
+ * to.
+ * If set to 0, then the LED #0 cannot be grouped.
+ * For all other non-zero values of this field, LED #0 is
+ * grouped together with the LEDs with the same group ID
+ * value.
+ */
+ uint8_t led1_group_id;
+ uint8_t unused_1;
+ /* The states supported by LED #1. */
+ uint16_t led1_state_caps;
+ /*
+ * If set to 1, this LED is enabled.
+ * If set to 0, this LED is disabled.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, off state is supported on this LED.
+ * If set to 0, off state is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, on state is supported on this LED.
+ * If set to 0, on state is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * If set to 1, blink state is supported on this LED.
+ * If set to 0, blink state is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
+ UINT32_C(0x8)
+ /*
+ * If set to 1, blink_alt state is supported on this LED.
+ * If set to 0, blink_alt state is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
+ UINT32_C(0x10)
+ /* The colors supported by LED #1. */
+ uint16_t led1_color_caps;
+ /* reserved. */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, Amber color is supported on this LED.
+ * If set to 0, Amber color is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, Green color is supported on this LED.
+ * If set to 0, Green color is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
+ UINT32_C(0x4)
+ /* An identifier for the LED #2. */
+ uint8_t led2_id;
+ /* The type of LED #2. */
+ uint8_t led2_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
+ HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
+ /*
+ * An identifier for the group of LEDs that LED #0 belongs
+ * to.
+ * If set to 0, then the LED #0 cannot be grouped.
+ * For all other non-zero values of this field, LED #0 is
+ * grouped together with the LEDs with the same group ID
+ * value.
+ */
+ uint8_t led2_group_id;
+ uint8_t unused_2;
+ /* The states supported by LED #2. */
+ uint16_t led2_state_caps;
+ /*
+ * If set to 1, this LED is enabled.
+ * If set to 0, this LED is disabled.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, off state is supported on this LED.
+ * If set to 0, off state is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, on state is supported on this LED.
+ * If set to 0, on state is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * If set to 1, blink state is supported on this LED.
+ * If set to 0, blink state is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
+ UINT32_C(0x8)
+ /*
+ * If set to 1, blink_alt state is supported on this LED.
+ * If set to 0, blink_alt state is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
+ UINT32_C(0x10)
+ /* The colors supported by LED #2. */
+ uint16_t led2_color_caps;
+ /* reserved. */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, Amber color is supported on this LED.
+ * If set to 0, Amber color is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, Green color is supported on this LED.
+ * If set to 0, Green color is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
+ UINT32_C(0x4)
+ /* An identifier for the LED #3. */
+ uint8_t led3_id;
+ /* The type of LED #3. */
+ uint8_t led3_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
+ HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
+ /*
+ * An identifier for the group of LEDs that LED #3 belongs
+ * to.
+ * If set to 0, then the LED #0 cannot be grouped.
+ * For all other non-zero values of this field, LED #0 is
+ * grouped together with the LEDs with the same group ID
+ * value.
+ */
+ uint8_t led3_group_id;
+ uint8_t unused_3;
+ /* The states supported by LED #3. */
+ uint16_t led3_state_caps;
+ /*
+ * If set to 1, this LED is enabled.
+ * If set to 0, this LED is disabled.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, off state is supported on this LED.
+ * If set to 0, off state is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, on state is supported on this LED.
+ * If set to 0, on state is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * If set to 1, blink state is supported on this LED.
+ * If set to 0, blink state is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
+ UINT32_C(0x8)
+ /*
+ * If set to 1, blink_alt state is supported on this LED.
+ * If set to 0, blink_alt state is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
+ UINT32_C(0x10)
+ /* The colors supported by LED #3. */
+ uint16_t led3_color_caps;
+ /* reserved. */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, Amber color is supported on this LED.
+ * If set to 0, Amber color is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, Green color is supported on this LED.
+ * If set to 0, Green color is not supported on this LED.
+ */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
+ UINT32_C(0x4)
+ uint8_t unused_4[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/***************************
- * hwrm_queue_pri2cos_qcfg *
- ***************************/
+/***********************
+ * hwrm_queue_qportcfg *
+ ***********************/
-/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
-struct hwrm_queue_pri2cos_qcfg_input {
+/* hwrm_queue_qportcfg_input (size:192b/24B) */
+struct hwrm_queue_qportcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* This enumeration is used for resources that are similar for both
* TX and RX paths of the chip.
*/
- #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
/* tx path */
- #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
/* rx path */
- #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
- HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
+ #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
/*
- * When this bit is set to '0', the query is
- * for VLAN PRI field in tunnel headers.
- * When this bit is set to '1', the query is
- * for VLAN PRI field in inner packet headers.
+ * Port ID of port for which the queue configuration is being
+ * queried. This field is only required when sent by IPC.
*/
- #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
+ uint16_t port_id;
/*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure pri2cos mapping on this port.
+ * Drivers will set this capability when it can use
+ * queue_idx_service_profile to map the queues to application.
*/
- uint8_t port_id;
- uint8_t unused_0[3];
+ uint8_t drv_qmap_cap;
+ /* disabled */
+ #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
+ /* enabled */
+ #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
+ #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
+ HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
+ uint8_t unused_0;
} __attribute__((packed));
-/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
-struct hwrm_queue_pri2cos_qcfg_output {
+/* hwrm_queue_qportcfg_output (size:256b/32B) */
+struct hwrm_queue_qportcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
/* The length of the response data in number of bytes. */
uint16_t resp_len;
/*
- * CoS Queue assigned to priority 0. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
- */
- uint8_t pri0_cos_queue_id;
- /*
- * CoS Queue assigned to priority 1. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
- */
- uint8_t pri1_cos_queue_id;
- /*
- * CoS Queue assigned to priority 2 This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
- */
- uint8_t pri2_cos_queue_id;
- /*
- * CoS Queue assigned to priority 3. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
- */
- uint8_t pri3_cos_queue_id;
- /*
- * CoS Queue assigned to priority 4. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
- */
- uint8_t pri4_cos_queue_id;
- /*
- * CoS Queue assigned to priority 5. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
+ * The maximum number of queues that can be configured on this
+ * port.
+ * Valid values range from 1 through 8.
*/
- uint8_t pri5_cos_queue_id;
+ uint8_t max_configurable_queues;
/*
- * CoS Queue assigned to priority 6. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
+ * The maximum number of lossless queues that can be configured
+ * on this port.
+ * Valid values range from 0 through 8.
*/
- uint8_t pri6_cos_queue_id;
+ uint8_t max_configurable_lossless_queues;
/*
- * CoS Queue assigned to priority 7. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
+ * Bitmask indicating which queues can be configured by the
+ * hwrm_queue_cfg command.
+ *
+ * Each bit represents a specific queue where bit 0 represents
+ * queue 0 and bit 7 represents queue 7.
+ * # A value of 0 indicates that the queue is not configurable
+ * by the hwrm_queue_cfg command.
+ * # A value of 1 indicates that the queue is configurable.
+ * # A hwrm_queue_cfg command shall return error when trying to
+ * configure a queue not configurable.
*/
- uint8_t pri7_cos_queue_id;
+ uint8_t queue_cfg_allowed;
/* Information about queue configuration. */
uint8_t queue_cfg_info;
/*
- * If this flag is set to '1', then the PRI to CoS
- * configuration is asymmetric on TX and RX sides.
- * If this flag is set to '0', then PRI to CoS configuration
- * is symmetric on TX and RX sides.
+ * If this flag is set to '1', then the queues are
+ * configured asymmetrically on TX and RX sides.
+ * If this flag is set to '0', then the queues are
+ * configured symmetrically on TX and RX sides. For
+ * symmetric configuration, the queue configuration
+ * including queue ids and service profiles on the
+ * TX side is the same as the corresponding queue
+ * configuration on the RX side.
*/
- #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
UINT32_C(0x1)
- uint8_t unused_0[6];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/**************************
- * hwrm_queue_pri2cos_cfg *
- **************************/
-
-
-/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
-struct hwrm_queue_pri2cos_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Bitmask indicating which queues can be configured by the
+ * hwrm_queue_pfcenable_cfg command.
+ *
+ * Each bit represents a specific priority where bit 0 represents
+ * priority 0 and bit 7 represents priority 7.
+ * # A value of 0 indicates that the priority is not configurable by
+ * the hwrm_queue_pfcenable_cfg command.
+ * # A value of 1 indicates that the priority is configurable.
+ * # A hwrm_queue_pfcenable_cfg command shall return error when
+ * trying to configure a priority that is not configurable.
*/
- uint64_t resp_addr;
- uint32_t flags;
+ uint8_t queue_pfcenable_cfg_allowed;
/*
- * Enumeration denoting the RX, TX, or both directions applicable to the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
+ * Bitmask indicating which queues can be configured by the
+ * hwrm_queue_pri2cos_cfg command.
+ *
+ * Each bit represents a specific queue where bit 0 represents
+ * queue 0 and bit 7 represents queue 7.
+ * # A value of 0 indicates that the queue is not configurable
+ * by the hwrm_queue_pri2cos_cfg command.
+ * # A value of 1 indicates that the queue is configurable.
+ * # A hwrm_queue_pri2cos_cfg command shall return error when
+ * trying to configure a queue that is not configurable.
*/
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
- /* tx path */
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* rx path */
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- /* Bi-directional (Symmetrically applicable to TX and RX paths) */
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
- HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
+ uint8_t queue_pri2cos_cfg_allowed;
/*
- * When this bit is set to '0', the mapping is requested
- * for VLAN PRI field in tunnel headers.
- * When this bit is set to '1', the mapping is requested
- * for VLAN PRI field in inner packet headers.
+ * Bitmask indicating which queues can be configured by the
+ * hwrm_queue_pri2cos_cfg command.
+ *
+ * Each bit represents a specific queue where bit 0 represents
+ * queue 0 and bit 7 represents queue 7.
+ * # A value of 0 indicates that the queue is not configurable
+ * by the hwrm_queue_pri2cos_cfg command.
+ * # A value of 1 indicates that the queue is configurable.
+ * # A hwrm_queue_pri2cos_cfg command shall return error when
+ * trying to configure a queue not configurable.
*/
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
- uint32_t enables;
+ uint8_t queue_cos2bw_cfg_allowed;
/*
- * This bit must be '1' for the pri0_cos_queue_id field to be
- * configured.
+ * ID of CoS Queue 0.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # Any driver or software should not make any assumptions about
+ * queue IDs.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
*/
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
+ uint8_t queue_id0;
+ /* This value is applicable to CoS queues only. */
+ uint8_t queue_id0_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless (legacy) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
UINT32_C(0x1)
- /*
- * This bit must be '1' for the pri1_cos_queue_id field to be
- * configured.
- */
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
+ /* Lossless RoCE */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
UINT32_C(0x2)
+ /* Lossless NIC */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
/*
- * This bit must be '1' for the pri2_cos_queue_id field to be
- * configured.
- */
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
- UINT32_C(0x4)
- /*
- * This bit must be '1' for the pri3_cos_queue_id field to be
- * configured.
- */
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
- UINT32_C(0x8)
- /*
- * This bit must be '1' for the pri4_cos_queue_id field to be
- * configured.
- */
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
- UINT32_C(0x10)
- /*
- * This bit must be '1' for the pri5_cos_queue_id field to be
- * configured.
- */
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
- UINT32_C(0x20)
- /*
- * This bit must be '1' for the pri6_cos_queue_id field to be
- * configured.
- */
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
- UINT32_C(0x40)
- /*
- * This bit must be '1' for the pri7_cos_queue_id field to be
- * configured.
+ * ID of CoS Queue 1.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # Any driver or software should not make any assumptions about
+ * queue IDs.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
*/
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
- UINT32_C(0x80)
+ uint8_t queue_id1;
+ /* This value is applicable to CoS queues only. */
+ uint8_t queue_id1_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless (legacy) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
/*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure pri2cos mapping on this port.
+ * ID of CoS Queue 2.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # Any driver or software should not make any assumptions about
+ * queue IDs.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
*/
- uint8_t port_id;
+ uint8_t queue_id2;
+ /* This value is applicable to CoS queues only. */
+ uint8_t queue_id2_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless (legacy) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
/*
- * CoS Queue assigned to priority 0. This value can only
- * be changed before traffic has started.
+ * ID of CoS Queue 3.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # Any driver or software should not make any assumptions about
+ * queue IDs.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
*/
- uint8_t pri0_cos_queue_id;
+ uint8_t queue_id3;
+ /* This value is applicable to CoS queues only. */
+ uint8_t queue_id3_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless (legacy) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
/*
- * CoS Queue assigned to priority 1. This value can only
- * be changed before traffic has started.
+ * ID of CoS Queue 4.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # Any driver or software should not make any assumptions about
+ * queue IDs.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
*/
- uint8_t pri1_cos_queue_id;
+ uint8_t queue_id4;
+ /* This value is applicable to CoS queues only. */
+ uint8_t queue_id4_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless (legacy) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
/*
- * CoS Queue assigned to priority 2 This value can only
- * be changed before traffic has started.
+ * ID of CoS Queue 5.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # Any driver or software should not make any assumptions about
+ * queue IDs.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
*/
- uint8_t pri2_cos_queue_id;
+ uint8_t queue_id5;
+ /* This value is applicable to CoS queues only. */
+ uint8_t queue_id5_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless (legacy) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
/*
- * CoS Queue assigned to priority 3. This value can only
- * be changed before traffic has started.
+ * ID of CoS Queue 6.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # Any driver or software should not make any assumptions about
+ * queue IDs.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
*/
- uint8_t pri3_cos_queue_id;
+ uint8_t queue_id6;
+ /* This value is applicable to CoS queues only. */
+ uint8_t queue_id6_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless (legacy) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
/*
- * CoS Queue assigned to priority 4. This value can only
- * be changed before traffic has started.
+ * ID of CoS Queue 7.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # Any driver or software should not make any assumptions about
+ * queue IDs.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
*/
- uint8_t pri4_cos_queue_id;
+ uint8_t queue_id7;
+ /* This value is applicable to CoS queues only. */
+ uint8_t queue_id7_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless (legacy) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
/*
- * CoS Queue assigned to priority 5. This value can only
- * be changed before traffic has started.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t pri5_cos_queue_id;
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************
+ * hwrm_queue_qcfg *
+ *******************/
+
+
+/* hwrm_queue_qcfg_input (size:192b/24B) */
+struct hwrm_queue_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * CoS Queue assigned to priority 6. This value can only
- * be changed before traffic has started.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint8_t pri6_cos_queue_id;
+ uint16_t cmpl_ring;
/*
- * CoS Queue assigned to priority 7. This value can only
- * be changed before traffic has started.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t pri7_cos_queue_id;
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
+ /* Queue ID of the queue. */
+ uint32_t queue_id;
+} __attribute__((packed));
+
+/* hwrm_queue_qcfg_output (size:128b/16B) */
+struct hwrm_queue_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * This value is a the estimate packet length used in the
+ * TX arbiter.
+ */
+ uint32_t queue_len;
+ /* This value is applicable to CoS queues only. */
+ uint8_t service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
+ /* Lossless */
+ #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
+ #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
+ /* Information about queue configuration. */
+ uint8_t queue_cfg_info;
+ /*
+ * If this flag is set to '1', then the queue is
+ * configured asymmetrically on TX and RX sides.
+ * If this flag is set to '0', then this queue is
+ * configured symmetrically on TX and RX sides.
+ */
+ #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
+ UINT32_C(0x1)
+ uint8_t unused_0;
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/******************
+ * hwrm_queue_cfg *
+ ******************/
+
+
+/* hwrm_queue_cfg_input (size:320b/40B) */
+struct hwrm_queue_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * Enumeration denoting the RX, TX, or both directions applicable to the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
+ #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
+ /* tx path */
+ #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ /* Bi-directional (Symmetrically applicable to TX and RX paths) */
+ #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
+ #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the dflt_len field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the service_profile field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
+ /* Queue ID of queue that is to be configured by this function. */
+ uint32_t queue_id;
+ /*
+ * This value is a the estimate packet length used in the
+ * TX arbiter.
+ * Set to 0xFF... (All Fs) to not adjust this value.
+ */
+ uint32_t dflt_len;
+ /* This value is applicable to CoS queues only. */
+ uint8_t service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
+ /* Lossless */
+ #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
+ #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
-struct hwrm_queue_pri2cos_cfg_output {
+/* hwrm_queue_cfg_output (size:128b/16B) */
+struct hwrm_queue_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/**************************
- * hwrm_queue_cos2bw_qcfg *
- **************************/
+/*****************************
+ * hwrm_queue_pfcenable_qcfg *
+ *****************************/
-/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
-struct hwrm_queue_cos2bw_qcfg_input {
+/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
+struct hwrm_queue_pfcenable_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
/*
* Port ID of port for which the table is being configured.
* The HWRM needs to check whether this function is allowed
- * to configure TC BW assignment on this port.
+ * to configure pri2cos mapping on this port.
*/
uint16_t port_id;
uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
-struct hwrm_queue_cos2bw_qcfg_output {
+/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
+struct hwrm_queue_pfcenable_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* ID of CoS Queue 0. */
- uint8_t queue_id0;
- uint8_t unused_0;
- uint16_t unused_1;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id0_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id0_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id0_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id0_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id0_bw_weight;
- /* ID of CoS Queue 1. */
- uint8_t queue_id1;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id1_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id1_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id1_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id1_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id1_bw_weight;
- /* ID of CoS Queue 2. */
- uint8_t queue_id2;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id2_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id2_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id2_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id2_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id2_bw_weight;
- /* ID of CoS Queue 3. */
- uint8_t queue_id3;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id3_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id3_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id3_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id3_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id3_bw_weight;
- /* ID of CoS Queue 4. */
- uint8_t queue_id4;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id4_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id4_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id4_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id4_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id4_bw_weight;
- /* ID of CoS Queue 5. */
- uint8_t queue_id5;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id5_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id5_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id5_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id5_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id5_bw_weight;
- /* ID of CoS Queue 6. */
- uint8_t queue_id6;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id6_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id6_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id6_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id6_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id6_bw_weight;
- /* ID of CoS Queue 7. */
- uint8_t queue_id7;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id7_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id7_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id7_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id7_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id7_bw_weight;
- uint8_t unused_2[4];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/*************************
- * hwrm_queue_cos2bw_cfg *
- *************************/
-
-
-/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
-struct hwrm_queue_cos2bw_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- uint32_t flags;
- uint32_t enables;
- /*
- * If this bit is set to 1, then all queue_id0 related
- * parameters in this command are valid.
- */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
- UINT32_C(0x1)
- /*
- * If this bit is set to 1, then all queue_id1 related
- * parameters in this command are valid.
- */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
- UINT32_C(0x2)
- /*
- * If this bit is set to 1, then all queue_id2 related
- * parameters in this command are valid.
- */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
- UINT32_C(0x4)
- /*
- * If this bit is set to 1, then all queue_id3 related
- * parameters in this command are valid.
- */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
- UINT32_C(0x8)
- /*
- * If this bit is set to 1, then all queue_id4 related
- * parameters in this command are valid.
- */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
- UINT32_C(0x10)
- /*
- * If this bit is set to 1, then all queue_id5 related
- * parameters in this command are valid.
- */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
- UINT32_C(0x20)
- /*
- * If this bit is set to 1, then all queue_id6 related
- * parameters in this command are valid.
- */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
- UINT32_C(0x40)
- /*
- * If this bit is set to 1, then all queue_id7 related
- * parameters in this command are valid.
- */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
- UINT32_C(0x80)
- /*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure TC BW assignment on this port.
- */
- uint16_t port_id;
- /* ID of CoS Queue 0. */
- uint8_t queue_id0;
- uint8_t unused_0;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id0_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id0_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id0_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id0_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id0_bw_weight;
- /* ID of CoS Queue 1. */
- uint8_t queue_id1;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id1_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id1_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id1_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id1_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id1_bw_weight;
- /* ID of CoS Queue 2. */
- uint8_t queue_id2;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id2_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id2_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id2_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id2_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id2_bw_weight;
- /* ID of CoS Queue 3. */
- uint8_t queue_id3;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id3_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id3_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id3_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id3_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id3_bw_weight;
- /* ID of CoS Queue 4. */
- uint8_t queue_id4;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id4_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id4_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id4_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id4_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id4_bw_weight;
- /* ID of CoS Queue 5. */
- uint8_t queue_id5;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id5_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id5_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id5_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id5_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id5_bw_weight;
- /* ID of CoS Queue 6. */
- uint8_t queue_id6;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id6_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id6_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id6_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id6_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id6_bw_weight;
- /* ID of CoS Queue 7. */
- uint8_t queue_id7;
- /*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id7_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
- /*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
- */
- uint32_t queue_id7_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id7_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
- /*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
- */
- uint8_t queue_id7_pri_lvl;
- /*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
- */
- uint8_t queue_id7_bw_weight;
- uint8_t unused_1[5];
-} __attribute__((packed));
-
-/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
-struct hwrm_queue_cos2bw_cfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/*************************
- * hwrm_queue_dscp_qcaps *
- *************************/
-
-
-/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
-struct hwrm_queue_dscp_qcaps_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- /*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure pri2cos mapping on this port.
- */
- uint8_t port_id;
- uint8_t unused_0[7];
-} __attribute__((packed));
-
-/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
-struct hwrm_queue_dscp_qcaps_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* The number of bits provided by the hardware for the DSCP value. */
- uint8_t num_dscp_bits;
- uint8_t unused_0;
- /* Max number of DSCP-MASK-PRI entries supported. */
- uint16_t max_entries;
- uint8_t unused_1[3];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/****************************
- * hwrm_queue_dscp2pri_qcfg *
- ****************************/
-
-
-/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
-struct hwrm_queue_dscp2pri_qcfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- /*
- * This is the host address where the 24-bits DSCP-MASK-PRI
- * tuple(s) will be copied to.
- */
- uint64_t dest_data_addr;
- /*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure pri2cos mapping on this port.
- */
- uint8_t port_id;
- uint8_t unused_0;
- /* Size of the buffer pointed to by dest_data_addr. */
- uint16_t dest_data_buffer_size;
- uint8_t unused_1[4];
-} __attribute__((packed));
-
-/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
-struct hwrm_queue_dscp2pri_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /*
- * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
- * by the dest_data_addr.
- */
- uint16_t entry_cnt;
- /*
- * This is the default PRI which un-initialized DSCP values are
- * mapped to.
- */
- uint8_t default_pri;
- uint8_t unused_0[4];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/***************************
- * hwrm_queue_dscp2pri_cfg *
- ***************************/
-
-
-/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
-struct hwrm_queue_dscp2pri_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- /*
- * This is the host address where the 24-bits DSCP-MASK-PRI tuple
- * will be copied from.
- */
- uint64_t src_data_addr;
- uint32_t flags;
- /* use_hw_default_pri is 1 b */
- #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
- UINT32_C(0x1)
- uint32_t enables;
- /*
- * This bit must be '1' for the default_pri field to be
- * configured.
- */
- #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
- UINT32_C(0x1)
- /*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure pri2cos mapping on this port.
- */
- uint8_t port_id;
- /*
- * This is the default PRI which un-initialized DSCP values will be
- * mapped to.
- */
- uint8_t default_pri;
- /*
- * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
- * to by src_data_addr.
- */
- uint16_t entry_cnt;
- uint8_t unused_0[4];
-} __attribute__((packed));
-
-/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
-struct hwrm_queue_dscp2pri_cfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/*******************
- * hwrm_vnic_alloc *
- *******************/
-
-
-/* hwrm_vnic_alloc_input (size:192b/24B) */
-struct hwrm_vnic_alloc_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- uint32_t flags;
- /*
- * When this bit is '1', this VNIC is requested to
- * be the default VNIC for this function.
- */
- #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
- uint8_t unused_0[4];
-} __attribute__((packed));
-
-/* hwrm_vnic_alloc_output (size:128b/16B) */
-struct hwrm_vnic_alloc_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* Logical vnic ID */
- uint32_t vnic_id;
- uint8_t unused_0[3];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/******************
- * hwrm_vnic_free *
- ******************/
-
-
-/* hwrm_vnic_free_input (size:192b/24B) */
-struct hwrm_vnic_free_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- /* Logical vnic ID */
- uint32_t vnic_id;
- uint8_t unused_0[4];
-} __attribute__((packed));
-
-/* hwrm_vnic_free_output (size:128b/16B) */
-struct hwrm_vnic_free_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/*****************
- * hwrm_vnic_cfg *
- *****************/
-
-
-/* hwrm_vnic_cfg_input (size:320b/40B) */
-struct hwrm_vnic_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
uint32_t flags;
- /*
- * When this bit is '1', the VNIC is requested to
- * be the default VNIC for the function.
- */
- #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
- UINT32_C(0x1)
- /*
- * When this bit is '1', the VNIC is being configured to
- * strip VLAN in the RX path.
- * If set to '0', then VLAN stripping is disabled on
- * this VNIC.
- */
- #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
- UINT32_C(0x2)
- /*
- * When this bit is '1', the VNIC is being configured to
- * buffer receive packets in the hardware until the host
- * posts new receive buffers.
- * If set to '0', then bd_stall is being configured to be
- * disabled on this VNIC.
- */
- #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
- UINT32_C(0x4)
- /*
- * When this bit is '1', the VNIC is being configured to
- * receive both RoCE and non-RoCE traffic.
- * If set to '0', then this VNIC is not configured to be
- * operating in dual VNIC mode.
- */
- #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
- UINT32_C(0x8)
- /*
- * When this flag is set to '1', the VNIC is requested to
- * be configured to receive only RoCE traffic.
- * If this flag is set to '0', then this flag shall be
- * ignored by the HWRM.
- * If roce_dual_vnic_mode flag is set to '1'
- * or roce_mirroring_capable_vnic_mode flag to 1,
- * then the HWRM client shall not set this flag to '1'.
- */
- #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
- UINT32_C(0x10)
- /*
- * When a VNIC uses one destination ring group for certain
- * application (e.g. Receive Flow Steering) where
- * exact match is used to direct packets to a VNIC with one
- * destination ring group only, there is no need to configure
- * RSS indirection table for that VNIC as only one destination
- * ring group is used.
- *
- * This flag is used to enable a mode where
- * RSS is enabled in the VNIC using a RSS context
- * for computing RSS hash but the RSS indirection table is
- * not configured using hwrm_vnic_rss_cfg.
- *
- * If this mode is enabled, then the driver should not program
- * RSS indirection table for the RSS context that is used for
- * computing RSS hash only.
- */
- #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
- UINT32_C(0x20)
- /*
- * When this bit is '1', the VNIC is being configured to
- * receive both RoCE and non-RoCE traffic, but forward only the
- * RoCE traffic further. Also, RoCE traffic can be mirrored to
- * L2 driver.
- */
- #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
- UINT32_C(0x40)
- uint32_t enables;
- /*
- * This bit must be '1' for the dflt_ring_grp field to be
- * configured.
- */
- #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
+ /* If set to 1, then PFC is enabled on PRI 0. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
UINT32_C(0x1)
- /*
- * This bit must be '1' for the rss_rule field to be
- * configured.
- */
- #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
+ /* If set to 1, then PFC is enabled on PRI 1. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
UINT32_C(0x2)
- /*
- * This bit must be '1' for the cos_rule field to be
- * configured.
- */
- #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
- UINT32_C(0x4)
- /*
- * This bit must be '1' for the lb_rule field to be
- * configured.
- */
- #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
+ /* If set to 1, then PFC is enabled on PRI 2. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
+ UINT32_C(0x4)
+ /* If set to 1, then PFC is enabled on PRI 3. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
UINT32_C(0x8)
- /*
- * This bit must be '1' for the mru field to be
- * configured.
- */
- #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
+ /* If set to 1, then PFC is enabled on PRI 4. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
UINT32_C(0x10)
- /*
- * This bit must be '1' for the default_rx_ring_id field to be
- * configured.
- */
- #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
+ /* If set to 1, then PFC is enabled on PRI 5. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
UINT32_C(0x20)
- /*
- * This bit must be '1' for the default_cmpl_ring_id field to be
- * configured.
- */
- #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
+ /* If set to 1, then PFC is enabled on PRI 6. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
UINT32_C(0x40)
- /* Logical vnic ID */
- uint16_t vnic_id;
- /*
- * Default Completion ring for the VNIC. This ring will
- * be chosen if packet does not match any RSS rules and if
- * there is no COS rule.
- */
- uint16_t dflt_ring_grp;
+ /* If set to 1, then PFC is enabled on PRI 7. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
+ UINT32_C(0x80)
+ uint8_t unused_0[3];
/*
- * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
- * there is no RSS rule.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint16_t rss_rule;
+ uint8_t valid;
+} __attribute__((packed));
+
+/****************************
+ * hwrm_queue_pfcenable_cfg *
+ ****************************/
+
+
+/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
+struct hwrm_queue_pfcenable_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
- * there is no COS rule.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t cos_rule;
+ uint16_t cmpl_ring;
/*
- * RSS ID for load balancing rule/table structure.
- * 0xFF... (All Fs) if there is no LB rule.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint16_t lb_rule;
+ uint16_t seq_id;
/*
- * The maximum receive unit of the vnic.
- * Each vnic is associated with a function.
- * The vnic mru value overwrites the mru setting of the
- * associated function.
- * The HWRM shall make sure that vnic mru does not exceed
- * the mru of the port the function is associated with.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint16_t mru;
+ uint16_t target_id;
/*
- * Default Rx ring for the VNIC. This ring will
- * be chosen if packet does not match any RSS rules.
- * The aggregation ring associated with the Rx ring is
- * implied based on the Rx ring specified when the
- * aggregation ring was allocated.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t default_rx_ring_id;
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* If set to 1, then PFC is requested to be enabled on PRI 0. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
+ UINT32_C(0x1)
+ /* If set to 1, then PFC is requested to be enabled on PRI 1. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
+ UINT32_C(0x2)
+ /* If set to 1, then PFC is requested to be enabled on PRI 2. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
+ UINT32_C(0x4)
+ /* If set to 1, then PFC is requested to be enabled on PRI 3. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
+ UINT32_C(0x8)
+ /* If set to 1, then PFC is requested to be enabled on PRI 4. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
+ UINT32_C(0x10)
+ /* If set to 1, then PFC is requested to be enabled on PRI 5. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
+ UINT32_C(0x20)
+ /* If set to 1, then PFC is requested to be enabled on PRI 6. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
+ UINT32_C(0x40)
+ /* If set to 1, then PFC is requested to be enabled on PRI 7. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
+ UINT32_C(0x80)
/*
- * Default completion ring for the VNIC. This ring will
- * be chosen if packet does not match any RSS rules.
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure pri2cos mapping on this port.
*/
- uint16_t default_cmpl_ring_id;
+ uint16_t port_id;
+ uint8_t unused_0[2];
} __attribute__((packed));
-/* hwrm_vnic_cfg_output (size:128b/16B) */
-struct hwrm_vnic_cfg_output {
+/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
+struct hwrm_queue_pfcenable_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/******************
- * hwrm_vnic_qcfg *
- ******************/
+/***************************
+ * hwrm_queue_pri2cos_qcfg *
+ ***************************/
-/* hwrm_vnic_qcfg_input (size:256b/32B) */
-struct hwrm_vnic_qcfg_input {
+/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
+struct hwrm_queue_pri2cos_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
+ uint32_t flags;
/*
- * This bit must be '1' for the vf_id_valid field to be
- * configured.
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
*/
- #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
- /* Logical vnic ID */
- uint32_t vnic_id;
- /* ID of Virtual Function whose VNIC resource is being queried. */
- uint16_t vf_id;
- uint8_t unused_0[6];
+ #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
+ /*
+ * When this bit is set to '0', the query is
+ * for VLAN PRI field in tunnel headers.
+ * When this bit is set to '1', the query is
+ * for VLAN PRI field in inner packet headers.
+ */
+ #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure pri2cos mapping on this port.
+ */
+ uint8_t port_id;
+ uint8_t unused_0[3];
} __attribute__((packed));
-/* hwrm_vnic_qcfg_output (size:256b/32B) */
-struct hwrm_vnic_qcfg_output {
+/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
+struct hwrm_queue_pri2cos_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Default Completion ring for the VNIC. */
- uint16_t dflt_ring_grp;
- /*
- * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
- * there is no RSS rule.
- */
- uint16_t rss_rule;
/*
- * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
- * there is no COS rule.
+ * CoS Queue assigned to priority 0. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
*/
- uint16_t cos_rule;
+ uint8_t pri0_cos_queue_id;
/*
- * RSS ID for load balancing rule/table structure.
- * 0xFF... (All Fs) if there is no LB rule.
+ * CoS Queue assigned to priority 1. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
*/
- uint16_t lb_rule;
- /* The maximum receive unit of the vnic. */
- uint16_t mru;
- uint8_t unused_0[2];
- uint32_t flags;
+ uint8_t pri1_cos_queue_id;
/*
- * When this bit is '1', the VNIC is the default VNIC for
- * the function.
+ * CoS Queue assigned to priority 2 This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
*/
- #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
- UINT32_C(0x1)
+ uint8_t pri2_cos_queue_id;
/*
- * When this bit is '1', the VNIC is configured to
- * strip VLAN in the RX path.
- * If set to '0', then VLAN stripping is disabled on
- * this VNIC.
+ * CoS Queue assigned to priority 3. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
*/
- #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
- UINT32_C(0x2)
+ uint8_t pri3_cos_queue_id;
/*
- * When this bit is '1', the VNIC is configured to
- * buffer receive packets in the hardware until the host
- * posts new receive buffers.
- * If set to '0', then bd_stall is disabled on
- * this VNIC.
+ * CoS Queue assigned to priority 4. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
*/
- #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
- UINT32_C(0x4)
+ uint8_t pri4_cos_queue_id;
/*
- * When this bit is '1', the VNIC is configured to
- * receive both RoCE and non-RoCE traffic.
- * If set to '0', then this VNIC is not configured to
- * operate in dual VNIC mode.
+ * CoS Queue assigned to priority 5. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
*/
- #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
- UINT32_C(0x8)
- /*
- * When this flag is set to '1', the VNIC is configured to
- * receive only RoCE traffic.
- * When this flag is set to '0', the VNIC is not configured
- * to receive only RoCE traffic.
- * If roce_dual_vnic_mode flag and this flag both are set
- * to '1', then it is an invalid configuration of the
- * VNIC. The HWRM should not allow that type of
- * mis-configuration by HWRM clients.
+ uint8_t pri5_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 6. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
*/
- #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
- UINT32_C(0x10)
+ uint8_t pri6_cos_queue_id;
/*
- * When a VNIC uses one destination ring group for certain
- * application (e.g. Receive Flow Steering) where
- * exact match is used to direct packets to a VNIC with one
- * destination ring group only, there is no need to configure
- * RSS indirection table for that VNIC as only one destination
- * ring group is used.
- *
- * When this bit is set to '1', then the VNIC is enabled in a
- * mode where RSS is enabled in the VNIC using a RSS context
- * for computing RSS hash but the RSS indirection table is
- * not configured.
+ * CoS Queue assigned to priority 7. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
*/
- #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
- UINT32_C(0x20)
+ uint8_t pri7_cos_queue_id;
+ /* Information about queue configuration. */
+ uint8_t queue_cfg_info;
/*
- * When this bit is '1', the VNIC is configured to
- * receive both RoCE and non-RoCE traffic, but forward only
- * RoCE traffic further. Also RoCE traffic can be mirrored to
- * L2 driver.
+ * If this flag is set to '1', then the PRI to CoS
+ * configuration is asymmetric on TX and RX sides.
+ * If this flag is set to '0', then PRI to CoS configuration
+ * is symmetric on TX and RX sides.
*/
- #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
- UINT32_C(0x40)
- uint8_t unused_1[7];
+ #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
+ UINT32_C(0x1)
+ uint8_t unused_0[6];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/*******************
- * hwrm_vnic_qcaps *
- *******************/
+/**************************
+ * hwrm_queue_pri2cos_cfg *
+ **************************/
-/* hwrm_vnic_qcaps_input (size:192b/24B) */
-struct hwrm_vnic_qcaps_input {
+/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
+struct hwrm_queue_pri2cos_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
- uint8_t unused_0[4];
-} __attribute__((packed));
-
-/* hwrm_vnic_qcaps_output (size:192b/24B) */
-struct hwrm_vnic_qcaps_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* The maximum receive unit that is settable on a vnic. */
- uint16_t mru;
- uint8_t unused_0[2];
uint32_t flags;
- /* Unused. */
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
+ /*
+ * Enumeration denoting the RX, TX, or both directions applicable to the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
+ /* tx path */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ /* Bi-directional (Symmetrically applicable to TX and RX paths) */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
+ /*
+ * When this bit is set to '0', the mapping is requested
+ * for VLAN PRI field in tunnel headers.
+ * When this bit is set to '1', the mapping is requested
+ * for VLAN PRI field in inner packet headers.
+ */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the pri0_cos_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
UINT32_C(0x1)
/*
- * When this bit is '1', the capability of stripping VLAN in
- * the RX path is supported on VNIC(s).
- * If set to '0', then VLAN stripping capability is
- * not supported on VNIC(s).
+ * This bit must be '1' for the pri1_cos_queue_id field to be
+ * configured.
*/
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
UINT32_C(0x2)
/*
- * When this bit is '1', the capability to buffer receive
- * packets in the hardware until the host posts new receive buffers
- * is supported on VNIC(s).
- * If set to '0', then bd_stall capability is not supported
- * on VNIC(s).
+ * This bit must be '1' for the pri2_cos_queue_id field to be
+ * configured.
*/
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
UINT32_C(0x4)
/*
- * When this bit is '1', the capability to
- * receive both RoCE and non-RoCE traffic on VNIC(s) is
- * supported.
- * If set to '0', then the capability to receive
- * both RoCE and non-RoCE traffic on VNIC(s) is
- * not supported.
+ * This bit must be '1' for the pri3_cos_queue_id field to be
+ * configured.
*/
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
UINT32_C(0x8)
/*
- * When this bit is set to '1', the capability to configure
- * a VNIC to receive only RoCE traffic is supported.
- * When this flag is set to '0', the VNIC capability to
- * configure to receive only RoCE traffic is not supported.
+ * This bit must be '1' for the pri4_cos_queue_id field to be
+ * configured.
*/
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
UINT32_C(0x10)
/*
- * When this bit is set to '1', then the capability to enable
- * a VNIC in a mode where RSS context without configuring
- * RSS indirection table is supported (for RSS hash computation).
- * When this bit is set to '0', then a VNIC can not be configured
- * with a mode to enable RSS context without configuring RSS
- * indirection table.
+ * This bit must be '1' for the pri5_cos_queue_id field to be
+ * configured.
*/
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
UINT32_C(0x20)
/*
- * When this bit is '1', the capability to
- * mirror the the RoCE traffic is supported.
- * If set to '0', then the capability to mirror the
- * RoCE traffic is not supported.
+ * This bit must be '1' for the pri6_cos_queue_id field to be
+ * configured.
*/
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
UINT32_C(0x40)
/*
- * When this bit is '1', the outermost RSS hashing capability
- * is supported. If set to '0', then the outermost RSS hashing
- * capability is not supported.
+ * This bit must be '1' for the pri7_cos_queue_id field to be
+ * configured.
*/
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
UINT32_C(0x80)
- uint8_t unused_1[7];
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure pri2cos mapping on this port.
+ */
+ uint8_t port_id;
+ /*
+ * CoS Queue assigned to priority 0. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri0_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 1. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri1_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 2 This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri2_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 3. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri3_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 4. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri4_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 5. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri5_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 6. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri6_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 7. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri7_cos_queue_id;
+ uint8_t unused_0[7];
+} __attribute__((packed));
+
+/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
+struct hwrm_queue_pri2cos_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/*********************
- * hwrm_vnic_tpa_cfg *
- *********************/
+/**************************
+ * hwrm_queue_cos2bw_qcfg *
+ **************************/
-/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
-struct hwrm_vnic_tpa_cfg_input {
+/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
+struct hwrm_queue_cos2bw_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
*/
uint16_t target_id;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure TC BW assignment on this port.
+ */
+ uint16_t port_id;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
+struct hwrm_queue_cos2bw_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* ID of CoS Queue 0. */
+ uint8_t queue_id0;
+ uint8_t unused_0;
+ uint16_t unused_1;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- uint64_t resp_addr;
- uint32_t flags;
+ uint32_t queue_id0_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * When this bit is '1', the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) of
- * non-tunneled TCP packets.
+ * Maximum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
+ uint32_t queue_id0_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id0_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
UINT32_C(0x1)
- /*
- * When this bit is '1', the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) of
- * tunneled TCP packets.
- */
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * When this bit is '1', the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) according
- * to Windows Receive Segment Coalescing (RSC) rules.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
- UINT32_C(0x4)
+ uint8_t queue_id0_pri_lvl;
/*
- * When this bit is '1', the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) according
- * to Linux Generic Receive Offload (GRO) rules.
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
- UINT32_C(0x8)
+ uint8_t queue_id0_bw_weight;
+ /* ID of CoS Queue 1. */
+ uint8_t queue_id1;
/*
- * When this bit is '1', the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) for TCP
- * packets with IP ECN set to non-zero.
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
- UINT32_C(0x10)
+ uint32_t queue_id1_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * When this bit is '1', the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) for
- * GRE tunneled TCP packets only if all packets have the
- * same GRE sequence.
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
- UINT32_C(0x20)
+ uint32_t queue_id1_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id1_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * When this bit is '1' and the GRO mode is enabled,
- * the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) for
- * TCP/IPv4 packets with consecutively increasing IPIDs.
- * In other words, the last packet that is being
- * aggregated to an already existing aggregation context
- * shall have IPID 1 more than the IPID of the last packet
- * that was aggregated in that aggregation context.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
- UINT32_C(0x40)
+ uint8_t queue_id1_pri_lvl;
/*
- * When this bit is '1' and the GRO mode is enabled,
- * the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) for
- * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
- * value.
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
- UINT32_C(0x80)
- uint32_t enables;
+ uint8_t queue_id1_bw_weight;
+ /* ID of CoS Queue 2. */
+ uint8_t queue_id2;
/*
- * This bit must be '1' for the max_agg_segs field to be
- * configured.
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
+ uint32_t queue_id2_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * This bit must be '1' for the max_aggs field to be
- * configured.
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
+ uint32_t queue_id2_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id2_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * This bit must be '1' for the max_agg_timer field to be
- * configured.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
+ uint8_t queue_id2_pri_lvl;
/*
- * This bit must be '1' for the min_agg_len field to be
- * configured.
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
- /* Logical vnic ID */
- uint16_t vnic_id;
+ uint8_t queue_id2_bw_weight;
+ /* ID of CoS Queue 3. */
+ uint8_t queue_id3;
/*
- * This is the maximum number of TCP segments that can
- * be aggregated (unit is Log2). Max value is 31.
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- uint16_t max_agg_segs;
- /* 1 segment */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
- /* 2 segments */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
- /* 4 segments */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
- /* 8 segments */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
- /* Any segment size larger than this is not valid */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
- HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
+ uint32_t queue_id3_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * This is the maximum number of aggregations this VNIC is
- * allowed (unit is Log2). Max value is 7
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- uint16_t max_aggs;
- /* 1 aggregation */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
- /* 2 aggregations */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
- /* 4 aggregations */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
- /* 8 aggregations */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
- /* 16 aggregations */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
- /* Any aggregation size larger than this is not valid */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
- HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
- uint8_t unused_0[2];
+ uint32_t queue_id3_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id3_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * This is the maximum amount of time allowed for
- * an aggregation context to complete after it was initiated.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- uint32_t max_agg_timer;
+ uint8_t queue_id3_pri_lvl;
/*
- * This is the minimum amount of payload length required to
- * start an aggregation context.
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- uint32_t min_agg_len;
-} __attribute__((packed));
-
-/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
-struct hwrm_vnic_tpa_cfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
+ uint8_t queue_id3_bw_weight;
+ /* ID of CoS Queue 4. */
+ uint8_t queue_id4;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/**********************
- * hwrm_vnic_tpa_qcfg *
- **********************/
-
-
-/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
-struct hwrm_vnic_tpa_qcfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint32_t queue_id4_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- uint16_t cmpl_ring;
+ uint32_t queue_id4_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id4_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- uint16_t seq_id;
+ uint8_t queue_id4_pri_lvl;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- uint16_t target_id;
+ uint8_t queue_id4_bw_weight;
+ /* ID of CoS Queue 5. */
+ uint8_t queue_id5;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- uint64_t resp_addr;
- /* Logical vnic ID */
- uint16_t vnic_id;
- uint8_t unused_0[6];
-} __attribute__((packed));
-
-/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
-struct hwrm_vnic_tpa_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint32_t flags;
+ uint32_t queue_id5_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * When this bit is '1', the VNIC is configured to
- * perform transparent packet aggregation (TPA) of
- * non-tunneled TCP packets.
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA \
+ uint32_t queue_id5_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id5_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
UINT32_C(0x1)
- /*
- * When this bit is '1', the VNIC is configured to
- * perform transparent packet aggregation (TPA) of
- * tunneled TCP packets.
- */
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA \
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * When this bit is '1', the VNIC is configured to
- * perform transparent packet aggregation (TPA) according
- * to Windows Receive Segment Coalescing (RSC) rules.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE \
- UINT32_C(0x4)
+ uint8_t queue_id5_pri_lvl;
/*
- * When this bit is '1', the VNIC is configured to
- * perform transparent packet aggregation (TPA) according
- * to Linux Generic Receive Offload (GRO) rules.
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO \
- UINT32_C(0x8)
+ uint8_t queue_id5_bw_weight;
+ /* ID of CoS Queue 6. */
+ uint8_t queue_id6;
/*
- * When this bit is '1', the VNIC is configured to
- * perform transparent packet aggregation (TPA) for TCP
- * packets with IP ECN set to non-zero.
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN \
- UINT32_C(0x10)
+ uint32_t queue_id6_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * When this bit is '1', the VNIC is configured to
- * perform transparent packet aggregation (TPA) for
- * GRE tunneled TCP packets only if all packets have the
- * same GRE sequence.
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
- UINT32_C(0x20)
+ uint32_t queue_id6_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id6_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * When this bit is '1' and the GRO mode is enabled,
- * the VNIC is configured to
- * perform transparent packet aggregation (TPA) for
- * TCP/IPv4 packets with consecutively increasing IPIDs.
- * In other words, the last packet that is being
- * aggregated to an already existing aggregation context
- * shall have IPID 1 more than the IPID of the last packet
- * that was aggregated in that aggregation context.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK \
- UINT32_C(0x40)
+ uint8_t queue_id6_pri_lvl;
/*
- * When this bit is '1' and the GRO mode is enabled,
- * the VNIC is configured to
- * perform transparent packet aggregation (TPA) for
- * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
- * value.
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK \
- UINT32_C(0x80)
+ uint8_t queue_id6_bw_weight;
+ /* ID of CoS Queue 7. */
+ uint8_t queue_id7;
/*
- * This is the maximum number of TCP segments that can
- * be aggregated (unit is Log2). Max value is 31.
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- uint16_t max_agg_segs;
- /* 1 segment */
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
- /* 2 segments */
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
- /* 4 segments */
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
- /* 8 segments */
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
- /* Any segment size larger than this is not valid */
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_LAST \
- HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX
+ uint32_t queue_id7_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * This is the maximum number of aggregations this VNIC is
- * allowed (unit is Log2). Max value is 7
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- uint16_t max_aggs;
- /* 1 aggregation */
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0)
- /* 2 aggregations */
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1)
- /* 4 aggregations */
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2)
- /* 8 aggregations */
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3)
- /* 16 aggregations */
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4)
- /* Any aggregation size larger than this is not valid */
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7)
- #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_LAST \
- HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX
+ uint32_t queue_id7_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id7_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * This is the maximum amount of time allowed for
- * an aggregation context to complete after it was initiated.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- uint32_t max_agg_timer;
+ uint8_t queue_id7_pri_lvl;
/*
- * This is the minimum amount of payload length required to
- * start an aggregation context.
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- uint32_t min_agg_len;
- uint8_t unused_0[7];
+ uint8_t queue_id7_bw_weight;
+ uint8_t unused_2[4];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/*********************
- * hwrm_vnic_rss_cfg *
- *********************/
+/*************************
+ * hwrm_queue_cos2bw_cfg *
+ *************************/
-/* hwrm_vnic_rss_cfg_input (size:384b/48B) */
-struct hwrm_vnic_rss_cfg_input {
+/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
+struct hwrm_queue_cos2bw_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t hash_type;
+ uint32_t flags;
+ uint32_t enables;
/*
- * When this bit is '1', the RSS hash shall be computed
- * over source and destination IPv4 addresses of IPv4
- * packets.
+ * If this bit is set to 1, then all queue_id0 related
+ * parameters in this command are valid.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
+ UINT32_C(0x1)
/*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv4 addresses and
- * source/destination ports of TCP/IPv4 packets.
+ * If this bit is set to 1, then all queue_id1 related
+ * parameters in this command are valid.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
+ UINT32_C(0x2)
/*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv4 addresses and
- * source/destination ports of UDP/IPv4 packets.
+ * If this bit is set to 1, then all queue_id2 related
+ * parameters in this command are valid.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
+ UINT32_C(0x4)
/*
- * When this bit is '1', the RSS hash shall be computed
- * over source and destination IPv4 addresses of IPv6
- * packets.
+ * If this bit is set to 1, then all queue_id3 related
+ * parameters in this command are valid.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
+ UINT32_C(0x8)
/*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv6 addresses and
- * source/destination ports of TCP/IPv6 packets.
+ * If this bit is set to 1, then all queue_id4 related
+ * parameters in this command are valid.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
+ UINT32_C(0x10)
/*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv6 addresses and
- * source/destination ports of UDP/IPv6 packets.
+ * If this bit is set to 1, then all queue_id5 related
+ * parameters in this command are valid.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
- /* VNIC ID of VNIC associated with RSS table being configured. */
- uint16_t vnic_id;
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
+ UINT32_C(0x20)
/*
- * Specifies which VNIC ring table pair to configure.
- * Valid values range from 0 to 7.
+ * If this bit is set to 1, then all queue_id6 related
+ * parameters in this command are valid.
*/
- uint8_t ring_table_pair_index;
- /* Flags to specify different RSS hash modes. */
- uint8_t hash_mode_flags;
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
+ UINT32_C(0x40)
/*
- * When this bit is '1', it indicates using current RSS
- * hash mode setting configured in the device.
+ * If this bit is set to 1, then all queue_id7 related
+ * parameters in this command are valid.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
- UINT32_C(0x1)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
+ UINT32_C(0x80)
/*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
- * l4.src, l4.dest} for tunnel packets. For none-tunnel
- * packets, the RSS hash is computed over the normal
- * src/dest l3 and src/dest l4 headers.
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure TC BW assignment on this port.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
- UINT32_C(0x2)
+ uint16_t port_id;
+ /* ID of CoS Queue 0. */
+ uint8_t queue_id0;
+ uint8_t unused_0;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id0_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
- * tunnel packets. For none-tunnel packets, the RSS hash is
- * computed over the normal src/dest l3 headers.
+ * Maximum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
- UINT32_C(0x4)
+ uint32_t queue_id0_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id0_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
- * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
- * packets, the RSS hash is computed over the normal
- * src/dest l3 and src/dest l4 headers.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
- UINT32_C(0x8)
+ uint8_t queue_id0_pri_lvl;
/*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
- * tunnel packets. For none-tunnel packets, the RSS hash is
- * computed over the normal src/dest l3 headers.
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
- UINT32_C(0x10)
- /* This is the address for rss ring group table */
- uint64_t ring_grp_tbl_addr;
- /* This is the address for rss hash key table */
- uint64_t hash_key_tbl_addr;
- /* Index to the rss indirection table. */
- uint16_t rss_ctx_idx;
- uint8_t unused_1[6];
-} __attribute__((packed));
-
-/* hwrm_vnic_rss_cfg_output (size:128b/16B) */
-struct hwrm_vnic_rss_cfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
+ uint8_t queue_id0_bw_weight;
+ /* ID of CoS Queue 1. */
+ uint8_t queue_id1;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/**********************
- * hwrm_vnic_rss_qcfg *
- **********************/
-
-
-/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
-struct hwrm_vnic_rss_qcfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint32_t queue_id1_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- uint16_t cmpl_ring;
+ uint32_t queue_id1_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id1_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- uint16_t seq_id;
+ uint8_t queue_id1_pri_lvl;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ uint8_t queue_id1_bw_weight;
+ /* ID of CoS Queue 2. */
+ uint8_t queue_id2;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- uint64_t resp_addr;
- /* Index to the rss indirection table. */
- uint16_t rss_ctx_idx;
- uint8_t unused_0[6];
-} __attribute__((packed));
-
-/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
-struct hwrm_vnic_rss_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint32_t hash_type;
+ uint32_t queue_id2_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * When this bit is '1', the RSS hash shall be computed
- * over source and destination IPv4 addresses of IPv4
- * packets.
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
+ uint32_t queue_id2_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id2_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv4 addresses and
- * source/destination ports of TCP/IPv4 packets.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
+ uint8_t queue_id2_pri_lvl;
/*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv4 addresses and
- * source/destination ports of UDP/IPv4 packets.
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
+ uint8_t queue_id2_bw_weight;
+ /* ID of CoS Queue 3. */
+ uint8_t queue_id3;
/*
- * When this bit is '1', the RSS hash shall be computed
- * over source and destination IPv4 addresses of IPv6
- * packets.
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
+ uint32_t queue_id3_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv6 addresses and
- * source/destination ports of TCP/IPv6 packets.
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
+ uint32_t queue_id3_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id3_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv6 addresses and
- * source/destination ports of UDP/IPv6 packets.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
- uint8_t unused_0[4];
- /* This is the value of rss hash key */
- uint32_t hash_key[10];
- /* Flags to specify different RSS hash modes. */
- uint8_t hash_mode_flags;
+ uint8_t queue_id3_pri_lvl;
/*
- * When this bit is '1', it indicates using current RSS
- * hash mode setting configured in the device.
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
- UINT32_C(0x1)
+ uint8_t queue_id3_bw_weight;
+ /* ID of CoS Queue 4. */
+ uint8_t queue_id4;
/*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
- * l4.src, l4.dest} for tunnel packets. For none-tunnel
- * packets, the RSS hash is computed over the normal
- * src/dest l3 and src/dest l4 headers.
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
- UINT32_C(0x2)
+ uint32_t queue_id4_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
- * tunnel packets. For none-tunnel packets, the RSS hash is
- * computed over the normal src/dest l3 headers.
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
- UINT32_C(0x4)
+ uint32_t queue_id4_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id4_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
- * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
- * packets, the RSS hash is computed over the normal
- * src/dest l3 and src/dest l4 headers.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
- UINT32_C(0x8)
+ uint8_t queue_id4_pri_lvl;
/*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
- * tunnel packets. For none-tunnel packets, the RSS hash is
- * computed over the normal src/dest l3 headers.
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
- UINT32_C(0x10)
- uint8_t unused_1[6];
+ uint8_t queue_id4_bw_weight;
+ /* ID of CoS Queue 5. */
+ uint8_t queue_id5;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/**************************
- * hwrm_vnic_plcmodes_cfg *
- **************************/
-
-
-/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
-struct hwrm_vnic_plcmodes_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint32_t queue_id5_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- uint16_t cmpl_ring;
+ uint32_t queue_id5_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id5_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- uint16_t seq_id;
+ uint8_t queue_id5_pri_lvl;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- uint16_t target_id;
+ uint8_t queue_id5_bw_weight;
+ /* ID of CoS Queue 6. */
+ uint8_t queue_id6;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- uint64_t resp_addr;
- uint32_t flags;
+ uint32_t queue_id6_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * When this bit is '1', the VNIC shall be configured to
- * use regular placement algorithm.
- * By default, the regular placement algorithm shall be
- * enabled on the VNIC.
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
+ uint32_t queue_id6_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id6_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
UINT32_C(0x1)
- /*
- * When this bit is '1', the VNIC shall be configured
- * use the jumbo placement algorithm.
- */
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * When this bit is '1', the VNIC shall be configured
- * to enable Header-Data split for IPv4 packets according
- * to the following rules:
- * # If the packet is identified as TCP/IPv4, then the
- * packet is split at the beginning of the TCP payload.
- * # If the packet is identified as UDP/IPv4, then the
- * packet is split at the beginning of UDP payload.
- * # If the packet is identified as non-TCP and non-UDP
- * IPv4 packet, then the packet is split at the beginning
- * of the upper layer protocol header carried in the IPv4
- * packet.
- */
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
- UINT32_C(0x4)
- /*
- * When this bit is '1', the VNIC shall be configured
- * to enable Header-Data split for IPv6 packets according
- * to the following rules:
- * # If the packet is identified as TCP/IPv6, then the
- * packet is split at the beginning of the TCP payload.
- * # If the packet is identified as UDP/IPv6, then the
- * packet is split at the beginning of UDP payload.
- * # If the packet is identified as non-TCP and non-UDP
- * IPv6 packet, then the packet is split at the beginning
- * of the upper layer protocol header carried in the IPv6
- * packet.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
- UINT32_C(0x8)
+ uint8_t queue_id6_pri_lvl;
/*
- * When this bit is '1', the VNIC shall be configured
- * to enable Header-Data split for FCoE packets at the
- * beginning of FC payload.
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
- UINT32_C(0x10)
+ uint8_t queue_id6_bw_weight;
+ /* ID of CoS Queue 7. */
+ uint8_t queue_id7;
/*
- * When this bit is '1', the VNIC shall be configured
- * to enable Header-Data split for RoCE packets at the
- * beginning of RoCE payload (after BTH/GRH headers).
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
- UINT32_C(0x20)
- uint32_t enables;
+ uint32_t queue_id7_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * This bit must be '1' for the jumbo_thresh_valid field to be
- * configured.
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
*/
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
+ uint32_t queue_id7_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id7_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
UINT32_C(0x1)
- /*
- * This bit must be '1' for the hds_offset_valid field to be
- * configured.
- */
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
/*
- * This bit must be '1' for the hds_threshold_valid field to be
- * configured.
- */
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
- UINT32_C(0x4)
- /* Logical vnic ID */
- uint32_t vnic_id;
- /*
- * When jumbo placement algorithm is enabled, this value
- * is used to determine the threshold for jumbo placement.
- * Packets with length larger than this value will be
- * placed according to the jumbo placement algorithm.
- */
- uint16_t jumbo_thresh;
- /*
- * This value is used to determine the offset into
- * packet buffer where the split data (payload) will be
- * placed according to one of of HDS placement algorithm.
- *
- * The lengths of packet buffers provided for split data
- * shall be larger than this value.
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
*/
- uint16_t hds_offset;
+ uint8_t queue_id7_pri_lvl;
/*
- * When one of the HDS placement algorithm is enabled, this
- * value is used to determine the threshold for HDS
- * placement.
- * Packets with length larger than this value will be
- * placed according to the HDS placement algorithm.
- * This value shall be in multiple of 4 bytes.
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
*/
- uint16_t hds_threshold;
- uint8_t unused_0[6];
+ uint8_t queue_id7_bw_weight;
+ uint8_t unused_1[5];
} __attribute__((packed));
-/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
-struct hwrm_vnic_plcmodes_cfg_output {
+/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
+struct hwrm_queue_cos2bw_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/***************************
- * hwrm_vnic_plcmodes_qcfg *
- ***************************/
+/*******************
+ * hwrm_vnic_alloc *
+ *******************/
-/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
-struct hwrm_vnic_plcmodes_qcfg_input {
+/* hwrm_vnic_alloc_input (size:192b/24B) */
+struct hwrm_vnic_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Logical vnic ID */
- uint32_t vnic_id;
- uint8_t unused_0[4];
-} __attribute__((packed));
-
-/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
-struct hwrm_vnic_plcmodes_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
uint32_t flags;
/*
- * When this bit is '1', the VNIC is configured to
- * use regular placement algorithm.
- */
- #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
- UINT32_C(0x1)
- /*
- * When this bit is '1', the VNIC is configured to
- * use the jumbo placement algorithm.
- */
- #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
- UINT32_C(0x2)
- /*
- * When this bit is '1', the VNIC is configured
- * to enable Header-Data split for IPv4 packets.
- */
- #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
- UINT32_C(0x4)
- /*
- * When this bit is '1', the VNIC is configured
- * to enable Header-Data split for IPv6 packets.
- */
- #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
- UINT32_C(0x8)
- /*
- * When this bit is '1', the VNIC is configured
- * to enable Header-Data split for FCoE packets.
- */
- #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
- UINT32_C(0x10)
- /*
- * When this bit is '1', the VNIC is configured
- * to enable Header-Data split for RoCE packets.
- */
- #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
- UINT32_C(0x20)
- /*
- * When this bit is '1', the VNIC is configured
- * to be the default VNIC of the requesting function.
- */
- #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
- UINT32_C(0x40)
- /*
- * When jumbo placement algorithm is enabled, this value
- * is used to determine the threshold for jumbo placement.
- * Packets with length larger than this value will be
- * placed according to the jumbo placement algorithm.
- */
- uint16_t jumbo_thresh;
- /*
- * This value is used to determine the offset into
- * packet buffer where the split data (payload) will be
- * placed according to one of of HDS placement algorithm.
- *
- * The lengths of packet buffers provided for split data
- * shall be larger than this value.
- */
- uint16_t hds_offset;
- /*
- * When one of the HDS placement algorithm is enabled, this
- * value is used to determine the threshold for HDS
- * placement.
- * Packets with length larger than this value will be
- * placed according to the HDS placement algorithm.
- * This value shall be in multiple of 4 bytes.
- */
- uint16_t hds_threshold;
- uint8_t unused_0[5];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/**********************************
- * hwrm_vnic_rss_cos_lb_ctx_alloc *
- **********************************/
-
-
-/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
-struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * When this bit is '1', this VNIC is requested to
+ * be the default VNIC for this function.
*/
- uint64_t resp_addr;
+ #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
+ uint8_t unused_0[4];
} __attribute__((packed));
-/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
-struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
+/* hwrm_vnic_alloc_output (size:128b/16B) */
+struct hwrm_vnic_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* rss_cos_lb_ctx_id is 16 b */
- uint16_t rss_cos_lb_ctx_id;
- uint8_t unused_0[5];
+ /* Logical vnic ID */
+ uint32_t vnic_id;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/*********************************
- * hwrm_vnic_rss_cos_lb_ctx_free *
- *********************************/
+/******************
+ * hwrm_vnic_free *
+ ******************/
-/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
-struct hwrm_vnic_rss_cos_lb_ctx_free_input {
+/* hwrm_vnic_free_input (size:192b/24B) */
+struct hwrm_vnic_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* rss_cos_lb_ctx_id is 16 b */
- uint16_t rss_cos_lb_ctx_id;
- uint8_t unused_0[6];
+ /* Logical vnic ID */
+ uint32_t vnic_id;
+ uint8_t unused_0[4];
} __attribute__((packed));
-/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
-struct hwrm_vnic_rss_cos_lb_ctx_free_output {
+/* hwrm_vnic_free_output (size:128b/16B) */
+struct hwrm_vnic_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/*******************
- * hwrm_ring_alloc *
- *******************/
+/*****************
+ * hwrm_vnic_cfg *
+ *****************/
-/* hwrm_ring_alloc_input (size:640b/80B) */
-struct hwrm_ring_alloc_input {
+/* hwrm_vnic_cfg_input (size:320b/40B) */
+struct hwrm_vnic_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
- /*
- * This bit must be '1' for the ring_arb_cfg field to be
- * configured.
- */
- #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
- UINT32_C(0x2)
- /*
- * This bit must be '1' for the stat_ctx_id_valid field to be
- * configured.
- */
- #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
- UINT32_C(0x8)
- /*
- * This bit must be '1' for the max_bw_valid field to be
- * configured.
- */
- #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
- UINT32_C(0x20)
- /*
- * This bit must be '1' for the rx_ring_id field to be
- * configured.
- */
- #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
- UINT32_C(0x40)
- /*
- * This bit must be '1' for the nq_ring_id field to be
- * configured.
- */
- #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
- UINT32_C(0x80)
+ uint32_t flags;
/*
- * This bit must be '1' for the rx_buf_size field to be
- * configured.
+ * When this bit is '1', the VNIC is requested to
+ * be the default VNIC for the function.
*/
- #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
- UINT32_C(0x100)
- /* Ring Type. */
- uint8_t ring_type;
- /* L2 Completion Ring (CR) */
- #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
- /* TX Ring (TR) */
- #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
- /* RX Ring (RR) */
- #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
- /* RoCE Notification Completion Ring (ROCE_CR) */
- #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
- /* RX Aggregation Ring */
- #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
- /* Notification Queue */
- #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
- #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
- HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
- uint8_t unused_0[3];
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
+ UINT32_C(0x1)
/*
- * This value is a pointer to the page table for the
- * Ring.
+ * When this bit is '1', the VNIC is being configured to
+ * strip VLAN in the RX path.
+ * If set to '0', then VLAN stripping is disabled on
+ * this VNIC.
*/
- uint64_t page_tbl_addr;
- /* First Byte Offset of the first entry in the first page. */
- uint32_t fbo;
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
+ UINT32_C(0x2)
/*
- * Actual page size in 2^page_size. The supported range is increments
- * in powers of 2 from 16 bytes to 1GB.
- * - 4 = 16 B
- * Page size is 16 B.
- * - 12 = 4 KB
- * Page size is 4 KB.
- * - 13 = 8 KB
- * Page size is 8 KB.
- * - 16 = 64 KB
- * Page size is 64 KB.
- * - 21 = 2 MB
- * Page size is 2 MB.
- * - 22 = 4 MB
- * Page size is 4 MB.
- * - 30 = 1 GB
- * Page size is 1 GB.
+ * When this bit is '1', the VNIC is being configured to
+ * buffer receive packets in the hardware until the host
+ * posts new receive buffers.
+ * If set to '0', then bd_stall is being configured to be
+ * disabled on this VNIC.
*/
- uint8_t page_size;
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
+ UINT32_C(0x4)
/*
- * This value indicates the depth of page table.
- * For this version of the specification, value other than 0 or
- * 1 shall be considered as an invalid value.
- * When the page_tbl_depth = 0, then it is treated as a
- * special case with the following.
- * 1. FBO and page size fields are not valid.
- * 2. page_tbl_addr is the physical address of the first
- * element of the ring.
+ * When this bit is '1', the VNIC is being configured to
+ * receive both RoCE and non-RoCE traffic.
+ * If set to '0', then this VNIC is not configured to be
+ * operating in dual VNIC mode.
*/
- uint8_t page_tbl_depth;
- uint8_t unused_1[2];
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
+ UINT32_C(0x8)
/*
- * Number of 16B units in the ring. Minimum size for
- * a ring is 16 16B entries.
+ * When this flag is set to '1', the VNIC is requested to
+ * be configured to receive only RoCE traffic.
+ * If this flag is set to '0', then this flag shall be
+ * ignored by the HWRM.
+ * If roce_dual_vnic_mode flag is set to '1'
+ * or roce_mirroring_capable_vnic_mode flag to 1,
+ * then the HWRM client shall not set this flag to '1'.
*/
- uint32_t length;
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
+ UINT32_C(0x10)
/*
- * Logical ring number for the ring to be allocated.
- * This value determines the position in the doorbell
- * area where the update to the ring will be made.
+ * When a VNIC uses one destination ring group for certain
+ * application (e.g. Receive Flow Steering) where
+ * exact match is used to direct packets to a VNIC with one
+ * destination ring group only, there is no need to configure
+ * RSS indirection table for that VNIC as only one destination
+ * ring group is used.
*
- * For completion rings, this value is also the MSI-X
- * vector number for the function the completion ring is
- * associated with.
+ * This flag is used to enable a mode where
+ * RSS is enabled in the VNIC using a RSS context
+ * for computing RSS hash but the RSS indirection table is
+ * not configured using hwrm_vnic_rss_cfg.
+ *
+ * If this mode is enabled, then the driver should not program
+ * RSS indirection table for the RSS context that is used for
+ * computing RSS hash only.
*/
- uint16_t logical_id;
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
+ UINT32_C(0x20)
/*
- * This field is used only when ring_type is a TX ring.
- * This value indicates what completion ring the TX ring
- * is associated with.
+ * When this bit is '1', the VNIC is being configured to
+ * receive both RoCE and non-RoCE traffic, but forward only the
+ * RoCE traffic further. Also, RoCE traffic can be mirrored to
+ * L2 driver.
*/
- uint16_t cmpl_ring_id;
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
+ UINT32_C(0x40)
+ uint32_t enables;
/*
- * This field is used only when ring_type is a TX ring.
- * This value indicates what CoS queue the TX ring
- * is associated with.
+ * This bit must be '1' for the dflt_ring_grp field to be
+ * configured.
*/
- uint16_t queue_id;
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
+ UINT32_C(0x1)
/*
- * When allocating a Rx ring or Rx aggregation ring, this field
- * specifies the size of the buffer descriptors posted to the ring.
+ * This bit must be '1' for the rss_rule field to be
+ * configured.
*/
- uint16_t rx_buf_size;
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
+ UINT32_C(0x2)
/*
- * When allocating an Rx aggregation ring, this field
- * specifies the associated Rx ring ID.
+ * This bit must be '1' for the cos_rule field to be
+ * configured.
*/
- uint16_t rx_ring_id;
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
+ UINT32_C(0x4)
/*
- * When allocating a completion ring, this field
- * specifies the associated NQ ring ID.
+ * This bit must be '1' for the lb_rule field to be
+ * configured.
*/
- uint16_t nq_ring_id;
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
+ UINT32_C(0x8)
/*
- * This field is used only when ring_type is a TX ring.
- * This field is used to configure arbitration related
- * parameters for a TX ring.
+ * This bit must be '1' for the mru field to be
+ * configured.
*/
- uint16_t ring_arb_cfg;
- /* Arbitration policy used for the ring. */
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
- UINT32_C(0xf)
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
+ UINT32_C(0x10)
/*
- * Use strict priority for the TX ring.
- * Priority value is specified in arb_policy_param
+ * This bit must be '1' for the default_rx_ring_id field to be
+ * configured.
*/
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
- UINT32_C(0x1)
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
+ UINT32_C(0x20)
/*
- * Use weighted fair queue arbitration for the TX ring.
- * Weight is specified in arb_policy_param
+ * This bit must be '1' for the default_cmpl_ring_id field to be
+ * configured.
*/
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
- UINT32_C(0x2)
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
- HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
- /* Reserved field. */
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
- UINT32_C(0xf0)
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
+ UINT32_C(0x40)
+ /* Logical vnic ID */
+ uint16_t vnic_id;
/*
- * Arbitration policy specific parameter.
- * # For strict priority arbitration policy, this field
- * represents a priority value. If set to 0, then the priority
- * is not specified and the HWRM is allowed to select
- * any priority for this TX ring.
- * # For weighted fair queue arbitration policy, this field
- * represents a weight value. If set to 0, then the weight
- * is not specified and the HWRM is allowed to select
- * any weight for this TX ring.
+ * Default Completion ring for the VNIC. This ring will
+ * be chosen if packet does not match any RSS rules and if
+ * there is no COS rule.
*/
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
- UINT32_C(0xff00)
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
- uint16_t unused_3;
+ uint16_t dflt_ring_grp;
/*
- * This field is reserved for the future use.
- * It shall be set to 0.
+ * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
+ * there is no RSS rule.
*/
- uint32_t reserved3;
+ uint16_t rss_rule;
/*
- * This field is used only when ring_type is a TX ring.
- * This input indicates what statistics context this ring
- * should be associated with.
+ * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
+ * there is no COS rule.
*/
- uint32_t stat_ctx_id;
+ uint16_t cos_rule;
/*
- * This field is reserved for the future use.
- * It shall be set to 0.
+ * RSS ID for load balancing rule/table structure.
+ * 0xFF... (All Fs) if there is no LB rule.
*/
- uint32_t reserved4;
+ uint16_t lb_rule;
/*
- * This field is used only when ring_type is a TX ring
- * to specify maximum BW allocated to the TX ring.
- * The HWRM will translate this value into byte counter and
- * time interval used for this ring inside the device.
+ * The maximum receive unit of the vnic.
+ * Each vnic is associated with a function.
+ * The vnic mru value overwrites the mru setting of the
+ * associated function.
+ * The HWRM shall make sure that vnic mru does not exceed
+ * the mru of the port the function is associated with.
*/
- uint32_t max_bw;
- /* The bandwidth value. */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
- HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
+ uint16_t mru;
/*
- * This field is used only when ring_type is a Completion ring.
- * This value indicates what interrupt mode should be used
- * on this completion ring.
- * Note: In the legacy interrupt mode, no more than 16
- * completion rings are allowed.
+ * Default Rx ring for the VNIC. This ring will
+ * be chosen if packet does not match any RSS rules.
+ * The aggregation ring associated with the Rx ring is
+ * implied based on the Rx ring specified when the
+ * aggregation ring was allocated.
*/
- uint8_t int_mode;
- /* Legacy INTA */
- #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
- /* Reserved */
- #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
- /* MSI-X */
- #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
- /* No Interrupt - Polled mode */
- #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
- #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
- HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
- uint8_t unused_4[3];
+ uint16_t default_rx_ring_id;
+ /*
+ * Default completion ring for the VNIC. This ring will
+ * be chosen if packet does not match any RSS rules.
+ */
+ uint16_t default_cmpl_ring_id;
} __attribute__((packed));
-/* hwrm_ring_alloc_output (size:128b/16B) */
-struct hwrm_ring_alloc_output {
+/* hwrm_vnic_cfg_output (size:128b/16B) */
+struct hwrm_vnic_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /*
- * Physical number of ring allocated.
- * This value shall be unique for a ring type.
- */
- uint16_t ring_id;
- /* Logical number of ring allocated. */
- uint16_t logical_ring_id;
- uint8_t unused_0[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
} __attribute__((packed));
/******************
- * hwrm_ring_free *
+ * hwrm_vnic_qcfg *
******************/
-/* hwrm_ring_free_input (size:192b/24B) */
-struct hwrm_ring_free_input {
+/* hwrm_vnic_qcfg_input (size:256b/32B) */
+struct hwrm_vnic_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Ring Type. */
- uint8_t ring_type;
- /* L2 Completion Ring (CR) */
- #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
- /* TX Ring (TR) */
- #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
- /* RX Ring (RR) */
- #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
- /* RoCE Notification Completion Ring (ROCE_CR) */
- #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
- /* RX Aggregation Ring */
- #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
- /* Notification Queue */
- #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
- #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
- HWRM_RING_FREE_INPUT_RING_TYPE_NQ
- uint8_t unused_0;
- /* Physical number of ring allocated. */
- uint16_t ring_id;
- uint8_t unused_1[4];
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the vf_id_valid field to be
+ * configured.
+ */
+ #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
+ /* Logical vnic ID */
+ uint32_t vnic_id;
+ /* ID of Virtual Function whose VNIC resource is being queried. */
+ uint16_t vf_id;
+ uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_ring_free_output (size:128b/16B) */
-struct hwrm_ring_free_output {
+/* hwrm_vnic_qcfg_output (size:256b/32B) */
+struct hwrm_vnic_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /* Default Completion ring for the VNIC. */
+ uint16_t dflt_ring_grp;
+ /*
+ * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
+ * there is no RSS rule.
+ */
+ uint16_t rss_rule;
+ /*
+ * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
+ * there is no COS rule.
+ */
+ uint16_t cos_rule;
+ /*
+ * RSS ID for load balancing rule/table structure.
+ * 0xFF... (All Fs) if there is no LB rule.
+ */
+ uint16_t lb_rule;
+ /* The maximum receive unit of the vnic. */
+ uint16_t mru;
+ uint8_t unused_0[2];
+ uint32_t flags;
+ /*
+ * When this bit is '1', the VNIC is the default VNIC for
+ * the function.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', the VNIC is configured to
+ * strip VLAN in the RX path.
+ * If set to '0', then VLAN stripping is disabled on
+ * this VNIC.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
+ UINT32_C(0x2)
+ /*
+ * When this bit is '1', the VNIC is configured to
+ * buffer receive packets in the hardware until the host
+ * posts new receive buffers.
+ * If set to '0', then bd_stall is disabled on
+ * this VNIC.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
+ UINT32_C(0x4)
+ /*
+ * When this bit is '1', the VNIC is configured to
+ * receive both RoCE and non-RoCE traffic.
+ * If set to '0', then this VNIC is not configured to
+ * operate in dual VNIC mode.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
+ UINT32_C(0x8)
+ /*
+ * When this flag is set to '1', the VNIC is configured to
+ * receive only RoCE traffic.
+ * When this flag is set to '0', the VNIC is not configured
+ * to receive only RoCE traffic.
+ * If roce_dual_vnic_mode flag and this flag both are set
+ * to '1', then it is an invalid configuration of the
+ * VNIC. The HWRM should not allow that type of
+ * mis-configuration by HWRM clients.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
+ UINT32_C(0x10)
+ /*
+ * When a VNIC uses one destination ring group for certain
+ * application (e.g. Receive Flow Steering) where
+ * exact match is used to direct packets to a VNIC with one
+ * destination ring group only, there is no need to configure
+ * RSS indirection table for that VNIC as only one destination
+ * ring group is used.
+ *
+ * When this bit is set to '1', then the VNIC is enabled in a
+ * mode where RSS is enabled in the VNIC using a RSS context
+ * for computing RSS hash but the RSS indirection table is
+ * not configured.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
+ UINT32_C(0x20)
+ /*
+ * When this bit is '1', the VNIC is configured to
+ * receive both RoCE and non-RoCE traffic, but forward only
+ * RoCE traffic further. Also RoCE traffic can be mirrored to
+ * L2 driver.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
+ UINT32_C(0x40)
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/**************************************
- * hwrm_ring_cmpl_ring_qaggint_params *
- **************************************/
+/*******************
+ * hwrm_vnic_qcaps *
+ *******************/
-/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
-struct hwrm_ring_cmpl_ring_qaggint_params_input {
+/* hwrm_vnic_qcaps_input (size:192b/24B) */
+struct hwrm_vnic_qcaps_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Physical number of completion ring. */
- uint16_t ring_id;
- uint8_t unused_0[6];
+ uint32_t enables;
+ uint8_t unused_0[4];
} __attribute__((packed));
-/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
-struct hwrm_ring_cmpl_ring_qaggint_params_output {
+/* hwrm_vnic_qcaps_output (size:192b/24B) */
+struct hwrm_vnic_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint16_t flags;
- /*
- * When this bit is set to '1', interrupt max
- * timer is reset whenever a completion is received.
- */
- #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
+ /* The maximum receive unit that is settable on a vnic. */
+ uint16_t mru;
+ uint8_t unused_0[2];
+ uint32_t flags;
+ /* Unused. */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
UINT32_C(0x1)
/*
- * When this bit is set to '1', ring idle mode
- * aggregation will be enabled.
+ * When this bit is '1', the capability of stripping VLAN in
+ * the RX path is supported on VNIC(s).
+ * If set to '0', then VLAN stripping capability is
+ * not supported on VNIC(s).
*/
- #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
UINT32_C(0x2)
/*
- * Number of completions to aggregate before DMA
- * during the normal mode.
+ * When this bit is '1', the capability to buffer receive
+ * packets in the hardware until the host posts new receive buffers
+ * is supported on VNIC(s).
+ * If set to '0', then bd_stall capability is not supported
+ * on VNIC(s).
*/
- uint16_t num_cmpl_dma_aggr;
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
+ UINT32_C(0x4)
/*
- * Number of completions to aggregate before DMA
- * during the interrupt mode.
+ * When this bit is '1', the capability to
+ * receive both RoCE and non-RoCE traffic on VNIC(s) is
+ * supported.
+ * If set to '0', then the capability to receive
+ * both RoCE and non-RoCE traffic on VNIC(s) is
+ * not supported.
*/
- uint16_t num_cmpl_dma_aggr_during_int;
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
+ UINT32_C(0x8)
/*
- * Timer in unit of 80-nsec used to aggregate completions before
- * DMA during the normal mode (not in interrupt mode).
+ * When this bit is set to '1', the capability to configure
+ * a VNIC to receive only RoCE traffic is supported.
+ * When this flag is set to '0', the VNIC capability to
+ * configure to receive only RoCE traffic is not supported.
*/
- uint16_t cmpl_aggr_dma_tmr;
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
+ UINT32_C(0x10)
/*
- * Timer in unit of 80-nsec used to aggregate completions before
- * DMA during the interrupt mode.
+ * When this bit is set to '1', then the capability to enable
+ * a VNIC in a mode where RSS context without configuring
+ * RSS indirection table is supported (for RSS hash computation).
+ * When this bit is set to '0', then a VNIC can not be configured
+ * with a mode to enable RSS context without configuring RSS
+ * indirection table.
*/
- uint16_t cmpl_aggr_dma_tmr_during_int;
- /* Minimum time (in unit of 80-nsec) between two interrupts. */
- uint16_t int_lat_tmr_min;
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
+ UINT32_C(0x20)
/*
- * Maximum wait time (in unit of 80-nsec) spent aggregating
- * completions before signaling the interrupt after the
- * interrupt is enabled.
+ * When this bit is '1', the capability to
+ * mirror the the RoCE traffic is supported.
+ * If set to '0', then the capability to mirror the
+ * RoCE traffic is not supported.
*/
- uint16_t int_lat_tmr_max;
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
+ UINT32_C(0x40)
/*
- * Minimum number of completions aggregated before signaling
- * an interrupt.
+ * When this bit is '1', the outermost RSS hashing capability
+ * is supported. If set to '0', then the outermost RSS hashing
+ * capability is not supported.
*/
- uint16_t num_cmpl_aggr_int;
- uint8_t unused_0[7];
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
+ UINT32_C(0x80)
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/*****************************************
- * hwrm_ring_cmpl_ring_cfg_aggint_params *
- *****************************************/
+/*********************
+ * hwrm_vnic_tpa_cfg *
+ *********************/
-/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
-struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
+/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
+struct hwrm_vnic_tpa_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Physical number of completion ring. */
- uint16_t ring_id;
- uint16_t flags;
+ uint32_t flags;
/*
- * When this bit is set to '1', interrupt latency max
- * timer is reset whenever a completion is received.
+ * When this bit is '1', the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) of
+ * non-tunneled TCP packets.
*/
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
UINT32_C(0x1)
/*
- * When this bit is set to '1', ring idle mode
- * aggregation will be enabled.
+ * When this bit is '1', the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) of
+ * tunneled TCP packets.
*/
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
UINT32_C(0x2)
/*
- * Set this flag to 1 when configuring parameters on a
- * notification queue. Set this flag to 0 when configuring
- * parameters on a completion queue.
+ * When this bit is '1', the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) according
+ * to Windows Receive Segment Coalescing (RSC) rules.
*/
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
UINT32_C(0x4)
/*
- * Number of completions to aggregate before DMA
- * during the normal mode.
+ * When this bit is '1', the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) according
+ * to Linux Generic Receive Offload (GRO) rules.
*/
- uint16_t num_cmpl_dma_aggr;
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
+ UINT32_C(0x8)
/*
- * Number of completions to aggregate before DMA
- * during the interrupt mode.
+ * When this bit is '1', the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) for TCP
+ * packets with IP ECN set to non-zero.
*/
- uint16_t num_cmpl_dma_aggr_during_int;
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
+ UINT32_C(0x10)
/*
- * Timer in unit of 80-nsec used to aggregate completions before
- * DMA during the normal mode (not in interrupt mode).
+ * When this bit is '1', the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) for
+ * GRE tunneled TCP packets only if all packets have the
+ * same GRE sequence.
*/
- uint16_t cmpl_aggr_dma_tmr;
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
+ UINT32_C(0x20)
/*
- * Timer in unit of 80-nsec used to aggregate completions before
- * DMA during the interrupt mode.
+ * When this bit is '1' and the GRO mode is enabled,
+ * the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) for
+ * TCP/IPv4 packets with consecutively increasing IPIDs.
+ * In other words, the last packet that is being
+ * aggregated to an already existing aggregation context
+ * shall have IPID 1 more than the IPID of the last packet
+ * that was aggregated in that aggregation context.
*/
- uint16_t cmpl_aggr_dma_tmr_during_int;
- /* Minimum time (in unit of 80-nsec) between two interrupts. */
- uint16_t int_lat_tmr_min;
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
+ UINT32_C(0x40)
/*
- * Maximum wait time (in unit of 80-nsec) spent aggregating
- * cmpls before signaling the interrupt after the
- * interrupt is enabled.
+ * When this bit is '1' and the GRO mode is enabled,
+ * the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) for
+ * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
+ * value.
*/
- uint16_t int_lat_tmr_max;
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
+ UINT32_C(0x80)
+ uint32_t enables;
/*
- * Minimum number of completions aggregated before signaling
- * an interrupt.
+ * This bit must be '1' for the max_agg_segs field to be
+ * configured.
*/
- uint16_t num_cmpl_aggr_int;
+ #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
/*
- * Bitfield that indicates which parameters are to be applied. Only
- * required when configuring devices with notification queues, and
- * used in that case to set certain parameters on completion queues
- * and others on notification queues.
+ * This bit must be '1' for the max_aggs field to be
+ * configured.
*/
- uint16_t enables;
+ #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
/*
- * This bit must be '1' for the num_cmpl_dma_aggr field to be
+ * This bit must be '1' for the max_agg_timer field to be
* configured.
*/
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
- UINT32_C(0x1)
+ #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
/*
- * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
+ * This bit must be '1' for the min_agg_len field to be
* configured.
*/
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
- UINT32_C(0x2)
+ #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
+ /* Logical vnic ID */
+ uint16_t vnic_id;
/*
- * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
- * configured.
+ * This is the maximum number of TCP segments that can
+ * be aggregated (unit is Log2). Max value is 31.
*/
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
- UINT32_C(0x4)
+ uint16_t max_agg_segs;
+ /* 1 segment */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
+ /* 2 segments */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
+ /* 4 segments */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
+ /* 8 segments */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
+ /* Any segment size larger than this is not valid */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
+ HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
/*
- * This bit must be '1' for the int_lat_tmr_min field to be
- * configured.
+ * This is the maximum number of aggregations this VNIC is
+ * allowed (unit is Log2). Max value is 7
*/
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
- UINT32_C(0x8)
+ uint16_t max_aggs;
+ /* 1 aggregation */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
+ /* 2 aggregations */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
+ /* 4 aggregations */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
+ /* 8 aggregations */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
+ /* 16 aggregations */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
+ /* Any aggregation size larger than this is not valid */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
+ HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
+ uint8_t unused_0[2];
/*
- * This bit must be '1' for the int_lat_tmr_max field to be
- * configured.
+ * This is the maximum amount of time allowed for
+ * an aggregation context to complete after it was initiated.
*/
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
- UINT32_C(0x10)
+ uint32_t max_agg_timer;
/*
- * This bit must be '1' for the num_cmpl_aggr_int field to be
- * configured.
+ * This is the minimum amount of payload length required to
+ * start an aggregation context.
*/
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
- UINT32_C(0x20)
- uint8_t unused_0[4];
+ uint32_t min_agg_len;
} __attribute__((packed));
-/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
-struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
+/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
+struct hwrm_vnic_tpa_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/*******************
- * hwrm_ring_reset *
- *******************/
+/*********************
+ * hwrm_vnic_rss_cfg *
+ *********************/
-/* hwrm_ring_reset_input (size:192b/24B) */
-struct hwrm_ring_reset_input {
+/* hwrm_vnic_rss_cfg_input (size:384b/48B) */
+struct hwrm_vnic_rss_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Ring Type. */
- uint8_t ring_type;
- /* L2 Completion Ring (CR) */
- #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
- /* TX Ring (TR) */
- #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
- /* RX Ring (RR) */
- #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
- /* RoCE Notification Completion Ring (ROCE_CR) */
- #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
- #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
- HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL
- uint8_t unused_0;
- /* Physical number of the ring. */
- uint16_t ring_id;
- uint8_t unused_1[4];
+ uint32_t hash_type;
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source and destination IPv4 addresses of IPv4
+ * packets.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv4 addresses and
+ * source/destination ports of TCP/IPv4 packets.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv4 addresses and
+ * source/destination ports of UDP/IPv4 packets.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source and destination IPv4 addresses of IPv6
+ * packets.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv6 addresses and
+ * source/destination ports of TCP/IPv6 packets.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv6 addresses and
+ * source/destination ports of UDP/IPv6 packets.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
+ /* VNIC ID of VNIC associated with RSS table being configured. */
+ uint16_t vnic_id;
+ /*
+ * Specifies which VNIC ring table pair to configure.
+ * Valid values range from 0 to 7.
+ */
+ uint8_t ring_table_pair_index;
+ /* Flags to specify different RSS hash modes. */
+ uint8_t hash_mode_flags;
+ /*
+ * When this bit is '1', it indicates using current RSS
+ * hash mode setting configured in the device.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
+ * l4.src, l4.dest} for tunnel packets. For none-tunnel
+ * packets, the RSS hash is computed over the normal
+ * src/dest l3 and src/dest l4 headers.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
+ UINT32_C(0x2)
+ /*
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
+ * tunnel packets. For none-tunnel packets, the RSS hash is
+ * computed over the normal src/dest l3 headers.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
+ UINT32_C(0x4)
+ /*
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
+ * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
+ * packets, the RSS hash is computed over the normal
+ * src/dest l3 and src/dest l4 headers.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
+ UINT32_C(0x8)
+ /*
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
+ * tunnel packets. For none-tunnel packets, the RSS hash is
+ * computed over the normal src/dest l3 headers.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
+ UINT32_C(0x10)
+ /* This is the address for rss ring group table */
+ uint64_t ring_grp_tbl_addr;
+ /* This is the address for rss hash key table */
+ uint64_t hash_key_tbl_addr;
+ /* Index to the rss indirection table. */
+ uint16_t rss_ctx_idx;
+ uint8_t unused_1[6];
} __attribute__((packed));
-/* hwrm_ring_reset_output (size:128b/16B) */
-struct hwrm_ring_reset_output {
+/* hwrm_vnic_rss_cfg_output (size:128b/16B) */
+struct hwrm_vnic_rss_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_ring_grp_alloc *
- ***********************/
+/**********************
+ * hwrm_vnic_rss_qcfg *
+ **********************/
-/* hwrm_ring_grp_alloc_input (size:192b/24B) */
-struct hwrm_ring_grp_alloc_input {
+/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
+struct hwrm_vnic_rss_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * This value identifies the CR associated with the ring
- * group.
- */
- uint16_t cr;
- /*
- * This value identifies the main RR associated with the ring
- * group.
- */
- uint16_t rr;
- /*
- * This value identifies the aggregation RR associated with
- * the ring group. If this value is 0xFF... (All Fs), then no
- * Aggregation ring will be set.
- */
- uint16_t ar;
- /*
- * This value identifies the statistics context associated
- * with the ring group.
- */
- uint16_t sc;
+ /* Index to the rss indirection table. */
+ uint16_t rss_ctx_idx;
+ uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_ring_grp_alloc_output (size:128b/16B) */
-struct hwrm_ring_grp_alloc_output {
+/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
+struct hwrm_vnic_rss_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ uint32_t hash_type;
/*
- * This is the ring group ID value. Use this value to program
- * the default ring group for the VNIC or as table entries
- * in an RSS/COS context.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source and destination IPv4 addresses of IPv4
+ * packets.
*/
- uint32_t ring_group_id;
- uint8_t unused_0[3];
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv4 addresses and
+ * source/destination ports of TCP/IPv4 packets.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/**********************
- * hwrm_ring_grp_free *
- **********************/
-
-
-/* hwrm_ring_grp_free_input (size:192b/24B) */
-struct hwrm_ring_grp_free_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv4 addresses and
+ * source/destination ports of UDP/IPv4 packets.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source and destination IPv4 addresses of IPv6
+ * packets.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv6 addresses and
+ * source/destination ports of TCP/IPv6 packets.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv6 addresses and
+ * source/destination ports of UDP/IPv6 packets.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
+ uint8_t unused_0[4];
+ /* This is the value of rss hash key */
+ uint32_t hash_key[10];
+ /* Flags to specify different RSS hash modes. */
+ uint8_t hash_mode_flags;
+ /*
+ * When this bit is '1', it indicates using current RSS
+ * hash mode setting configured in the device.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
+ * l4.src, l4.dest} for tunnel packets. For none-tunnel
+ * packets, the RSS hash is computed over the normal
+ * src/dest l3 and src/dest l4 headers.
*/
- uint16_t cmpl_ring;
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
+ UINT32_C(0x2)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
+ * tunnel packets. For none-tunnel packets, the RSS hash is
+ * computed over the normal src/dest l3 headers.
*/
- uint16_t seq_id;
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
+ UINT32_C(0x4)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
+ * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
+ * packets, the RSS hash is computed over the normal
+ * src/dest l3 and src/dest l4 headers.
*/
- uint16_t target_id;
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
+ UINT32_C(0x8)
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
+ * tunnel packets. For none-tunnel packets, the RSS hash is
+ * computed over the normal src/dest l3 headers.
*/
- uint64_t resp_addr;
- /* This is the ring group ID value. */
- uint32_t ring_group_id;
- uint8_t unused_0[4];
-} __attribute__((packed));
-
-/* hwrm_ring_grp_free_output (size:128b/16B) */
-struct hwrm_ring_grp_free_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
+ UINT32_C(0x10)
+ uint8_t unused_1[6];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/****************************
- * hwrm_cfa_l2_filter_alloc *
- ****************************/
+/**************************
+ * hwrm_vnic_plcmodes_cfg *
+ **************************/
-/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
-struct hwrm_cfa_l2_filter_alloc_input {
+/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
+struct hwrm_vnic_plcmodes_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
uint64_t resp_addr;
uint32_t flags;
/*
- * Enumeration denoting the RX, TX type of the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
- */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
- UINT32_C(0x1)
- /* tx path */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
- UINT32_C(0x0)
- /* rx path */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
- UINT32_C(0x1)
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
- /* Setting of this flag indicates the applicability to the loopback path. */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
- UINT32_C(0x2)
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
- UINT32_C(0x4)
- /*
- * If this flag is set, all t_l2_* fields are invalid
- * and they should not be specified.
- * If this flag is set, then l2_* fields refer to
- * fields of outermost L2 header.
- */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
- UINT32_C(0x8)
- uint32_t enables;
- /*
- * This bit must be '1' for the l2_addr field to be
- * configured.
+ * When this bit is '1', the VNIC shall be configured to
+ * use regular placement algorithm.
+ * By default, the regular placement algorithm shall be
+ * enabled on the VNIC.
*/
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
UINT32_C(0x1)
/*
- * This bit must be '1' for the l2_addr_mask field to be
- * configured.
+ * When this bit is '1', the VNIC shall be configured
+ * use the jumbo placement algorithm.
*/
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
UINT32_C(0x2)
/*
- * This bit must be '1' for the l2_ovlan field to be
- * configured.
+ * When this bit is '1', the VNIC shall be configured
+ * to enable Header-Data split for IPv4 packets according
+ * to the following rules:
+ * # If the packet is identified as TCP/IPv4, then the
+ * packet is split at the beginning of the TCP payload.
+ * # If the packet is identified as UDP/IPv4, then the
+ * packet is split at the beginning of UDP payload.
+ * # If the packet is identified as non-TCP and non-UDP
+ * IPv4 packet, then the packet is split at the beginning
+ * of the upper layer protocol header carried in the IPv4
+ * packet.
*/
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
UINT32_C(0x4)
/*
- * This bit must be '1' for the l2_ovlan_mask field to be
- * configured.
+ * When this bit is '1', the VNIC shall be configured
+ * to enable Header-Data split for IPv6 packets according
+ * to the following rules:
+ * # If the packet is identified as TCP/IPv6, then the
+ * packet is split at the beginning of the TCP payload.
+ * # If the packet is identified as UDP/IPv6, then the
+ * packet is split at the beginning of UDP payload.
+ * # If the packet is identified as non-TCP and non-UDP
+ * IPv6 packet, then the packet is split at the beginning
+ * of the upper layer protocol header carried in the IPv6
+ * packet.
*/
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
UINT32_C(0x8)
/*
- * This bit must be '1' for the l2_ivlan field to be
- * configured.
+ * When this bit is '1', the VNIC shall be configured
+ * to enable Header-Data split for FCoE packets at the
+ * beginning of FC payload.
*/
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
UINT32_C(0x10)
/*
- * This bit must be '1' for the l2_ivlan_mask field to be
- * configured.
+ * When this bit is '1', the VNIC shall be configured
+ * to enable Header-Data split for RoCE packets at the
+ * beginning of RoCE payload (after BTH/GRH headers).
*/
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
UINT32_C(0x20)
+ uint32_t enables;
/*
- * This bit must be '1' for the t_l2_addr field to be
- * configured.
- */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
- UINT32_C(0x40)
- /*
- * This bit must be '1' for the t_l2_addr_mask field to be
- * configured.
- */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
- UINT32_C(0x80)
- /*
- * This bit must be '1' for the t_l2_ovlan field to be
- * configured.
- */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
- UINT32_C(0x100)
- /*
- * This bit must be '1' for the t_l2_ovlan_mask field to be
- * configured.
- */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
- UINT32_C(0x200)
- /*
- * This bit must be '1' for the t_l2_ivlan field to be
- * configured.
- */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
- UINT32_C(0x400)
- /*
- * This bit must be '1' for the t_l2_ivlan_mask field to be
- * configured.
- */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
- UINT32_C(0x800)
- /*
- * This bit must be '1' for the src_type field to be
+ * This bit must be '1' for the jumbo_thresh_valid field to be
* configured.
*/
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
- UINT32_C(0x1000)
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
+ UINT32_C(0x1)
/*
- * This bit must be '1' for the src_id field to be
+ * This bit must be '1' for the hds_offset_valid field to be
* configured.
*/
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
- UINT32_C(0x2000)
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
+ UINT32_C(0x2)
/*
- * This bit must be '1' for the tunnel_type field to be
+ * This bit must be '1' for the hds_threshold_valid field to be
* configured.
*/
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
- UINT32_C(0x4000)
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
+ UINT32_C(0x4)
+ /* Logical vnic ID */
+ uint32_t vnic_id;
/*
- * This bit must be '1' for the dst_id field to be
- * configured.
+ * When jumbo placement algorithm is enabled, this value
+ * is used to determine the threshold for jumbo placement.
+ * Packets with length larger than this value will be
+ * placed according to the jumbo placement algorithm.
*/
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
- UINT32_C(0x8000)
+ uint16_t jumbo_thresh;
/*
- * This bit must be '1' for the mirror_vnic_id field to be
- * configured.
+ * This value is used to determine the offset into
+ * packet buffer where the split data (payload) will be
+ * placed according to one of of HDS placement algorithm.
+ *
+ * The lengths of packet buffers provided for split data
+ * shall be larger than this value.
*/
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
- UINT32_C(0x10000)
+ uint16_t hds_offset;
/*
- * This value sets the match value for the L2 MAC address.
- * Destination MAC address for RX path.
- * Source MAC address for TX path.
+ * When one of the HDS placement algorithm is enabled, this
+ * value is used to determine the threshold for HDS
+ * placement.
+ * Packets with length larger than this value will be
+ * placed according to the HDS placement algorithm.
+ * This value shall be in multiple of 4 bytes.
*/
- uint8_t l2_addr[6];
- uint8_t unused_0[2];
+ uint16_t hds_threshold;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
+struct hwrm_vnic_plcmodes_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * This value sets the mask value for the L2 address.
- * A value of 0 will mask the corresponding bit from
- * compare.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t l2_addr_mask[6];
- /* This value sets VLAN ID value for outer VLAN. */
- uint16_t l2_ovlan;
+ uint8_t valid;
+} __attribute__((packed));
+
+/***************************
+ * hwrm_vnic_plcmodes_qcfg *
+ ***************************/
+
+
+/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
+struct hwrm_vnic_plcmodes_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This value sets the mask value for the ovlan id.
- * A value of 0 will mask the corresponding bit from
- * compare.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t l2_ovlan_mask;
- /* This value sets VLAN ID value for inner VLAN. */
- uint16_t l2_ivlan;
+ uint16_t cmpl_ring;
/*
- * This value sets the mask value for the ivlan id.
- * A value of 0 will mask the corresponding bit from
- * compare.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint16_t l2_ivlan_mask;
- uint8_t unused_1[2];
+ uint16_t seq_id;
/*
- * This value sets the match value for the tunnel
- * L2 MAC address.
- * Destination MAC address for RX path.
- * Source MAC address for TX path.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint8_t t_l2_addr[6];
- uint8_t unused_2[2];
+ uint16_t target_id;
/*
- * This value sets the mask value for the tunnel L2
- * address.
- * A value of 0 will mask the corresponding bit from
- * compare.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint8_t t_l2_addr_mask[6];
- /* This value sets VLAN ID value for tunnel outer VLAN. */
- uint16_t t_l2_ovlan;
+ uint64_t resp_addr;
+ /* Logical vnic ID */
+ uint32_t vnic_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
+struct hwrm_vnic_plcmodes_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
/*
- * This value sets the mask value for the tunnel ovlan id.
- * A value of 0 will mask the corresponding bit from
- * compare.
+ * When this bit is '1', the VNIC is configured to
+ * use regular placement algorithm.
*/
- uint16_t t_l2_ovlan_mask;
- /* This value sets VLAN ID value for tunnel inner VLAN. */
- uint16_t t_l2_ivlan;
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
+ UINT32_C(0x1)
/*
- * This value sets the mask value for the tunnel ivlan id.
- * A value of 0 will mask the corresponding bit from
- * compare.
+ * When this bit is '1', the VNIC is configured to
+ * use the jumbo placement algorithm.
*/
- uint16_t t_l2_ivlan_mask;
- /* This value identifies the type of source of the packet. */
- uint8_t src_type;
- /* Network port */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
- /* Physical function */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
- /* Virtual function */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
- /* Virtual NIC of a function */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
- /* Embedded processor for CFA management */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
- /* Embedded processor for OOB management */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
- /* Embedded processor for RoCE */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
- /* Embedded processor for network proxy functions */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
- HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
- uint8_t unused_3;
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
+ UINT32_C(0x2)
/*
- * This value is the id of the source.
- * For a network port, it represents port_id.
- * For a physical function, it represents fid.
- * For a virtual function, it represents vf_id.
- * For a vnic, it represents vnic_id.
- * For embedded processors, this id is not valid.
- *
- * Notes:
- * 1. The function ID is implied if it src_id is
- * not provided for a src_type that is either
+ * When this bit is '1', the VNIC is configured
+ * to enable Header-Data split for IPv4 packets.
*/
- uint32_t src_id;
- /* Tunnel Type. */
- uint8_t tunnel_type;
- /* Non-tunnel */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
- UINT32_C(0x0)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
- UINT32_C(0x1)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
- UINT32_C(0x2)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
- UINT32_C(0x3)
- /* IP in IP */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
UINT32_C(0x4)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
- UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
- UINT32_C(0x6)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
- UINT32_C(0x7)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ /*
+ * When this bit is '1', the VNIC is configured
+ * to enable Header-Data split for IPv6 packets.
+ */
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
UINT32_C(0x8)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
- UINT32_C(0x9)
- /* Any tunneled traffic */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
- UINT32_C(0xff)
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
- uint8_t unused_4;
/*
- * If set, this value shall represent the
- * Logical VNIC ID of the destination VNIC for the RX
- * path and network port id of the destination port for
- * the TX path.
+ * When this bit is '1', the VNIC is configured
+ * to enable Header-Data split for FCoE packets.
*/
- uint16_t dst_id;
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
+ UINT32_C(0x10)
/*
- * Logical VNIC ID of the VNIC where traffic is
- * mirrored.
+ * When this bit is '1', the VNIC is configured
+ * to enable Header-Data split for RoCE packets.
*/
- uint16_t mirror_vnic_id;
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
+ UINT32_C(0x20)
/*
- * This hint is provided to help in placing
- * the filter in the filter table.
+ * When this bit is '1', the VNIC is configured
+ * to be the default VNIC of the requesting function.
*/
- uint8_t pri_hint;
- /* No preference */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
- UINT32_C(0x0)
- /* Above the given filter */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
- UINT32_C(0x1)
- /* Below the given filter */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
- UINT32_C(0x2)
- /* As high as possible */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
- UINT32_C(0x3)
- /* As low as possible */
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
- UINT32_C(0x4)
- #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
- HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
- uint8_t unused_5;
- uint32_t unused_6;
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
+ UINT32_C(0x40)
/*
- * This is the ID of the filter that goes along with
- * the pri_hint.
- *
- * This field is valid only for the following values.
- * 1 - Above the given filter
- * 2 - Below the given filter
+ * When jumbo placement algorithm is enabled, this value
+ * is used to determine the threshold for jumbo placement.
+ * Packets with length larger than this value will be
+ * placed according to the jumbo placement algorithm.
*/
- uint64_t l2_filter_id_hint;
-} __attribute__((packed));
-
-/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
-struct hwrm_cfa_l2_filter_alloc_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
+ uint16_t jumbo_thresh;
/*
- * This value identifies a set of CFA data structures used for an L2
- * context.
+ * This value is used to determine the offset into
+ * packet buffer where the split data (payload) will be
+ * placed according to one of of HDS placement algorithm.
+ *
+ * The lengths of packet buffers provided for split data
+ * shall be larger than this value.
*/
- uint64_t l2_filter_id;
+ uint16_t hds_offset;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * When one of the HDS placement algorithm is enabled, this
+ * value is used to determine the threshold for HDS
+ * placement.
+ * Packets with length larger than this value will be
+ * placed according to the HDS placement algorithm.
+ * This value shall be in multiple of 4 bytes.
*/
- uint32_t flow_id;
- uint8_t unused_0[3];
+ uint16_t hds_threshold;
+ uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/***************************
- * hwrm_cfa_l2_filter_free *
- ***************************/
+/**********************************
+ * hwrm_vnic_rss_cos_lb_ctx_alloc *
+ **********************************/
-/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
-struct hwrm_cfa_l2_filter_free_input {
+/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
+struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * This value identifies a set of CFA data structures used for an L2
- * context.
- */
- uint64_t l2_filter_id;
} __attribute__((packed));
-/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
-struct hwrm_cfa_l2_filter_free_output {
+/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
+struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /* rss_cos_lb_ctx_id is 16 b */
+ uint16_t rss_cos_lb_ctx_id;
+ uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/**************************
- * hwrm_cfa_l2_filter_cfg *
- **************************/
+/*********************************
+ * hwrm_vnic_rss_cos_lb_ctx_free *
+ *********************************/
-/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
-struct hwrm_cfa_l2_filter_cfg_input {
+/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
+struct hwrm_vnic_rss_cos_lb_ctx_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /*
- * Enumeration denoting the RX, TX type of the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
- */
- #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
- /* tx path */
- #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* rx path */
- #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP UINT32_C(0x2)
- uint32_t enables;
- /*
- * This bit must be '1' for the dst_id field to be
- * configured.
- */
- #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
- UINT32_C(0x1)
- /*
- * This bit must be '1' for the new_mirror_vnic_id field to be
- * configured.
- */
- #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
- UINT32_C(0x2)
- /*
- * This value identifies a set of CFA data structures used for an L2
- * context.
- */
- uint64_t l2_filter_id;
- /*
- * If set, this value shall represent the
- * Logical VNIC ID of the destination VNIC for the RX
- * path and network port id of the destination port for
- * the TX path.
- */
- uint32_t dst_id;
- /*
- * New Logical VNIC ID of the VNIC where traffic is
- * mirrored.
- */
- uint32_t new_mirror_vnic_id;
+ /* rss_cos_lb_ctx_id is 16 b */
+ uint16_t rss_cos_lb_ctx_id;
+ uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
-struct hwrm_cfa_l2_filter_cfg_output {
+/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
+struct hwrm_vnic_rss_cos_lb_ctx_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/***************************
- * hwrm_cfa_l2_set_rx_mask *
- ***************************/
+/*******************
+ * hwrm_ring_alloc *
+ *******************/
-/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
-struct hwrm_cfa_l2_set_rx_mask_input {
+/* hwrm_ring_alloc_input (size:704b/88B) */
+struct hwrm_ring_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* VNIC ID */
- uint32_t vnic_id;
- uint32_t mask;
+ uint32_t enables;
/*
- * When this bit is '1', the function is requested to accept
- * multi-cast packets specified by the multicast addr table.
+ * This bit must be '1' for the ring_arb_cfg field to be
+ * configured.
*/
- #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
UINT32_C(0x2)
/*
- * When this bit is '1', the function is requested to accept
- * all multi-cast packets.
+ * This bit must be '1' for the stat_ctx_id_valid field to be
+ * configured.
*/
- #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
- UINT32_C(0x4)
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
+ UINT32_C(0x8)
/*
- * When this bit is '1', the function is requested to accept
- * broadcast packets.
+ * This bit must be '1' for the max_bw_valid field to be
+ * configured.
+ */
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the rx_ring_id field to be
+ * configured.
+ */
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the nq_ring_id field to be
+ * configured.
+ */
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
+ UINT32_C(0x80)
+ /*
+ * This bit must be '1' for the rx_buf_size field to be
+ * configured.
+ */
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
+ UINT32_C(0x100)
+ /* Ring Type. */
+ uint8_t ring_type;
+ /* L2 Completion Ring (CR) */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
+ /* TX Ring (TR) */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
+ /* RX Ring (RR) */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
+ /* RoCE Notification Completion Ring (ROCE_CR) */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
+ /* RX Aggregation Ring */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
+ /* Notification Queue */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
+ HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
+ uint8_t unused_0;
+ /* Ring allocation flags. */
+ uint16_t flags;
+ /*
+ * For Rx rings, the incoming packet data can be placed at either
+ * a 0B or 2B offset from the start of the Rx packet buffer. When
+ * '1', the received packet will be padded with 2B of zeros at the
+ * front of the packet. Note that this flag is only used for
+ * Rx rings and is ignored for all other rings included Rx
+ * Aggregation rings.
+ */
+ #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
+ /*
+ * This value is a pointer to the page table for the
+ * Ring.
+ */
+ uint64_t page_tbl_addr;
+ /* First Byte Offset of the first entry in the first page. */
+ uint32_t fbo;
+ /*
+ * Actual page size in 2^page_size. The supported range is increments
+ * in powers of 2 from 16 bytes to 1GB.
+ * - 4 = 16 B
+ * Page size is 16 B.
+ * - 12 = 4 KB
+ * Page size is 4 KB.
+ * - 13 = 8 KB
+ * Page size is 8 KB.
+ * - 16 = 64 KB
+ * Page size is 64 KB.
+ * - 21 = 2 MB
+ * Page size is 2 MB.
+ * - 22 = 4 MB
+ * Page size is 4 MB.
+ * - 30 = 1 GB
+ * Page size is 1 GB.
+ */
+ uint8_t page_size;
+ /*
+ * This value indicates the depth of page table.
+ * For this version of the specification, value other than 0 or
+ * 1 shall be considered as an invalid value.
+ * When the page_tbl_depth = 0, then it is treated as a
+ * special case with the following.
+ * 1. FBO and page size fields are not valid.
+ * 2. page_tbl_addr is the physical address of the first
+ * element of the ring.
+ */
+ uint8_t page_tbl_depth;
+ uint8_t unused_1[2];
+ /*
+ * Number of 16B units in the ring. Minimum size for
+ * a ring is 16 16B entries.
+ */
+ uint32_t length;
+ /*
+ * Logical ring number for the ring to be allocated.
+ * This value determines the position in the doorbell
+ * area where the update to the ring will be made.
+ *
+ * For completion rings, this value is also the MSI-X
+ * vector number for the function the completion ring is
+ * associated with.
+ */
+ uint16_t logical_id;
+ /*
+ * This field is used only when ring_type is a TX ring.
+ * This value indicates what completion ring the TX ring
+ * is associated with.
+ */
+ uint16_t cmpl_ring_id;
+ /*
+ * This field is used only when ring_type is a TX ring.
+ * This value indicates what CoS queue the TX ring
+ * is associated with.
+ */
+ uint16_t queue_id;
+ /*
+ * When allocating a Rx ring or Rx aggregation ring, this field
+ * specifies the size of the buffer descriptors posted to the ring.
+ */
+ uint16_t rx_buf_size;
+ /*
+ * When allocating an Rx aggregation ring, this field
+ * specifies the associated Rx ring ID.
+ */
+ uint16_t rx_ring_id;
+ /*
+ * When allocating a completion ring, this field
+ * specifies the associated NQ ring ID.
+ */
+ uint16_t nq_ring_id;
+ /*
+ * This field is used only when ring_type is a TX ring.
+ * This field is used to configure arbitration related
+ * parameters for a TX ring.
+ */
+ uint16_t ring_arb_cfg;
+ /* Arbitration policy used for the ring. */
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
+ UINT32_C(0xf)
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
+ /*
+ * Use strict priority for the TX ring.
+ * Priority value is specified in arb_policy_param
*/
- #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
- UINT32_C(0x8)
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
+ UINT32_C(0x1)
/*
- * When this bit is '1', the function is requested to be
- * put in the promiscuous mode.
- *
- * The HWRM should accept any function to set up
- * promiscuous mode.
- *
- * The HWRM shall follow the semantics below for the
- * promiscuous mode support.
- * # When partitioning is not enabled on a port
- * (i.e. single PF on the port), then the PF shall
- * be allowed to be in the promiscuous mode. When the
- * PF is in the promiscuous mode, then it shall
- * receive all host bound traffic on that port.
- * # When partitioning is enabled on a port
- * (i.e. multiple PFs per port) and a PF on that
- * port is in the promiscuous mode, then the PF
- * receives all traffic within that partition as
- * identified by a unique identifier for the
- * PF (e.g. S-Tag). If a unique outer VLAN
- * for the PF is specified, then the setting of
- * promiscuous mode on that PF shall result in the
- * PF receiving all host bound traffic with matching
- * outer VLAN.
- * # A VF shall can be set in the promiscuous mode.
- * In the promiscuous mode, the VF does not receive any
- * traffic unless a unique outer VLAN for the
- * VF is specified. If a unique outer VLAN
- * for the VF is specified, then the setting of
- * promiscuous mode on that VF shall result in the
- * VF receiving all host bound traffic with the
- * matching outer VLAN.
- * # The HWRM shall allow the setting of promiscuous
- * mode on a function independently from the
- * promiscuous mode settings on other functions.
+ * Use weighted fair queue arbitration for the TX ring.
+ * Weight is specified in arb_policy_param
*/
- #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
- UINT32_C(0x10)
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
+ UINT32_C(0x2)
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
+ HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
+ /* Reserved field. */
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
/*
- * If this flag is set, the corresponding RX
- * filters shall be set up to cover multicast/broadcast
- * filters for the outermost Layer 2 destination MAC
- * address field.
+ * Arbitration policy specific parameter.
+ * # For strict priority arbitration policy, this field
+ * represents a priority value. If set to 0, then the priority
+ * is not specified and the HWRM is allowed to select
+ * any priority for this TX ring.
+ * # For weighted fair queue arbitration policy, this field
+ * represents a weight value. If set to 0, then the weight
+ * is not specified and the HWRM is allowed to select
+ * any weight for this TX ring.
*/
- #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
- UINT32_C(0x20)
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
+ uint16_t unused_3;
/*
- * If this flag is set, the corresponding RX
- * filters shall be set up to cover multicast/broadcast
- * filters for the VLAN-tagged packets that match the
- * TPID and VID fields of VLAN tags in the VLAN tag
- * table specified in this command.
+ * This field is reserved for the future use.
+ * It shall be set to 0.
*/
- #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
- UINT32_C(0x40)
+ uint32_t reserved3;
/*
- * If this flag is set, the corresponding RX
- * filters shall be set up to cover multicast/broadcast
- * filters for non-VLAN tagged packets and VLAN-tagged
- * packets that match the TPID and VID fields of VLAN
- * tags in the VLAN tag table specified in this command.
+ * This field is used only when ring_type is a TX ring.
+ * This input indicates what statistics context this ring
+ * should be associated with.
*/
- #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
- UINT32_C(0x80)
+ uint32_t stat_ctx_id;
/*
- * If this flag is set, the corresponding RX
- * filters shall be set up to cover multicast/broadcast
- * filters for non-VLAN tagged packets and VLAN-tagged
- * packets matching any VLAN tag.
- *
- * If this flag is set, then the HWRM shall ignore
- * VLAN tags specified in vlan_tag_tbl.
- *
- * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
- * flags is set, then the HWRM shall ignore
- * VLAN tags specified in vlan_tag_tbl.
- *
- * The HWRM client shall set at most one flag out of
- * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
+ * This field is reserved for the future use.
+ * It shall be set to 0.
*/
- #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
- UINT32_C(0x100)
- /* This is the address for mcast address tbl. */
- uint64_t mc_tbl_addr;
+ uint32_t reserved4;
/*
- * This value indicates how many entries in mc_tbl are valid.
- * Each entry is 6 bytes.
+ * This field is used only when ring_type is a TX ring
+ * to specify maximum BW allocated to the TX ring.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this ring inside the device.
*/
- uint32_t num_mc_entries;
- uint8_t unused_0[4];
+ uint32_t max_bw;
+ /* The bandwidth value. */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
+ HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
/*
- * This is the address for VLAN tag table.
- * Each VLAN entry in the table is 4 bytes of a VLAN tag
- * including TPID, PCP, DEI, and VID fields in network byte
- * order.
+ * This field is used only when ring_type is a Completion ring.
+ * This value indicates what interrupt mode should be used
+ * on this completion ring.
+ * Note: In the legacy interrupt mode, no more than 16
+ * completion rings are allowed.
*/
- uint64_t vlan_tag_tbl_addr;
+ uint8_t int_mode;
+ /* Legacy INTA */
+ #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
+ /* Reserved */
+ #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
+ /* MSI-X */
+ #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
+ /* No Interrupt - Polled mode */
+ #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
+ #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
+ HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
+ uint8_t unused_4[3];
/*
- * This value indicates how many entries in vlan_tag_tbl are
- * valid. Each entry is 4 bytes.
+ * The cq_handle is specified when allocating a completion ring. For
+ * devices that support NQs, this cq_handle will be included in the
+ * NQE to specify which CQ should be read to retrieve the completion
+ * record.
*/
- uint32_t num_vlan_tags;
- uint8_t unused_1[4];
+ uint64_t cq_handle;
} __attribute__((packed));
-/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
-struct hwrm_cfa_l2_set_rx_mask_output {
+/* hwrm_ring_alloc_output (size:128b/16B) */
+struct hwrm_ring_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /*
+ * Physical number of ring allocated.
+ * This value shall be unique for a ring type.
+ */
+ uint16_t ring_id;
+ /* Logical number of ring allocated. */
+ uint16_t logical_ring_id;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
-struct hwrm_cfa_l2_set_rx_mask_cmd_err {
- /*
- * command specific error codes that goes to
- * the cmd_err field in Common HWRM Error Response.
- */
- uint8_t code;
- /* Unknown error */
- #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
- UINT32_C(0x0)
- /* Unable to complete operation due to conflict with Ntuple Filter */
- #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
- UINT32_C(0x1)
- #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
- HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
- uint8_t unused_0[7];
-} __attribute__((packed));
-
-/*******************************
- * hwrm_cfa_vlan_antispoof_cfg *
- *******************************/
+/******************
+ * hwrm_ring_free *
+ ******************/
-/* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
-struct hwrm_cfa_vlan_antispoof_cfg_input {
+/* hwrm_ring_free_input (size:192b/24B) */
+struct hwrm_ring_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * Function ID of the function that is being configured.
- * Only valid for a VF FID configured by the PF.
- */
- uint16_t fid;
- uint8_t unused_0[2];
- /* Number of VLAN entries in the vlan_tag_mask_tbl. */
- uint32_t num_vlan_entries;
- /*
- * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
- * antispoof table. Each table entry contains the 16-bit TPID
- * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
- * all in network order to match hwrm_cfa_l2_set_rx_mask.
- * For an individual VLAN entry, the mask value should be 0xfff
- * for the 12-bit VLAN ID.
- */
- uint64_t vlan_tag_mask_tbl_addr;
+ /* Ring Type. */
+ uint8_t ring_type;
+ /* L2 Completion Ring (CR) */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
+ /* TX Ring (TR) */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
+ /* RX Ring (RR) */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
+ /* RoCE Notification Completion Ring (ROCE_CR) */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
+ /* RX Aggregation Ring */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
+ /* Notification Queue */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
+ HWRM_RING_FREE_INPUT_RING_TYPE_NQ
+ uint8_t unused_0;
+ /* Physical number of ring allocated. */
+ uint16_t ring_id;
+ uint8_t unused_1[4];
} __attribute__((packed));
-/* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
-struct hwrm_cfa_vlan_antispoof_cfg_output {
+/* hwrm_ring_free_output (size:128b/16B) */
+struct hwrm_ring_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/********************************
- * hwrm_cfa_vlan_antispoof_qcfg *
- ********************************/
+/*******************
+ * hwrm_ring_reset *
+ *******************/
-/* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
-struct hwrm_cfa_vlan_antispoof_qcfg_input {
+/* hwrm_ring_reset_input (size:192b/24B) */
+struct hwrm_ring_reset_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * Function ID of the function that is being queried.
- * Only valid for a VF FID queried by the PF.
- */
- uint16_t fid;
- uint8_t unused_0[2];
- /*
- * Maximum number of VLAN entries the firmware is allowed to DMA
- * to vlan_tag_mask_tbl.
- */
- uint32_t max_vlan_entries;
- /*
- * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
- * antispoof table to which firmware will DMA to. Each table
- * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
- * 16-bit VLAN ID, and a 16-bit mask, all in network order to
- * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
- * the mask value should be 0xfff for the 12-bit VLAN ID.
- */
- uint64_t vlan_tag_mask_tbl_addr;
+ /* Ring Type. */
+ uint8_t ring_type;
+ /* L2 Completion Ring (CR) */
+ #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
+ /* TX Ring (TR) */
+ #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
+ /* RX Ring (RR) */
+ #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
+ /* RoCE Notification Completion Ring (ROCE_CR) */
+ #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
+ #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
+ HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL
+ uint8_t unused_0;
+ /* Physical number of the ring. */
+ uint16_t ring_id;
+ uint8_t unused_1[4];
} __attribute__((packed));
-/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
-struct hwrm_cfa_vlan_antispoof_qcfg_output {
+/* hwrm_ring_reset_output (size:128b/16B) */
+struct hwrm_ring_reset_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
- uint32_t num_vlan_entries;
- uint8_t unused_0[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/********************************
- * hwrm_cfa_tunnel_filter_alloc *
- ********************************/
+/**************************
+ * hwrm_ring_aggint_qcaps *
+ **************************/
-/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
-struct hwrm_cfa_tunnel_filter_alloc_input {
+/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
+struct hwrm_ring_aggint_qcaps_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* Setting of this flag indicates the applicability to the loopback path. */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
- UINT32_C(0x1)
- uint32_t enables;
+} __attribute__((packed));
+
+/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
+struct hwrm_ring_aggint_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t cmpl_params;
/*
- * This bit must be '1' for the l2_filter_id field to be
- * configured.
+ * When this bit is set to '1', int_lat_tmr_min can be configured
+ * on completion rings.
*/
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
UINT32_C(0x1)
/*
- * This bit must be '1' for the l2_addr field to be
- * configured.
+ * When this bit is set to '1', int_lat_tmr_max can be configured
+ * on completion rings.
*/
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
UINT32_C(0x2)
/*
- * This bit must be '1' for the l2_ivlan field to be
- * configured.
+ * When this bit is set to '1', timer_reset can be enabled
+ * on completion rings.
*/
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
UINT32_C(0x4)
/*
- * This bit must be '1' for the l3_addr field to be
- * configured.
+ * When this bit is set to '1', ring_idle can be enabled
+ * on completion rings.
*/
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
UINT32_C(0x8)
/*
- * This bit must be '1' for the l3_addr_type field to be
- * configured.
+ * When this bit is set to '1', num_cmpl_dma_aggr can be configured
+ * on completion rings.
*/
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
UINT32_C(0x10)
/*
- * This bit must be '1' for the t_l3_addr_type field to be
- * configured.
+ * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
+ * on completion rings.
*/
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
UINT32_C(0x20)
/*
- * This bit must be '1' for the t_l3_addr field to be
- * configured.
+ * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
+ * on completion rings.
*/
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
UINT32_C(0x40)
- /*
- * This bit must be '1' for the tunnel_type field to be
- * configured.
- */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
- UINT32_C(0x80)
- /*
- * This bit must be '1' for the vni field to be
- * configured.
- */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
- UINT32_C(0x100)
- /*
- * This bit must be '1' for the dst_vnic_id field to be
- * configured.
- */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
- UINT32_C(0x200)
- /*
- * This bit must be '1' for the mirror_vnic_id field to be
- * configured.
- */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
- UINT32_C(0x400)
- /*
- * This value identifies a set of CFA data structures used for an L2
- * context.
- */
- uint64_t l2_filter_id;
- /*
- * This value sets the match value for the inner L2
- * MAC address.
- * Destination MAC address for RX path.
- * Source MAC address for TX path.
- */
- uint8_t l2_addr[6];
- /*
- * This value sets VLAN ID value for inner VLAN.
- * Only 12-bits of VLAN ID are used in setting the filter.
- */
- uint16_t l2_ivlan;
- /*
- * The value of inner destination IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
- */
- uint32_t l3_addr[4];
- /*
- * The value of tunnel destination IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
- */
- uint32_t t_l3_addr[4];
- /*
- * This value indicates the type of inner IP address.
- * 4 - IPv4
- * 6 - IPv6
- * All others are invalid.
- */
- uint8_t l3_addr_type;
- /*
- * This value indicates the type of tunnel IP address.
- * 4 - IPv4
- * 6 - IPv6
- * All others are invalid.
- */
- uint8_t t_l3_addr_type;
- /* Tunnel Type. */
- uint8_t tunnel_type;
- /* Non-tunnel */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
- UINT32_C(0x0)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
- UINT32_C(0x1)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
- UINT32_C(0x2)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
- UINT32_C(0x3)
- /* IP in IP */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
- UINT32_C(0x4)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
- UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
- UINT32_C(0x6)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
- UINT32_C(0x7)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
- UINT32_C(0x8)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
- UINT32_C(0x9)
- /* Any tunneled traffic */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
- UINT32_C(0xff)
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
- /*
- * tunnel_flags allows the user to indicate the tunnel tag detection
- * for the tunnel type specified in tunnel_type.
- */
- uint8_t tunnel_flags;
- /*
- * If the tunnel_type is geneve, then this bit indicates if we
- * need to match the geneve OAM packet.
- * If the tunnel_type is nvgre or gre, then this bit indicates if
- * we need to detect checksum present bit in geneve header.
- * If the tunnel_type is mpls, then this bit indicates if we need
- * to match mpls packet with explicit IPV4/IPV6 null header.
- */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
- UINT32_C(0x1)
- /*
- * If the tunnel_type is geneve, then this bit indicates if we
- * need to detect the critical option bit set in the oam packet.
- * If the tunnel_type is nvgre or gre, then this bit indicates
- * if we need to match nvgre packets with key present bit set in
- * gre header.
- * If the tunnel_type is mpls, then this bit indicates if we
- * need to match mpls packet with S bit from inner/second label.
- */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
- UINT32_C(0x2)
- /*
- * If the tunnel_type is geneve, then this bit indicates if we
- * need to match geneve packet with extended header bit set in
- * geneve header.
- * If the tunnel_type is nvgre or gre, then this bit indicates
- * if we need to match nvgre packets with sequence number
- * present bit set in gre header.
- * If the tunnel_type is mpls, then this bit indicates if we
- * need to match mpls packet with S bit from out/first label.
- */
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
- UINT32_C(0x4)
- /*
- * Virtual Network Identifier (VNI). Only valid with
- * tunnel_types VXLAN, NVGRE, and Geneve.
- * Only lower 24-bits of VNI field are used
- * in setting up the filter.
+ /*
+ * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
+ * on completion rings.
*/
- uint32_t vni;
- /* Logical VNIC ID of the destination VNIC. */
- uint32_t dst_vnic_id;
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
+ UINT32_C(0x80)
/*
- * Logical VNIC ID of the VNIC where traffic is
- * mirrored.
+ * When this bit is set to '1', num_cmpl_aggr_int can be configured
+ * on completion rings.
*/
- uint32_t mirror_vnic_id;
-} __attribute__((packed));
-
-/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
-struct hwrm_cfa_tunnel_filter_alloc_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* This value is an opaque id into CFA data structures. */
- uint64_t tunnel_filter_id;
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
+ UINT32_C(0x100)
+ uint32_t nq_params;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * When this bit is set to '1', int_lat_tmr_min can be configured
+ * on notification queues.
*/
- uint32_t flow_id;
- uint8_t unused_0[3];
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
+ UINT32_C(0x1)
+ /* Minimum value for num_cmpl_dma_aggr */
+ uint16_t num_cmpl_dma_aggr_min;
+ /* Maximum value for num_cmpl_dma_aggr */
+ uint16_t num_cmpl_dma_aggr_max;
+ /* Minimum value for num_cmpl_dma_aggr_during_int */
+ uint16_t num_cmpl_dma_aggr_during_int_min;
+ /* Maximum value for num_cmpl_dma_aggr_during_int */
+ uint16_t num_cmpl_dma_aggr_during_int_max;
+ /* Minimum value for cmpl_aggr_dma_tmr */
+ uint16_t cmpl_aggr_dma_tmr_min;
+ /* Maximum value for cmpl_aggr_dma_tmr */
+ uint16_t cmpl_aggr_dma_tmr_max;
+ /* Minimum value for cmpl_aggr_dma_tmr_during_int */
+ uint16_t cmpl_aggr_dma_tmr_during_int_min;
+ /* Maximum value for cmpl_aggr_dma_tmr_during_int */
+ uint16_t cmpl_aggr_dma_tmr_during_int_max;
+ /* Minimum value for int_lat_tmr_min */
+ uint16_t int_lat_tmr_min_min;
+ /* Maximum value for int_lat_tmr_min */
+ uint16_t int_lat_tmr_min_max;
+ /* Minimum value for int_lat_tmr_max */
+ uint16_t int_lat_tmr_max_min;
+ /* Maximum value for int_lat_tmr_max */
+ uint16_t int_lat_tmr_max_max;
+ /* Minimum value for num_cmpl_aggr_int */
+ uint16_t num_cmpl_aggr_int_min;
+ /* Maximum value for num_cmpl_aggr_int */
+ uint16_t num_cmpl_aggr_int_max;
+ /* The units for timer parameters, in nanoseconds. */
+ uint16_t timer_units;
+ uint8_t unused_0[1];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_cfa_tunnel_filter_free *
- *******************************/
+/**************************************
+ * hwrm_ring_cmpl_ring_qaggint_params *
+ **************************************/
-/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
-struct hwrm_cfa_tunnel_filter_free_input {
+/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
+struct hwrm_ring_cmpl_ring_qaggint_params_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* This value is an opaque id into CFA data structures. */
- uint64_t tunnel_filter_id;
+ /* Physical number of completion ring. */
+ uint16_t ring_id;
+ uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
-struct hwrm_cfa_tunnel_filter_free_output {
+/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
+struct hwrm_ring_cmpl_ring_qaggint_params_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ uint16_t flags;
+ /*
+ * When this bit is set to '1', interrupt max
+ * timer is reset whenever a completion is received.
+ */
+ #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
+ UINT32_C(0x1)
+ /*
+ * When this bit is set to '1', ring idle mode
+ * aggregation will be enabled.
+ */
+ #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
+ UINT32_C(0x2)
+ /*
+ * Number of completions to aggregate before DMA
+ * during the normal mode.
+ */
+ uint16_t num_cmpl_dma_aggr;
+ /*
+ * Number of completions to aggregate before DMA
+ * during the interrupt mode.
+ */
+ uint16_t num_cmpl_dma_aggr_during_int;
+ /*
+ * Timer in unit of 80-nsec used to aggregate completions before
+ * DMA during the normal mode (not in interrupt mode).
+ */
+ uint16_t cmpl_aggr_dma_tmr;
+ /*
+ * Timer in unit of 80-nsec used to aggregate completions before
+ * DMA during the interrupt mode.
+ */
+ uint16_t cmpl_aggr_dma_tmr_during_int;
+ /* Minimum time (in unit of 80-nsec) between two interrupts. */
+ uint16_t int_lat_tmr_min;
+ /*
+ * Maximum wait time (in unit of 80-nsec) spent aggregating
+ * completions before signaling the interrupt after the
+ * interrupt is enabled.
+ */
+ uint16_t int_lat_tmr_max;
+ /*
+ * Minimum number of completions aggregated before signaling
+ * an interrupt.
+ */
+ uint16_t num_cmpl_aggr_int;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
uint8_t valid;
} __attribute__((packed));
-/***************************************
- * hwrm_cfa_redirect_tunnel_type_alloc *
- ***************************************/
+/*****************************************
+ * hwrm_ring_cmpl_ring_cfg_aggint_params *
+ *****************************************/
-/* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
-struct hwrm_cfa_redirect_tunnel_type_alloc_input {
+/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
+struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* The destination function id, to whom the traffic is redirected. */
- uint16_t dest_fid;
- /* Tunnel Type. */
- uint8_t tunnel_type;
- /* Non-tunnel */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
- UINT32_C(0x0)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ /* Physical number of completion ring. */
+ uint16_t ring_id;
+ uint16_t flags;
+ /*
+ * When this bit is set to '1', interrupt latency max
+ * timer is reset whenever a completion is received.
+ */
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
UINT32_C(0x1)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ /*
+ * When this bit is set to '1', ring idle mode
+ * aggregation will be enabled.
+ */
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
UINT32_C(0x2)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
- UINT32_C(0x3)
- /* IP in IP */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ /*
+ * Set this flag to 1 when configuring parameters on a
+ * notification queue. Set this flag to 0 when configuring
+ * parameters on a completion queue.
+ */
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
UINT32_C(0x4)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
- UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
- UINT32_C(0x6)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
- UINT32_C(0x7)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
- UINT32_C(0x8)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
- UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
- UINT32_C(0xa)
- /* Any tunneled traffic */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
- UINT32_C(0xff)
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
- /* Tunnel alloc flags. */
- uint8_t flags;
- /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
+ /*
+ * Number of completions to aggregate before DMA
+ * during the normal mode.
+ */
+ uint16_t num_cmpl_dma_aggr;
+ /*
+ * Number of completions to aggregate before DMA
+ * during the interrupt mode.
+ */
+ uint16_t num_cmpl_dma_aggr_during_int;
+ /*
+ * Timer in unit of 80-nsec used to aggregate completions before
+ * DMA during the normal mode (not in interrupt mode).
+ */
+ uint16_t cmpl_aggr_dma_tmr;
+ /*
+ * Timer in unit of 80-nsec used to aggregate completions before
+ * DMA during the interrupt mode.
+ */
+ uint16_t cmpl_aggr_dma_tmr_during_int;
+ /* Minimum time (in unit of 80-nsec) between two interrupts. */
+ uint16_t int_lat_tmr_min;
+ /*
+ * Maximum wait time (in unit of 80-nsec) spent aggregating
+ * cmpls before signaling the interrupt after the
+ * interrupt is enabled.
+ */
+ uint16_t int_lat_tmr_max;
+ /*
+ * Minimum number of completions aggregated before signaling
+ * an interrupt.
+ */
+ uint16_t num_cmpl_aggr_int;
+ /*
+ * Bitfield that indicates which parameters are to be applied. Only
+ * required when configuring devices with notification queues, and
+ * used in that case to set certain parameters on completion queues
+ * and others on notification queues.
+ */
+ uint16_t enables;
+ /*
+ * This bit must be '1' for the num_cmpl_dma_aggr field to be
+ * configured.
+ */
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
+ * configured.
+ */
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
+ * configured.
+ */
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the int_lat_tmr_min field to be
+ * configured.
+ */
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the int_lat_tmr_max field to be
+ * configured.
+ */
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the num_cmpl_aggr_int field to be
+ * configured.
+ */
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
+ UINT32_C(0x20)
uint8_t unused_0[4];
} __attribute__((packed));
-/* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
-struct hwrm_cfa_redirect_tunnel_type_alloc_output {
+/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
+struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/**************************************
- * hwrm_cfa_redirect_tunnel_type_free *
- **************************************/
-
+/***********************
+ * hwrm_ring_grp_alloc *
+ ***********************/
-/* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
-struct hwrm_cfa_redirect_tunnel_type_free_input {
+
+/* hwrm_ring_grp_alloc_input (size:192b/24B) */
+struct hwrm_ring_grp_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* The destination function id, to whom the traffic is redirected. */
- uint16_t dest_fid;
- /* Tunnel Type. */
- uint8_t tunnel_type;
- /* Non-tunnel */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
- UINT32_C(0x0)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
- UINT32_C(0x1)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
- UINT32_C(0x2)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
- UINT32_C(0x3)
- /* IP in IP */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
- UINT32_C(0x4)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
- UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
- UINT32_C(0x6)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
- UINT32_C(0x7)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
- UINT32_C(0x8)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
- UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
- UINT32_C(0xa)
- /* Any tunneled traffic */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
- UINT32_C(0xff)
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
- uint8_t unused_0[5];
+ /*
+ * This value identifies the CR associated with the ring
+ * group.
+ */
+ uint16_t cr;
+ /*
+ * This value identifies the main RR associated with the ring
+ * group.
+ */
+ uint16_t rr;
+ /*
+ * This value identifies the aggregation RR associated with
+ * the ring group. If this value is 0xFF... (All Fs), then no
+ * Aggregation ring will be set.
+ */
+ uint16_t ar;
+ /*
+ * This value identifies the statistics context associated
+ * with the ring group.
+ */
+ uint16_t sc;
} __attribute__((packed));
-/* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
-struct hwrm_cfa_redirect_tunnel_type_free_output {
+/* hwrm_ring_grp_alloc_output (size:128b/16B) */
+struct hwrm_ring_grp_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /*
+ * This is the ring group ID value. Use this value to program
+ * the default ring group for the VNIC or as table entries
+ * in an RSS/COS context.
+ */
+ uint32_t ring_group_id;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/**************************************
- * hwrm_cfa_redirect_tunnel_type_info *
- **************************************/
+/**********************
+ * hwrm_ring_grp_free *
+ **********************/
-/* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
-struct hwrm_cfa_redirect_tunnel_type_info_input {
+/* hwrm_ring_grp_free_input (size:192b/24B) */
+struct hwrm_ring_grp_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* The source function id. */
- uint16_t src_fid;
- /* Tunnel Type. */
- uint8_t tunnel_type;
- /* Non-tunnel */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
- UINT32_C(0x0)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
- UINT32_C(0x1)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
- UINT32_C(0x2)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
- UINT32_C(0x3)
- /* IP in IP */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
- UINT32_C(0x4)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
- UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
- UINT32_C(0x6)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
- UINT32_C(0x7)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
- UINT32_C(0x8)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
- UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
- UINT32_C(0xa)
- /* Any tunneled traffic */
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
- UINT32_C(0xff)
- #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
- uint8_t unused_0[5];
-} __attribute__((packed));
-
-/* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
-struct hwrm_cfa_redirect_tunnel_type_info_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* The destination function id, to whom the traffic is redirected. */
- uint16_t dest_fid;
- uint8_t unused_0[5];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
-struct hwrm_vxlan_ipv4_hdr {
- /* IPv4 version and header length. */
- uint8_t ver_hlen;
- /* IPv4 header length */
- #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
- #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
- /* Version */
- #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
- #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
- /* IPv4 type of service. */
- uint8_t tos;
- /* IPv4 identification. */
- uint16_t ip_id;
- /* IPv4 flags and offset. */
- uint16_t flags_frag_offset;
- /* IPv4 TTL. */
- uint8_t ttl;
- /* IPv4 protocol. */
- uint8_t protocol;
- /* IPv4 source address. */
- uint32_t src_ip_addr;
- /* IPv4 destination address. */
- uint32_t dest_ip_addr;
-} __attribute__((packed));
-
-/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
-struct hwrm_vxlan_ipv6_hdr {
- /* IPv6 version, traffic class and flow label. */
- uint32_t ver_tc_flow_label;
- /* IPv6 version shift */
- #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
- UINT32_C(0x1c)
- /* IPv6 version mask */
- #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
- UINT32_C(0xf0000000)
- /* IPv6 TC shift */
- #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
- UINT32_C(0x14)
- /* IPv6 TC mask */
- #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
- UINT32_C(0xff00000)
- /* IPv6 flow label shift */
- #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
- UINT32_C(0x0)
- /* IPv6 flow label mask */
- #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
- UINT32_C(0xfffff)
- #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
- HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
- /* IPv6 payload length. */
- uint16_t payload_len;
- /* IPv6 next header. */
- uint8_t next_hdr;
- /* IPv6 TTL. */
- uint8_t ttl;
- /* IPv6 source address. */
- uint32_t src_ip_addr[4];
- /* IPv6 destination address. */
- uint32_t dest_ip_addr[4];
+ /* This is the ring group ID value. */
+ uint32_t ring_group_id;
+ uint8_t unused_0[4];
} __attribute__((packed));
-
-/* hwrm_cfa_encap_data_vxlan (size:576b/72B) */
-struct hwrm_cfa_encap_data_vxlan {
- /* Source MAC address. */
- uint8_t src_mac_addr[6];
- /* reserved. */
- uint16_t unused_0;
- /* Destination MAC address. */
- uint8_t dst_mac_addr[6];
- /* Number of VLAN tags. */
- uint8_t num_vlan_tags;
- /* reserved. */
- uint8_t unused_1;
- /* Outer VLAN TPID. */
- uint16_t ovlan_tpid;
- /* Outer VLAN TCI. */
- uint16_t ovlan_tci;
- /* Inner VLAN TPID. */
- uint16_t ivlan_tpid;
- /* Inner VLAN TCI. */
- uint16_t ivlan_tci;
- /* L3 header fields. */
- uint32_t l3[10];
- /* IP version mask. */
- #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
- /* IP version 4. */
- #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
- /* IP version 6. */
- #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
- #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
- HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
- /* UDP source port. */
- uint16_t src_port;
- /* UDP destination port. */
- uint16_t dst_port;
- /* VXLAN Network Identifier. */
- uint32_t vni;
+
+/* hwrm_ring_grp_free_output (size:128b/16B) */
+struct hwrm_ring_grp_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_cfa_encap_record_alloc *
- *******************************/
+/****************************
+ * hwrm_cfa_l2_filter_alloc *
+ ****************************/
-/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
-struct hwrm_cfa_encap_record_alloc_input {
+/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
+struct hwrm_cfa_l2_filter_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* physical address (HPA) or a guest physical address (GPA) and must
* point to a physically contiguous block of memory.
*/
- uint64_t resp_addr;
- uint32_t flags;
- /* Setting of this flag indicates the applicability to the loopback path. */
- #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
- UINT32_C(0x1)
- /* Encapsulation Type. */
- uint8_t encap_type;
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
+ UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
+ /* Setting of this flag indicates the applicability to the loopback path. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
+ UINT32_C(0x2)
+ /*
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
+ UINT32_C(0x4)
+ /*
+ * If this flag is set, all t_l2_* fields are invalid
+ * and they should not be specified.
+ * If this flag is set, then l2_* fields refer to
+ * fields of outermost L2 header.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
+ UINT32_C(0x8)
+ /*
+ * Enumeration denoting NO_ROCE_L2 to support old drivers.
+ * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
+ UINT32_C(0x30)
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
+ /* To support old drivers */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
+ (UINT32_C(0x0) << 4)
+ /* Only L2 traffic */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
+ (UINT32_C(0x1) << 4)
+ /* Roce & L2 traffic */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
+ (UINT32_C(0x2) << 4)
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the l2_addr field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the l2_addr_mask field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the l2_ovlan field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the l2_ovlan_mask field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the l2_ivlan field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the l2_ivlan_mask field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the t_l2_addr field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the t_l2_addr_mask field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
+ UINT32_C(0x80)
+ /*
+ * This bit must be '1' for the t_l2_ovlan field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
+ UINT32_C(0x100)
+ /*
+ * This bit must be '1' for the t_l2_ovlan_mask field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
+ UINT32_C(0x200)
+ /*
+ * This bit must be '1' for the t_l2_ivlan field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
+ UINT32_C(0x400)
+ /*
+ * This bit must be '1' for the t_l2_ivlan_mask field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
+ UINT32_C(0x800)
+ /*
+ * This bit must be '1' for the src_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
+ UINT32_C(0x1000)
+ /*
+ * This bit must be '1' for the src_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
+ UINT32_C(0x2000)
+ /*
+ * This bit must be '1' for the tunnel_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ UINT32_C(0x4000)
+ /*
+ * This bit must be '1' for the dst_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
+ UINT32_C(0x8000)
+ /*
+ * This bit must be '1' for the mirror_vnic_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
+ UINT32_C(0x10000)
+ /*
+ * This value sets the match value for the L2 MAC address.
+ * Destination MAC address for RX path.
+ * Source MAC address for TX path.
+ */
+ uint8_t l2_addr[6];
+ uint8_t unused_0[2];
+ /*
+ * This value sets the mask value for the L2 address.
+ * A value of 0 will mask the corresponding bit from
+ * compare.
+ */
+ uint8_t l2_addr_mask[6];
+ /* This value sets VLAN ID value for outer VLAN. */
+ uint16_t l2_ovlan;
+ /*
+ * This value sets the mask value for the ovlan id.
+ * A value of 0 will mask the corresponding bit from
+ * compare.
+ */
+ uint16_t l2_ovlan_mask;
+ /* This value sets VLAN ID value for inner VLAN. */
+ uint16_t l2_ivlan;
+ /*
+ * This value sets the mask value for the ivlan id.
+ * A value of 0 will mask the corresponding bit from
+ * compare.
+ */
+ uint16_t l2_ivlan_mask;
+ uint8_t unused_1[2];
+ /*
+ * This value sets the match value for the tunnel
+ * L2 MAC address.
+ * Destination MAC address for RX path.
+ * Source MAC address for TX path.
+ */
+ uint8_t t_l2_addr[6];
+ uint8_t unused_2[2];
+ /*
+ * This value sets the mask value for the tunnel L2
+ * address.
+ * A value of 0 will mask the corresponding bit from
+ * compare.
+ */
+ uint8_t t_l2_addr_mask[6];
+ /* This value sets VLAN ID value for tunnel outer VLAN. */
+ uint16_t t_l2_ovlan;
+ /*
+ * This value sets the mask value for the tunnel ovlan id.
+ * A value of 0 will mask the corresponding bit from
+ * compare.
+ */
+ uint16_t t_l2_ovlan_mask;
+ /* This value sets VLAN ID value for tunnel inner VLAN. */
+ uint16_t t_l2_ivlan;
+ /*
+ * This value sets the mask value for the tunnel ivlan id.
+ * A value of 0 will mask the corresponding bit from
+ * compare.
+ */
+ uint16_t t_l2_ivlan_mask;
+ /* This value identifies the type of source of the packet. */
+ uint8_t src_type;
+ /* Network port */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
+ /* Physical function */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
+ /* Virtual function */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
+ /* Virtual NIC of a function */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
+ /* Embedded processor for CFA management */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
+ /* Embedded processor for OOB management */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
+ /* Embedded processor for RoCE */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
+ /* Embedded processor for network proxy functions */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
+ uint8_t unused_3;
+ /*
+ * This value is the id of the source.
+ * For a network port, it represents port_id.
+ * For a physical function, it represents fid.
+ * For a virtual function, it represents vf_id.
+ * For a vnic, it represents vnic_id.
+ * For embedded processors, this id is not valid.
+ *
+ * Notes:
+ * 1. The function ID is implied if it src_id is
+ * not provided for a src_type that is either
+ */
+ uint32_t src_id;
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
/* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
UINT32_C(0x1)
/* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
UINT32_C(0x2)
- /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
- #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
UINT32_C(0x3)
/* IP in IP */
- #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
UINT32_C(0x4)
/* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
/* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
- /* VLAN */
- #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
UINT32_C(0x7)
/* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
UINT32_C(0x8)
- #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
- HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE
- uint8_t unused_0[3];
- /* This value is encap data used for the given encap type. */
- uint32_t encap_data[20];
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused_4;
+ /*
+ * If set, this value shall represent the
+ * Logical VNIC ID of the destination VNIC for the RX
+ * path and network port id of the destination port for
+ * the TX path.
+ */
+ uint16_t dst_id;
+ /*
+ * Logical VNIC ID of the VNIC where traffic is
+ * mirrored.
+ */
+ uint16_t mirror_vnic_id;
+ /*
+ * This hint is provided to help in placing
+ * the filter in the filter table.
+ */
+ uint8_t pri_hint;
+ /* No preference */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
+ UINT32_C(0x0)
+ /* Above the given filter */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
+ UINT32_C(0x1)
+ /* Below the given filter */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
+ UINT32_C(0x2)
+ /* As high as possible */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
+ UINT32_C(0x3)
+ /* As low as possible */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
+ UINT32_C(0x4)
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
+ uint8_t unused_5;
+ uint32_t unused_6;
+ /*
+ * This is the ID of the filter that goes along with
+ * the pri_hint.
+ *
+ * This field is valid only for the following values.
+ * 1 - Above the given filter
+ * 2 - Below the given filter
+ */
+ uint64_t l2_filter_id_hint;
} __attribute__((packed));
-/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
-struct hwrm_cfa_encap_record_alloc_output {
+/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
+struct hwrm_cfa_l2_filter_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* This value is an opaque id into CFA data structures. */
- uint32_t encap_record_id;
+ /*
+ * This value identifies a set of CFA data structures used for an L2
+ * context.
+ */
+ uint64_t l2_filter_id;
+ /*
+ * This is the ID of the flow associated with this
+ * filter.
+ * This value shall be used to match and associate the
+ * flow identifier returned in completion records.
+ * A value of 0xFFFFFFFF shall indicate no flow id.
+ */
+ uint32_t flow_id;
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
uint8_t valid;
} __attribute__((packed));
-/******************************
- * hwrm_cfa_encap_record_free *
- ******************************/
+/***************************
+ * hwrm_cfa_l2_filter_free *
+ ***************************/
-/* hwrm_cfa_encap_record_free_input (size:192b/24B) */
-struct hwrm_cfa_encap_record_free_input {
+/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
+struct hwrm_cfa_l2_filter_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* This value is an opaque id into CFA data structures. */
- uint32_t encap_record_id;
- uint8_t unused_0[4];
+ /*
+ * This value identifies a set of CFA data structures used for an L2
+ * context.
+ */
+ uint64_t l2_filter_id;
} __attribute__((packed));
-/* hwrm_cfa_encap_record_free_output (size:128b/16B) */
-struct hwrm_cfa_encap_record_free_output {
+/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
+struct hwrm_cfa_l2_filter_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/********************************
- * hwrm_cfa_ntuple_filter_alloc *
- ********************************/
+/**************************
+ * hwrm_cfa_l2_filter_cfg *
+ **************************/
-/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
-struct hwrm_cfa_ntuple_filter_alloc_input {
+/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
+struct hwrm_cfa_l2_filter_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
*/
uint64_t resp_addr;
uint32_t flags;
- /* Setting of this flag indicates the applicability to the loopback path. */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
- UINT32_C(0x1)
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
- UINT32_C(0x2)
- /*
- * Setting of this flag indicates that a meter is expected to be attached
- * to this flow. This hint can be used when choosing the action record
- * format required for the flow.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
- UINT32_C(0x4)
- uint32_t enables;
/*
- * This bit must be '1' for the l2_filter_id field to be
- * configured.
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
*/
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
+ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
/*
- * This bit must be '1' for the ethertype field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
- UINT32_C(0x2)
- /*
- * This bit must be '1' for the tunnel_type field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
- UINT32_C(0x4)
- /*
- * This bit must be '1' for the src_macaddr field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
- UINT32_C(0x8)
- /*
- * This bit must be '1' for the ipaddr_type field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
- UINT32_C(0x10)
- /*
- * This bit must be '1' for the src_ipaddr field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
- UINT32_C(0x20)
- /*
- * This bit must be '1' for the src_ipaddr_mask field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
- UINT32_C(0x40)
- /*
- * This bit must be '1' for the dst_ipaddr field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
- UINT32_C(0x80)
- /*
- * This bit must be '1' for the dst_ipaddr_mask field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
- UINT32_C(0x100)
- /*
- * This bit must be '1' for the ip_protocol field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
- UINT32_C(0x200)
- /*
- * This bit must be '1' for the src_port field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
- UINT32_C(0x400)
- /*
- * This bit must be '1' for the src_port_mask field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
- UINT32_C(0x800)
- /*
- * This bit must be '1' for the dst_port field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
- UINT32_C(0x1000)
- /*
- * This bit must be '1' for the dst_port_mask field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
- UINT32_C(0x2000)
- /*
- * This bit must be '1' for the pri_hint field to be
- * configured.
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
*/
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
- UINT32_C(0x4000)
+ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
+ UINT32_C(0x2)
/*
- * This bit must be '1' for the ntuple_filter_id field to be
- * configured.
+ * Enumeration denoting NO_ROCE_L2 to support old drivers.
+ * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
*/
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
- UINT32_C(0x8000)
+ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
+ UINT32_C(0xc)
+ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
+ /* To support old drivers */
+ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
+ (UINT32_C(0x0) << 2)
+ /* Only L2 traffic */
+ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
+ (UINT32_C(0x1) << 2)
+ /* Roce & L2 traffic */
+ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
+ (UINT32_C(0x2) << 2)
+ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
+ HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
+ uint32_t enables;
/*
* This bit must be '1' for the dst_id field to be
* configured.
*/
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
- UINT32_C(0x10000)
- /*
- * This bit must be '1' for the mirror_vnic_id field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
- UINT32_C(0x20000)
+ #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
+ UINT32_C(0x1)
/*
- * This bit must be '1' for the dst_macaddr field to be
+ * This bit must be '1' for the new_mirror_vnic_id field to be
* configured.
*/
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
- UINT32_C(0x40000)
+ #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
+ UINT32_C(0x2)
/*
* This value identifies a set of CFA data structures used for an L2
* context.
*/
uint64_t l2_filter_id;
/*
- * This value indicates the source MAC address in
- * the Ethernet header.
+ * If set, this value shall represent the
+ * Logical VNIC ID of the destination VNIC for the RX
+ * path and network port id of the destination port for
+ * the TX path.
*/
- uint8_t src_macaddr[6];
- /* This value indicates the ethertype in the Ethernet header. */
- uint16_t ethertype;
+ uint32_t dst_id;
/*
- * This value indicates the type of IP address.
- * 4 - IPv4
- * 6 - IPv6
- * All others are invalid.
+ * New Logical VNIC ID of the VNIC where traffic is
+ * mirrored.
*/
- uint8_t ip_addr_type;
- /* invalid */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
- UINT32_C(0x0)
- /* IPv4 */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
- UINT32_C(0x4)
- /* IPv6 */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
- UINT32_C(0x6)
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
- HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
+ uint32_t new_mirror_vnic_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
+struct hwrm_cfa_l2_filter_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * The value of protocol filed in IP header.
- * Applies to UDP and TCP traffic.
- * 6 - TCP
- * 17 - UDP
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t ip_protocol;
- /* invalid */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
- UINT32_C(0x0)
- /* TCP */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
- UINT32_C(0x6)
- /* UDP */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
- UINT32_C(0x11)
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
- HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
+ uint8_t valid;
+} __attribute__((packed));
+
+/***************************
+ * hwrm_cfa_l2_set_rx_mask *
+ ***************************/
+
+
+/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
+struct hwrm_cfa_l2_set_rx_mask_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * If set, this value shall represent the
- * Logical VNIC ID of the destination VNIC for the RX
- * path and network port id of the destination port for
- * the TX path.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t dst_id;
+ uint16_t cmpl_ring;
/*
- * Logical VNIC ID of the VNIC where traffic is
- * mirrored.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint16_t mirror_vnic_id;
+ uint16_t seq_id;
/*
- * This value indicates the tunnel type for this filter.
- * If this field is not specified, then the filter shall
- * apply to both non-tunneled and tunneled packets.
- * If this field conflicts with the tunnel_type specified
- * in the l2_filter_id, then the HWRM shall return an
- * error for this command.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint8_t tunnel_type;
- /* Non-tunnel */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
- UINT32_C(0x0)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
- UINT32_C(0x1)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
- UINT32_C(0x2)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
- UINT32_C(0x3)
- /* IP in IP */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
- UINT32_C(0x4)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
- UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
- UINT32_C(0x6)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
- UINT32_C(0x7)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
- UINT32_C(0x8)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
- UINT32_C(0x9)
- /* Any tunneled traffic */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
- UINT32_C(0xff)
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ uint16_t target_id;
/*
- * This hint is provided to help in placing
- * the filter in the filter table.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint8_t pri_hint;
- /* No preference */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
- UINT32_C(0x0)
- /* Above the given filter */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
- UINT32_C(0x1)
- /* Below the given filter */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
+ uint64_t resp_addr;
+ /* VNIC ID */
+ uint32_t vnic_id;
+ uint32_t mask;
+ /*
+ * When this bit is '1', the function is requested to accept
+ * multi-cast packets specified by the multicast addr table.
+ */
+ #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
UINT32_C(0x2)
- /* As high as possible */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
- UINT32_C(0x3)
- /* As low as possible */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
+ /*
+ * When this bit is '1', the function is requested to accept
+ * all multi-cast packets.
+ */
+ #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
UINT32_C(0x4)
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
- HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
/*
- * The value of source IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
+ * When this bit is '1', the function is requested to accept
+ * broadcast packets.
*/
- uint32_t src_ipaddr[4];
+ #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
+ UINT32_C(0x8)
/*
- * The value of source IP address mask to be used in
- * filtering.
- * For IPv4, first four bytes represent the IP address mask.
+ * When this bit is '1', the function is requested to be
+ * put in the promiscuous mode.
+ *
+ * The HWRM should accept any function to set up
+ * promiscuous mode.
+ *
+ * The HWRM shall follow the semantics below for the
+ * promiscuous mode support.
+ * # When partitioning is not enabled on a port
+ * (i.e. single PF on the port), then the PF shall
+ * be allowed to be in the promiscuous mode. When the
+ * PF is in the promiscuous mode, then it shall
+ * receive all host bound traffic on that port.
+ * # When partitioning is enabled on a port
+ * (i.e. multiple PFs per port) and a PF on that
+ * port is in the promiscuous mode, then the PF
+ * receives all traffic within that partition as
+ * identified by a unique identifier for the
+ * PF (e.g. S-Tag). If a unique outer VLAN
+ * for the PF is specified, then the setting of
+ * promiscuous mode on that PF shall result in the
+ * PF receiving all host bound traffic with matching
+ * outer VLAN.
+ * # A VF shall can be set in the promiscuous mode.
+ * In the promiscuous mode, the VF does not receive any
+ * traffic unless a unique outer VLAN for the
+ * VF is specified. If a unique outer VLAN
+ * for the VF is specified, then the setting of
+ * promiscuous mode on that VF shall result in the
+ * VF receiving all host bound traffic with the
+ * matching outer VLAN.
+ * # The HWRM shall allow the setting of promiscuous
+ * mode on a function independently from the
+ * promiscuous mode settings on other functions.
*/
- uint32_t src_ipaddr_mask[4];
+ #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
+ UINT32_C(0x10)
/*
- * The value of destination IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
+ * If this flag is set, the corresponding RX
+ * filters shall be set up to cover multicast/broadcast
+ * filters for the outermost Layer 2 destination MAC
+ * address field.
*/
- uint32_t dst_ipaddr[4];
+ #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
+ UINT32_C(0x20)
/*
- * The value of destination IP address mask to be used in
- * filtering.
- * For IPv4, first four bytes represent the IP address mask.
+ * If this flag is set, the corresponding RX
+ * filters shall be set up to cover multicast/broadcast
+ * filters for the VLAN-tagged packets that match the
+ * TPID and VID fields of VLAN tags in the VLAN tag
+ * table specified in this command.
*/
- uint32_t dst_ipaddr_mask[4];
+ #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
+ UINT32_C(0x40)
/*
- * The value of source port to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * If this flag is set, the corresponding RX
+ * filters shall be set up to cover multicast/broadcast
+ * filters for non-VLAN tagged packets and VLAN-tagged
+ * packets that match the TPID and VID fields of VLAN
+ * tags in the VLAN tag table specified in this command.
*/
- uint16_t src_port;
+ #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
+ UINT32_C(0x80)
/*
- * The value of source port mask to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * If this flag is set, the corresponding RX
+ * filters shall be set up to cover multicast/broadcast
+ * filters for non-VLAN tagged packets and VLAN-tagged
+ * packets matching any VLAN tag.
+ *
+ * If this flag is set, then the HWRM shall ignore
+ * VLAN tags specified in vlan_tag_tbl.
+ *
+ * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
+ * flags is set, then the HWRM shall ignore
+ * VLAN tags specified in vlan_tag_tbl.
+ *
+ * The HWRM client shall set at most one flag out of
+ * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
*/
- uint16_t src_port_mask;
+ #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
+ UINT32_C(0x100)
+ /* This is the address for mcast address tbl. */
+ uint64_t mc_tbl_addr;
/*
- * The value of destination port to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * This value indicates how many entries in mc_tbl are valid.
+ * Each entry is 6 bytes.
*/
- uint16_t dst_port;
+ uint32_t num_mc_entries;
+ uint8_t unused_0[4];
/*
- * The value of destination port mask to be used in
- * filtering.
- * Applies to UDP and TCP traffic.
+ * This is the address for VLAN tag table.
+ * Each VLAN entry in the table is 4 bytes of a VLAN tag
+ * including TPID, PCP, DEI, and VID fields in network byte
+ * order.
*/
- uint16_t dst_port_mask;
+ uint64_t vlan_tag_tbl_addr;
/*
- * This is the ID of the filter that goes along with
- * the pri_hint.
+ * This value indicates how many entries in vlan_tag_tbl are
+ * valid. Each entry is 4 bytes.
*/
- uint64_t ntuple_filter_id_hint;
+ uint32_t num_vlan_tags;
+ uint8_t unused_1[4];
} __attribute__((packed));
-/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
-struct hwrm_cfa_ntuple_filter_alloc_output {
+/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
+struct hwrm_cfa_l2_set_rx_mask_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* This value is an opaque id into CFA data structures. */
- uint64_t ntuple_filter_id;
- /*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
- */
- uint32_t flow_id;
- uint8_t unused_0[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
-struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
+/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
+struct hwrm_cfa_l2_set_rx_mask_cmd_err {
/*
* command specific error codes that goes to
* the cmd_err field in Common HWRM Error Response.
*/
uint8_t code;
/* Unknown error */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
+ #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
UINT32_C(0x0)
- /* Unable to complete operation due to conflict with Rx Mask VLAN */
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
+ /* Unable to complete operation due to conflict with Ntuple Filter */
+ #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
UINT32_C(0x1)
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
- HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
+ #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
+ HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
uint8_t unused_0[7];
} __attribute__((packed));
/*******************************
- * hwrm_cfa_ntuple_filter_free *
+ * hwrm_cfa_vlan_antispoof_cfg *
*******************************/
-/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
-struct hwrm_cfa_ntuple_filter_free_input {
+/* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
+struct hwrm_cfa_vlan_antispoof_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* This value is an opaque id into CFA data structures. */
- uint64_t ntuple_filter_id;
+ /*
+ * Function ID of the function that is being configured.
+ * Only valid for a VF FID configured by the PF.
+ */
+ uint16_t fid;
+ uint8_t unused_0[2];
+ /* Number of VLAN entries in the vlan_tag_mask_tbl. */
+ uint32_t num_vlan_entries;
+ /*
+ * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
+ * antispoof table. Each table entry contains the 16-bit TPID
+ * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
+ * all in network order to match hwrm_cfa_l2_set_rx_mask.
+ * For an individual VLAN entry, the mask value should be 0xfff
+ * for the 12-bit VLAN ID.
+ */
+ uint64_t vlan_tag_mask_tbl_addr;
} __attribute__((packed));
-/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
-struct hwrm_cfa_ntuple_filter_free_output {
+/* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
+struct hwrm_cfa_vlan_antispoof_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/******************************
- * hwrm_cfa_ntuple_filter_cfg *
- ******************************/
+/********************************
+ * hwrm_cfa_vlan_antispoof_qcfg *
+ ********************************/
-/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
-struct hwrm_cfa_ntuple_filter_cfg_input {
+/* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
+struct hwrm_cfa_vlan_antispoof_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
- /*
- * This bit must be '1' for the new_dst_id field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
- UINT32_C(0x1)
- /*
- * This bit must be '1' for the new_mirror_vnic_id field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
- UINT32_C(0x2)
- /*
- * This bit must be '1' for the new_meter_instance_id field to be
- * configured.
- */
- #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
- UINT32_C(0x4)
- uint8_t unused_0[4];
- /* This value is an opaque id into CFA data structures. */
- uint64_t ntuple_filter_id;
- /*
- * If set, this value shall represent the new
- * Logical VNIC ID of the destination VNIC for the RX
- * path and new network port id of the destination port for
- * the TX path.
- */
- uint32_t new_dst_id;
/*
- * New Logical VNIC ID of the VNIC where traffic is
- * mirrored.
+ * Function ID of the function that is being queried.
+ * Only valid for a VF FID queried by the PF.
*/
- uint32_t new_mirror_vnic_id;
+ uint16_t fid;
+ uint8_t unused_0[2];
/*
- * New meter to attach to the flow. Specifying the
- * invalid instance ID is used to remove any existing
- * meter from the flow.
+ * Maximum number of VLAN entries the firmware is allowed to DMA
+ * to vlan_tag_mask_tbl.
*/
- uint16_t new_meter_instance_id;
+ uint32_t max_vlan_entries;
/*
- * A value of 0xfff is considered invalid and implies the
- * instance is not configured.
+ * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
+ * antispoof table to which firmware will DMA to. Each table
+ * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
+ * 16-bit VLAN ID, and a 16-bit mask, all in network order to
+ * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
+ * the mask value should be 0xfff for the 12-bit VLAN ID.
*/
- #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
- UINT32_C(0xffff)
- #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
- HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
- uint8_t unused_1[6];
+ uint64_t vlan_tag_mask_tbl_addr;
} __attribute__((packed));
-/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
-struct hwrm_cfa_ntuple_filter_cfg_output {
+/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
+struct hwrm_cfa_vlan_antispoof_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
+ uint32_t num_vlan_entries;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/**************************
- * hwrm_cfa_em_flow_alloc *
- **************************/
+/********************************
+ * hwrm_cfa_tunnel_filter_alloc *
+ ********************************/
-/* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
-struct hwrm_cfa_em_flow_alloc_input {
+/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
+struct hwrm_cfa_tunnel_filter_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
uint16_t target_id;
/*
* A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- uint32_t flags;
- /*
- * Enumeration denoting the RX, TX type of the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
- */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
- /* tx path */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* rx path */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
- /*
- * Setting of this flag indicates enabling of a byte counter for a given
- * flow.
- */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
- /*
- * Setting of this flag indicates enabling of a packet counter for a given
- * flow.
- */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
- /* Setting of this flag indicates de-capsulation action for the given flow. */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
- /* Setting of this flag indicates encapsulation action for the given flow. */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
- /*
- * Setting of this flag indicates that a meter is expected to be attached
- * to this flow. This hint can be used when choosing the action record
- * format required for the flow.
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* Setting of this flag indicates the applicability to the loopback path. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
+ UINT32_C(0x1)
uint32_t enables;
/*
* This bit must be '1' for the l2_filter_id field to be
* configured.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
UINT32_C(0x1)
/*
- * This bit must be '1' for the tunnel_type field to be
+ * This bit must be '1' for the l2_addr field to be
* configured.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
UINT32_C(0x2)
/*
- * This bit must be '1' for the tunnel_id field to be
+ * This bit must be '1' for the l2_ivlan field to be
* configured.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
UINT32_C(0x4)
/*
- * This bit must be '1' for the src_macaddr field to be
+ * This bit must be '1' for the l3_addr field to be
* configured.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
UINT32_C(0x8)
/*
- * This bit must be '1' for the dst_macaddr field to be
+ * This bit must be '1' for the l3_addr_type field to be
* configured.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
UINT32_C(0x10)
/*
- * This bit must be '1' for the ovlan_vid field to be
+ * This bit must be '1' for the t_l3_addr_type field to be
* configured.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
UINT32_C(0x20)
/*
- * This bit must be '1' for the ivlan_vid field to be
+ * This bit must be '1' for the t_l3_addr field to be
* configured.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
UINT32_C(0x40)
/*
- * This bit must be '1' for the ethertype field to be
+ * This bit must be '1' for the tunnel_type field to be
* configured.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
UINT32_C(0x80)
/*
- * This bit must be '1' for the src_ipaddr field to be
+ * This bit must be '1' for the vni field to be
* configured.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
UINT32_C(0x100)
/*
- * This bit must be '1' for the dst_ipaddr field to be
+ * This bit must be '1' for the dst_vnic_id field to be
* configured.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
UINT32_C(0x200)
/*
- * This bit must be '1' for the ipaddr_type field to be
+ * This bit must be '1' for the mirror_vnic_id field to be
* configured.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
UINT32_C(0x400)
/*
- * This bit must be '1' for the ip_protocol field to be
- * configured.
- */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
- UINT32_C(0x800)
- /*
- * This bit must be '1' for the src_port field to be
- * configured.
+ * This value identifies a set of CFA data structures used for an L2
+ * context.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
- UINT32_C(0x1000)
+ uint64_t l2_filter_id;
/*
- * This bit must be '1' for the dst_port field to be
- * configured.
+ * This value sets the match value for the inner L2
+ * MAC address.
+ * Destination MAC address for RX path.
+ * Source MAC address for TX path.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
- UINT32_C(0x2000)
+ uint8_t l2_addr[6];
/*
- * This bit must be '1' for the dst_id field to be
- * configured.
+ * This value sets VLAN ID value for inner VLAN.
+ * Only 12-bits of VLAN ID are used in setting the filter.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
- UINT32_C(0x4000)
+ uint16_t l2_ivlan;
/*
- * This bit must be '1' for the mirror_vnic_id field to be
- * configured.
+ * The value of inner destination IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
- UINT32_C(0x8000)
+ uint32_t l3_addr[4];
/*
- * This bit must be '1' for the encap_record_id field to be
- * configured.
+ * The value of tunnel destination IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
- UINT32_C(0x10000)
+ uint32_t t_l3_addr[4];
/*
- * This bit must be '1' for the meter_instance_id field to be
- * configured.
+ * This value indicates the type of inner IP address.
+ * 4 - IPv4
+ * 6 - IPv6
+ * All others are invalid.
*/
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
- UINT32_C(0x20000)
+ uint8_t l3_addr_type;
/*
- * This value identifies a set of CFA data structures used for an L2
- * context.
+ * This value indicates the type of tunnel IP address.
+ * 4 - IPv4
+ * 6 - IPv6
+ * All others are invalid.
*/
- uint64_t l2_filter_id;
+ uint8_t t_l3_addr_type;
/* Tunnel Type. */
uint8_t tunnel_type;
/* Non-tunnel */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
UINT32_C(0x0)
/* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
UINT32_C(0x1)
/* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
UINT32_C(0x2)
/* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
UINT32_C(0x3)
/* IP in IP */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
UINT32_C(0x4)
/* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
/* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
UINT32_C(0x7)
/* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
UINT32_C(0x8)
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
/* Any tunneled traffic */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
- uint8_t unused_0[3];
- /*
- * Tunnel identifier.
- * Virtual Network Identifier (VNI). Only valid with
- * tunnel_types VXLAN, NVGRE, and Geneve.
- * Only lower 24-bits of VNI field are used
- * in setting up the filter.
- */
- uint32_t tunnel_id;
- /*
- * This value indicates the source MAC address in
- * the Ethernet header.
- */
- uint8_t src_macaddr[6];
- /* The meter instance to attach to the flow. */
- uint16_t meter_instance_id;
- /*
- * A value of 0xfff is considered invalid and implies the
- * instance is not configured.
- */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
- UINT32_C(0xffff)
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
- HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
- /*
- * This value indicates the destination MAC address in
- * the Ethernet header.
- */
- uint8_t dst_macaddr[6];
- /*
- * This value indicates the VLAN ID of the outer VLAN tag
- * in the Ethernet header.
- */
- uint16_t ovlan_vid;
- /*
- * This value indicates the VLAN ID of the inner VLAN tag
- * in the Ethernet header.
- */
- uint16_t ivlan_vid;
- /* This value indicates the ethertype in the Ethernet header. */
- uint16_t ethertype;
- /*
- * This value indicates the type of IP address.
- * 4 - IPv4
- * 6 - IPv6
- * All others are invalid.
- */
- uint8_t ip_addr_type;
- /* invalid */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
- /* IPv4 */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
- /* IPv6 */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
- HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
- /*
- * The value of protocol filed in IP header.
- * Applies to UDP and TCP traffic.
- * 6 - TCP
- * 17 - UDP
- */
- uint8_t ip_protocol;
- /* invalid */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
- /* TCP */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
- /* UDP */
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
- #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
- HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
- uint8_t unused_1[2];
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
/*
- * The value of source IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
+ * tunnel_flags allows the user to indicate the tunnel tag detection
+ * for the tunnel type specified in tunnel_type.
*/
- uint32_t src_ipaddr[4];
+ uint8_t tunnel_flags;
/*
- * big_endian = True
- * The value of destination IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
+ * If the tunnel_type is geneve, then this bit indicates if we
+ * need to match the geneve OAM packet.
+ * If the tunnel_type is nvgre or gre, then this bit indicates if
+ * we need to detect checksum present bit in geneve header.
+ * If the tunnel_type is mpls, then this bit indicates if we need
+ * to match mpls packet with explicit IPV4/IPV6 null header.
*/
- uint32_t dst_ipaddr[4];
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
+ UINT32_C(0x1)
/*
- * The value of source port to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * If the tunnel_type is geneve, then this bit indicates if we
+ * need to detect the critical option bit set in the oam packet.
+ * If the tunnel_type is nvgre or gre, then this bit indicates
+ * if we need to match nvgre packets with key present bit set in
+ * gre header.
+ * If the tunnel_type is mpls, then this bit indicates if we
+ * need to match mpls packet with S bit from inner/second label.
*/
- uint16_t src_port;
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
+ UINT32_C(0x2)
/*
- * The value of destination port to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * If the tunnel_type is geneve, then this bit indicates if we
+ * need to match geneve packet with extended header bit set in
+ * geneve header.
+ * If the tunnel_type is nvgre or gre, then this bit indicates
+ * if we need to match nvgre packets with sequence number
+ * present bit set in gre header.
+ * If the tunnel_type is mpls, then this bit indicates if we
+ * need to match mpls packet with S bit from out/first label.
*/
- uint16_t dst_port;
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
+ UINT32_C(0x4)
/*
- * If set, this value shall represent the
- * Logical VNIC ID of the destination VNIC for the RX
- * path and network port id of the destination port for
- * the TX path.
+ * Virtual Network Identifier (VNI). Only valid with
+ * tunnel_types VXLAN, NVGRE, and Geneve.
+ * Only lower 24-bits of VNI field are used
+ * in setting up the filter.
*/
- uint16_t dst_id;
+ uint32_t vni;
+ /* Logical VNIC ID of the destination VNIC. */
+ uint32_t dst_vnic_id;
/*
* Logical VNIC ID of the VNIC where traffic is
* mirrored.
*/
- uint16_t mirror_vnic_id;
- /* Logical ID of the encapsulation record. */
- uint32_t encap_record_id;
- uint8_t unused_2[4];
+ uint32_t mirror_vnic_id;
} __attribute__((packed));
-/* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
-struct hwrm_cfa_em_flow_alloc_output {
+/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
+struct hwrm_cfa_tunnel_filter_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
/* The length of the response data in number of bytes. */
uint16_t resp_len;
/* This value is an opaque id into CFA data structures. */
- uint64_t em_filter_id;
+ uint64_t tunnel_filter_id;
/*
* This is the ID of the flow associated with this
* filter.
uint8_t valid;
} __attribute__((packed));
-/*************************
- * hwrm_cfa_em_flow_free *
- *************************/
-
-
-/* hwrm_cfa_em_flow_free_input (size:192b/24B) */
-struct hwrm_cfa_em_flow_free_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- /* This value is an opaque id into CFA data structures. */
- uint64_t em_filter_id;
-} __attribute__((packed));
-
-/* hwrm_cfa_em_flow_free_output (size:128b/16B) */
-struct hwrm_cfa_em_flow_free_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/************************
- * hwrm_cfa_em_flow_cfg *
- ************************/
+/*******************************
+ * hwrm_cfa_tunnel_filter_free *
+ *******************************/
-/* hwrm_cfa_em_flow_cfg_input (size:384b/48B) */
-struct hwrm_cfa_em_flow_cfg_input {
+/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
+struct hwrm_cfa_tunnel_filter_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
- /*
- * This bit must be '1' for the new_dst_id field to be
- * configured.
- */
- #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID \
- UINT32_C(0x1)
- /*
- * This bit must be '1' for the new_mirror_vnic_id field to be
- * configured.
- */
- #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
- UINT32_C(0x2)
- /*
- * This bit must be '1' for the new_meter_instance_id field to be
- * configured.
- */
- #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
- UINT32_C(0x4)
- uint8_t unused_0[4];
/* This value is an opaque id into CFA data structures. */
- uint64_t em_filter_id;
- /*
- * If set, this value shall represent the new
- * Logical VNIC ID of the destination VNIC for the RX
- * path and network port id of the destination port for
- * the TX path.
- */
- uint32_t new_dst_id;
- /*
- * New Logical VNIC ID of the VNIC where traffic is
- * mirrored.
- */
- uint32_t new_mirror_vnic_id;
- /*
- * New meter to attach to the flow. Specifying the
- * invalid instance ID is used to remove any existing
- * meter from the flow.
- */
- uint16_t new_meter_instance_id;
- /*
- * A value of 0xfff is considered invalid and implies the
- * instance is not configured.
- */
- #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
- UINT32_C(0xffff)
- #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
- HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
- uint8_t unused_1[6];
+ uint64_t tunnel_filter_id;
} __attribute__((packed));
-/* hwrm_cfa_em_flow_cfg_output (size:128b/16B) */
-struct hwrm_cfa_em_flow_cfg_output {
+/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
+struct hwrm_cfa_tunnel_filter_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/********************************
- * hwrm_cfa_meter_profile_alloc *
- ********************************/
+/***************************************
+ * hwrm_cfa_redirect_tunnel_type_alloc *
+ ***************************************/
-/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
-struct hwrm_cfa_meter_profile_alloc_input {
+/* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
+struct hwrm_cfa_redirect_tunnel_type_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* command's response data will be written. This can be either a host
* physical address (HPA) or a guest physical address (GPA) and must
* point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- uint8_t flags;
- /*
- * Enumeration denoting the RX, TX type of the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
- */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
- /* tx path */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
- UINT32_C(0x0)
- /* rx path */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
- UINT32_C(0x1)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
- /* The meter algorithm type. */
- uint8_t meter_type;
- /* RFC 2697 (srTCM) */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
- UINT32_C(0x0)
- /* RFC 2698 (trTCM) */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
- UINT32_C(0x1)
- /* RFC 4115 (trTCM) */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
- UINT32_C(0x2)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
- /*
- * This field is reserved for the future use.
- * It shall be set to 0.
- */
- uint16_t reserved1;
- /*
- * This field is reserved for the future use.
- * It shall be set to 0.
- */
- uint32_t reserved2;
- /* A meter rate specified in bytes-per-second. */
- uint32_t commit_rate;
- /* The bandwidth value. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
- /* A meter burst size specified in bytes. */
- uint32_t commit_burst;
- /* The bandwidth value. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
- /* A meter rate specified in bytes-per-second. */
- uint32_t excess_peak_rate;
- /* The bandwidth value. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
- /* A meter burst size specified in bytes. */
- uint32_t excess_peak_burst;
- /* The bandwidth value. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
+ */
+ uint64_t resp_addr;
+ /* The destination function id, to whom the traffic is redirected. */
+ uint16_t dest_fid;
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ /* Tunnel alloc flags. */
+ uint8_t flags;
+ /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
+ UINT32_C(0x1)
+ uint8_t unused_0[4];
} __attribute__((packed));
-/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
-struct hwrm_cfa_meter_profile_alloc_output {
+/* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
+struct hwrm_cfa_redirect_tunnel_type_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* This value identifies a meter profile in CFA. */
- uint16_t meter_profile_id;
- /*
- * A value of 0xfff is considered invalid and implies the
- * profile is not configured.
- */
- #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
- UINT32_C(0xffff)
- #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
- uint8_t unused_0[5];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_cfa_meter_profile_free *
- *******************************/
+/**************************************
+ * hwrm_cfa_redirect_tunnel_type_free *
+ **************************************/
-/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
-struct hwrm_cfa_meter_profile_free_input {
+/* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
+struct hwrm_cfa_redirect_tunnel_type_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint8_t flags;
- /*
- * Enumeration denoting the RX, TX type of the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
- */
- #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
- /* tx path */
- #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
+ /* The destination function id, to whom the traffic is redirected. */
+ uint16_t dest_fid;
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
UINT32_C(0x0)
- /* rx path */
- #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
UINT32_C(0x1)
- #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
- uint8_t unused_0;
- /* This value identifies a meter profile in CFA. */
- uint16_t meter_profile_id;
- /*
- * A value of 0xfff is considered invalid and implies the
- * profile is not configured.
- */
- #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
- UINT32_C(0xffff)
- #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
- HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
- uint8_t unused_1[4];
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused_0[5];
} __attribute__((packed));
-/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
-struct hwrm_cfa_meter_profile_free_output {
+/* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
+struct hwrm_cfa_redirect_tunnel_type_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/******************************
- * hwrm_cfa_meter_profile_cfg *
- ******************************/
+/**************************************
+ * hwrm_cfa_redirect_tunnel_type_info *
+ **************************************/
-/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
-struct hwrm_cfa_meter_profile_cfg_input {
+/* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
+struct hwrm_cfa_redirect_tunnel_type_info_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint8_t flags;
- /*
- * Enumeration denoting the RX, TX type of the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
- */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
- /* tx path */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* rx path */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
- /* The meter algorithm type. */
- uint8_t meter_type;
- /* RFC 2697 (srTCM) */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
+ /* The source function id. */
+ uint16_t src_fid;
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
UINT32_C(0x0)
- /* RFC 2698 (trTCM) */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
UINT32_C(0x1)
- /* RFC 4115 (trTCM) */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
UINT32_C(0x2)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
- /* This value identifies a meter profile in CFA. */
- uint16_t meter_profile_id;
- /*
- * A value of 0xfff is considered invalid and implies the
- * profile is not configured.
- */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
- UINT32_C(0xffff)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
- /*
- * This field is reserved for the future use.
- * It shall be set to 0.
- */
- uint32_t reserved;
- /* A meter rate specified in bytes-per-second. */
- uint32_t commit_rate;
- /* The bandwidth value. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
- /* A meter burst size specified in bytes. */
- uint32_t commit_burst;
- /* The bandwidth value. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
- /* A meter rate specified in bytes-per-second. */
- uint32_t excess_peak_rate;
- /* The bandwidth value. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
- /* A meter burst size specified in bytes. */
- uint32_t excess_peak_burst;
- /* The bandwidth value. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused_0[5];
} __attribute__((packed));
-/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
-struct hwrm_cfa_meter_profile_cfg_output {
+/* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
+struct hwrm_cfa_redirect_tunnel_type_info_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /* The destination function id, to whom the traffic is redirected. */
+ uint16_t dest_fid;
+ uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/*********************************
- * hwrm_cfa_meter_instance_alloc *
- *********************************/
+/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
+struct hwrm_vxlan_ipv4_hdr {
+ /* IPv4 version and header length. */
+ uint8_t ver_hlen;
+ /* IPv4 header length */
+ #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
+ #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
+ /* Version */
+ #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
+ #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
+ /* IPv4 type of service. */
+ uint8_t tos;
+ /* IPv4 identification. */
+ uint16_t ip_id;
+ /* IPv4 flags and offset. */
+ uint16_t flags_frag_offset;
+ /* IPv4 TTL. */
+ uint8_t ttl;
+ /* IPv4 protocol. */
+ uint8_t protocol;
+ /* IPv4 source address. */
+ uint32_t src_ip_addr;
+ /* IPv4 destination address. */
+ uint32_t dest_ip_addr;
+} __attribute__((packed));
+
+/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
+struct hwrm_vxlan_ipv6_hdr {
+ /* IPv6 version, traffic class and flow label. */
+ uint32_t ver_tc_flow_label;
+ /* IPv6 version shift */
+ #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
+ UINT32_C(0x1c)
+ /* IPv6 version mask */
+ #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
+ UINT32_C(0xf0000000)
+ /* IPv6 TC shift */
+ #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
+ UINT32_C(0x14)
+ /* IPv6 TC mask */
+ #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
+ UINT32_C(0xff00000)
+ /* IPv6 flow label shift */
+ #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
+ UINT32_C(0x0)
+ /* IPv6 flow label mask */
+ #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
+ UINT32_C(0xfffff)
+ #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
+ HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
+ /* IPv6 payload length. */
+ uint16_t payload_len;
+ /* IPv6 next header. */
+ uint8_t next_hdr;
+ /* IPv6 TTL. */
+ uint8_t ttl;
+ /* IPv6 source address. */
+ uint32_t src_ip_addr[4];
+ /* IPv6 destination address. */
+ uint32_t dest_ip_addr[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
+struct hwrm_cfa_encap_data_vxlan {
+ /* Source MAC address. */
+ uint8_t src_mac_addr[6];
+ /* reserved. */
+ uint16_t unused_0;
+ /* Destination MAC address. */
+ uint8_t dst_mac_addr[6];
+ /* Number of VLAN tags. */
+ uint8_t num_vlan_tags;
+ /* reserved. */
+ uint8_t unused_1;
+ /* Outer VLAN TPID. */
+ uint16_t ovlan_tpid;
+ /* Outer VLAN TCI. */
+ uint16_t ovlan_tci;
+ /* Inner VLAN TPID. */
+ uint16_t ivlan_tpid;
+ /* Inner VLAN TCI. */
+ uint16_t ivlan_tci;
+ /* L3 header fields. */
+ uint32_t l3[10];
+ /* IP version mask. */
+ #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
+ /* IP version 4. */
+ #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
+ /* IP version 6. */
+ #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
+ #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
+ HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
+ /* UDP source port. */
+ uint16_t src_port;
+ /* UDP destination port. */
+ uint16_t dst_port;
+ /* VXLAN Network Identifier. */
+ uint32_t vni;
+ /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
+ uint8_t hdr_rsvd0[3];
+ /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
+ uint8_t hdr_rsvd1;
+ /* VXLAN header flags field. */
+ uint8_t hdr_flags;
+ uint8_t unused[3];
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_encap_record_alloc *
+ *******************************/
-/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
-struct hwrm_cfa_meter_instance_alloc_input {
+/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
+struct hwrm_cfa_encap_record_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint8_t flags;
- /*
- * Enumeration denoting the RX, TX type of the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
- */
- #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
+ uint32_t flags;
+ /* Setting of this flag indicates the applicability to the loopback path. */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
UINT32_C(0x1)
- /* tx path */
- #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
- UINT32_C(0x0)
- /* rx path */
- #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
+ /* Encapsulation Type. */
+ uint8_t encap_type;
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
UINT32_C(0x1)
- #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
- uint8_t unused_0;
- /* This value identifies a meter profile in CFA. */
- uint16_t meter_profile_id;
- /*
- * A value of 0xfff is considered invalid and implies the
- * profile is not configured.
- */
- #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
- UINT32_C(0xffff)
- #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
- HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
- uint8_t unused_1[4];
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* VLAN */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
+ HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4
+ uint8_t unused_0[3];
+ /* This value is encap data used for the given encap type. */
+ uint32_t encap_data[20];
} __attribute__((packed));
-/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
-struct hwrm_cfa_meter_instance_alloc_output {
+/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
+struct hwrm_cfa_encap_record_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* This value identifies a meter instance in CFA. */
- uint16_t meter_instance_id;
- /*
- * A value of 0xfff is considered invalid and implies the
- * instance is not configured.
- */
- #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
- UINT32_C(0xffff)
- #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
- HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
- uint8_t unused_0[5];
+ /* This value is an opaque id into CFA data structures. */
+ uint32_t encap_record_id;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/********************************
- * hwrm_cfa_meter_instance_free *
- ********************************/
+/******************************
+ * hwrm_cfa_encap_record_free *
+ ******************************/
-/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
-struct hwrm_cfa_meter_instance_free_input {
+/* hwrm_cfa_encap_record_free_input (size:192b/24B) */
+struct hwrm_cfa_encap_record_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint8_t flags;
- /*
- * Enumeration denoting the RX, TX type of the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
- */
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
- /* tx path */
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
- UINT32_C(0x0)
- /* rx path */
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
- UINT32_C(0x1)
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
- uint8_t unused_0;
- /* This value identifies a meter instance in CFA. */
- uint16_t meter_instance_id;
- /*
- * A value of 0xfff is considered invalid and implies the
- * instance is not configured.
- */
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
- UINT32_C(0xffff)
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
- HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
- uint8_t unused_1[4];
+ /* This value is an opaque id into CFA data structures. */
+ uint32_t encap_record_id;
+ uint8_t unused_0[4];
} __attribute__((packed));
-/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
-struct hwrm_cfa_meter_instance_free_output {
+/* hwrm_cfa_encap_record_free_output (size:128b/16B) */
+struct hwrm_cfa_encap_record_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_cfa_decap_filter_alloc *
- *******************************/
+/********************************
+ * hwrm_cfa_ntuple_filter_alloc *
+ ********************************/
-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
-struct hwrm_cfa_decap_filter_alloc_input {
+/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
+struct hwrm_cfa_ntuple_filter_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
*/
uint64_t resp_addr;
uint32_t flags;
- /* ovs_tunnel is 1 b */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
+ /* Setting of this flag indicates the applicability to the loopback path. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
UINT32_C(0x1)
+ /*
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
+ UINT32_C(0x2)
+ /*
+ * Setting of this flag indicates that a meter is expected to be attached
+ * to this flow. This hint can be used when choosing the action record
+ * format required for the flow.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
+ UINT32_C(0x4)
uint32_t enables;
/*
- * This bit must be '1' for the tunnel_type field to be
+ * This bit must be '1' for the l2_filter_id field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
UINT32_C(0x1)
/*
- * This bit must be '1' for the tunnel_id field to be
+ * This bit must be '1' for the ethertype field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
UINT32_C(0x2)
/*
- * This bit must be '1' for the src_macaddr field to be
+ * This bit must be '1' for the tunnel_type field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
UINT32_C(0x4)
/*
- * This bit must be '1' for the dst_macaddr field to be
+ * This bit must be '1' for the src_macaddr field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
UINT32_C(0x8)
/*
- * This bit must be '1' for the ovlan_vid field to be
+ * This bit must be '1' for the ipaddr_type field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
UINT32_C(0x10)
/*
- * This bit must be '1' for the ivlan_vid field to be
+ * This bit must be '1' for the src_ipaddr field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
UINT32_C(0x20)
/*
- * This bit must be '1' for the t_ovlan_vid field to be
+ * This bit must be '1' for the src_ipaddr_mask field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
UINT32_C(0x40)
/*
- * This bit must be '1' for the t_ivlan_vid field to be
+ * This bit must be '1' for the dst_ipaddr field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
UINT32_C(0x80)
/*
- * This bit must be '1' for the ethertype field to be
+ * This bit must be '1' for the dst_ipaddr_mask field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
UINT32_C(0x100)
/*
- * This bit must be '1' for the src_ipaddr field to be
+ * This bit must be '1' for the ip_protocol field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
UINT32_C(0x200)
/*
- * This bit must be '1' for the dst_ipaddr field to be
+ * This bit must be '1' for the src_port field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
UINT32_C(0x400)
/*
- * This bit must be '1' for the ipaddr_type field to be
+ * This bit must be '1' for the src_port_mask field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
UINT32_C(0x800)
/*
- * This bit must be '1' for the ip_protocol field to be
+ * This bit must be '1' for the dst_port field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
UINT32_C(0x1000)
/*
- * This bit must be '1' for the src_port field to be
+ * This bit must be '1' for the dst_port_mask field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
UINT32_C(0x2000)
/*
- * This bit must be '1' for the dst_port field to be
+ * This bit must be '1' for the pri_hint field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
UINT32_C(0x4000)
/*
- * This bit must be '1' for the dst_id field to be
+ * This bit must be '1' for the ntuple_filter_id field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
UINT32_C(0x8000)
/*
- * This bit must be '1' for the mirror_vnic_id field to be
+ * This bit must be '1' for the dst_id field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
UINT32_C(0x10000)
/*
- * Tunnel identifier.
- * Virtual Network Identifier (VNI). Only valid with
- * tunnel_types VXLAN, NVGRE, and Geneve.
- * Only lower 24-bits of VNI field are used
- * in setting up the filter.
- */
- uint32_t tunnel_id;
- /* Tunnel Type. */
- uint8_t tunnel_type;
- /* Non-tunnel */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
- UINT32_C(0x0)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
- UINT32_C(0x1)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
- UINT32_C(0x2)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
- UINT32_C(0x3)
- /* IP in IP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
- UINT32_C(0x4)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
- UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
- UINT32_C(0x6)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
- UINT32_C(0x7)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
- UINT32_C(0x8)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
- UINT32_C(0x9)
- /* Any tunneled traffic */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
- UINT32_C(0xff)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
- uint8_t unused_0;
- uint16_t unused_1;
- /*
- * This value indicates the source MAC address in
- * the Ethernet header.
- */
- uint8_t src_macaddr[6];
- uint8_t unused_2[2];
- /*
- * This value indicates the destination MAC address in
- * the Ethernet header.
- */
- uint8_t dst_macaddr[6];
- /*
- * This value indicates the VLAN ID of the outer VLAN tag
- * in the Ethernet header.
+ * This bit must be '1' for the mirror_vnic_id field to be
+ * configured.
*/
- uint16_t ovlan_vid;
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
+ UINT32_C(0x20000)
/*
- * This value indicates the VLAN ID of the inner VLAN tag
- * in the Ethernet header.
+ * This bit must be '1' for the dst_macaddr field to be
+ * configured.
*/
- uint16_t ivlan_vid;
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
+ UINT32_C(0x40000)
/*
- * This value indicates the VLAN ID of the outer VLAN tag
- * in the tunnel Ethernet header.
+ * This value identifies a set of CFA data structures used for an L2
+ * context.
*/
- uint16_t t_ovlan_vid;
+ uint64_t l2_filter_id;
/*
- * This value indicates the VLAN ID of the inner VLAN tag
- * in the tunnel Ethernet header.
+ * This value indicates the source MAC address in
+ * the Ethernet header.
*/
- uint16_t t_ivlan_vid;
+ uint8_t src_macaddr[6];
/* This value indicates the ethertype in the Ethernet header. */
uint16_t ethertype;
/*
*/
uint8_t ip_addr_type;
/* invalid */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
UINT32_C(0x0)
/* IPv4 */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
UINT32_C(0x4)
/* IPv6 */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
UINT32_C(0x6)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
/*
* The value of protocol filed in IP header.
* Applies to UDP and TCP traffic.
*/
uint8_t ip_protocol;
/* invalid */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
UINT32_C(0x0)
/* TCP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
UINT32_C(0x6)
/* UDP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
UINT32_C(0x11)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
- uint16_t unused_3;
- uint32_t unused_4;
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
+ /*
+ * If set, this value shall represent the
+ * Logical VNIC ID of the destination VNIC for the RX
+ * path and network port id of the destination port for
+ * the TX path.
+ */
+ uint16_t dst_id;
+ /*
+ * Logical VNIC ID of the VNIC where traffic is
+ * mirrored.
+ */
+ uint16_t mirror_vnic_id;
+ /*
+ * This value indicates the tunnel type for this filter.
+ * If this field is not specified, then the filter shall
+ * apply to both non-tunneled and tunneled packets.
+ * If this field conflicts with the tunnel_type specified
+ * in the l2_filter_id, then the HWRM shall return an
+ * error for this command.
+ */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ /*
+ * This hint is provided to help in placing
+ * the filter in the filter table.
+ */
+ uint8_t pri_hint;
+ /* No preference */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
+ UINT32_C(0x0)
+ /* Above the given filter */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
+ UINT32_C(0x1)
+ /* Below the given filter */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
+ UINT32_C(0x2)
+ /* As high as possible */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
+ UINT32_C(0x3)
+ /* As low as possible */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
+ UINT32_C(0x4)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
/*
* The value of source IP address to be used in filtering.
* For IPv4, first four bytes represent the IP address.
*/
- uint32_t src_ipaddr[4];
+ uint32_t src_ipaddr[4];
+ /*
+ * The value of source IP address mask to be used in
+ * filtering.
+ * For IPv4, first four bytes represent the IP address mask.
+ */
+ uint32_t src_ipaddr_mask[4];
/*
* The value of destination IP address to be used in filtering.
* For IPv4, first four bytes represent the IP address.
*/
uint32_t dst_ipaddr[4];
+ /*
+ * The value of destination IP address mask to be used in
+ * filtering.
+ * For IPv4, first four bytes represent the IP address mask.
+ */
+ uint32_t dst_ipaddr_mask[4];
/*
* The value of source port to be used in filtering.
* Applies to UDP and TCP traffic.
*/
uint16_t src_port;
+ /*
+ * The value of source port mask to be used in filtering.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t src_port_mask;
/*
* The value of destination port to be used in filtering.
* Applies to UDP and TCP traffic.
*/
uint16_t dst_port;
/*
- * If set, this value shall represent the
- * Logical VNIC ID of the destination VNIC for the RX
- * path.
+ * The value of destination port mask to be used in
+ * filtering.
+ * Applies to UDP and TCP traffic.
*/
- uint16_t dst_id;
+ uint16_t dst_port_mask;
/*
- * If set, this value shall represent the L2 context that matches the L2
- * information of the decap filter.
+ * This is the ID of the filter that goes along with
+ * the pri_hint.
*/
- uint16_t l2_ctxt_ref_id;
+ uint64_t ntuple_filter_id_hint;
} __attribute__((packed));
-/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
-struct hwrm_cfa_decap_filter_alloc_output {
+/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
+struct hwrm_cfa_ntuple_filter_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
/* The length of the response data in number of bytes. */
uint16_t resp_len;
/* This value is an opaque id into CFA data structures. */
- uint32_t decap_filter_id;
+ uint64_t ntuple_filter_id;
+ /*
+ * This is the ID of the flow associated with this
+ * filter.
+ * This value shall be used to match and associate the
+ * flow identifier returned in completion records.
+ * A value of 0xFFFFFFFF shall indicate no flow id.
+ */
+ uint32_t flow_id;
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
uint8_t valid;
} __attribute__((packed));
-/******************************
- * hwrm_cfa_decap_filter_free *
- ******************************/
-
-
-/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
-struct hwrm_cfa_decap_filter_free_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
+/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
+struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * command specific error codes that goes to
+ * the cmd_err field in Common HWRM Error Response.
*/
- uint64_t resp_addr;
- /* This value is an opaque id into CFA data structures. */
- uint32_t decap_filter_id;
- uint8_t unused_0[4];
-} __attribute__((packed));
-
-/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
-struct hwrm_cfa_decap_filter_free_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
+ uint8_t code;
+ /* Unknown error */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
+ UINT32_C(0x0)
+ /* Unable to complete operation due to conflict with Rx Mask VLAN */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
+ UINT32_C(0x1)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
uint8_t unused_0[7];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_alloc *
- ***********************/
+/*******************************
+ * hwrm_cfa_ntuple_filter_free *
+ *******************************/
-/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
-struct hwrm_cfa_flow_alloc_input {
+/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
+struct hwrm_cfa_ntuple_filter_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* physical address (HPA) or a guest physical address (GPA) and must
* point to a physically contiguous block of memory.
*/
- uint64_t resp_addr;
- uint16_t flags;
- /* tunnel is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL UINT32_C(0x1)
- /* num_vlan is 2 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK UINT32_C(0x6)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
- /* no tags */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
- (UINT32_C(0x0) << 1)
- /* 1 tag */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
- (UINT32_C(0x1) << 1)
- /* 2 tags */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
- (UINT32_C(0x2) << 1)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
- /* Enumeration denoting the Flow Type. */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK UINT32_C(0x38)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
- /* L2 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
- (UINT32_C(0x0) << 3)
- /* IPV4 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
- (UINT32_C(0x1) << 3)
- /* IPV6 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
- (UINT32_C(0x2) << 3)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
- /*
- * Tx Flow: vf fid.
- * Rx Flow: pf fid.
- */
- uint16_t src_fid;
- /* Tunnel handle valid when tunnel flag is set. */
- uint32_t tunnel_handle;
- uint16_t action_flags;
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
- UINT32_C(0x1)
- /* recycle is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
- UINT32_C(0x2)
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
- UINT32_C(0x4)
- /* meter is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
- UINT32_C(0x8)
- /* tunnel is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
- UINT32_C(0x10)
- /* nat_src is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
- UINT32_C(0x20)
- /* nat_dest is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
- UINT32_C(0x40)
- /* nat_ipv4_address is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
- UINT32_C(0x80)
- /* l2_header_rewrite is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
- UINT32_C(0x100)
- /* ttl_decrement is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
- UINT32_C(0x200)
- /*
- * Tx Flow: pf or vf fid.
- * Rx Flow: vf fid.
- */
- uint16_t dst_fid;
- /* VLAN tpid, valid when push_vlan flag is set. */
- uint16_t l2_rewrite_vlan_tpid;
- /* VLAN tci, valid when push_vlan flag is set. */
- uint16_t l2_rewrite_vlan_tci;
- /* Meter id, valid when meter flag is set. */
- uint16_t act_meter_id;
- /* Flow with the same l2 context tcam key. */
- uint16_t ref_flow_handle;
- /* This value sets the match value for the ethertype. */
- uint16_t ethertype;
- /* valid when num tags is 1 or 2. */
- uint16_t outer_vlan_tci;
- /* This value sets the match value for the Destination MAC address. */
- uint16_t dmac[3];
- /* valid when num tags is 2. */
- uint16_t inner_vlan_tci;
- /* This value sets the match value for the Source MAC address. */
- uint16_t smac[3];
- /* The bit length of destination IP address mask. */
- uint8_t ip_dst_mask_len;
- /* The bit length of source IP address mask. */
- uint8_t ip_src_mask_len;
- /* The value of destination IPv4/IPv6 address. */
- uint32_t ip_dst[4];
- /* The source IPv4/IPv6 address. */
- uint32_t ip_src[4];
- /*
- * The value of source port.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_src_port;
- /*
- * The value of source port mask.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_src_port_mask;
- /*
- * The value of destination port.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_dst_port;
- /*
- * The value of destination port mask.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_dst_port_mask;
- /*
- * NAT IPv4/6 address based on address type flag.
- * 0 values are ignored.
- */
- uint32_t nat_ip_address[4];
- /* L2 header re-write Destination MAC address. */
- uint16_t l2_rewrite_dmac[3];
- /*
- * The NAT source/destination port based on direction flag.
- * Applies to UDP and TCP traffic.
- * 0 values are ignored.
- */
- uint16_t nat_port;
- /* L2 header re-write Source MAC address. */
- uint16_t l2_rewrite_smac[3];
- /* The value of ip protocol. */
- uint8_t ip_proto;
- uint8_t unused_0;
+ uint64_t resp_addr;
+ /* This value is an opaque id into CFA data structures. */
+ uint64_t ntuple_filter_id;
} __attribute__((packed));
-/* hwrm_cfa_flow_alloc_output (size:128b/16B) */
-struct hwrm_cfa_flow_alloc_output {
+/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
+struct hwrm_cfa_ntuple_filter_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Flow record index. */
- uint16_t flow_handle;
- uint8_t unused_0[5];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_cfa_flow_free *
- **********************/
+/******************************
+ * hwrm_cfa_ntuple_filter_cfg *
+ ******************************/
-/* hwrm_cfa_flow_free_input (size:192b/24B) */
-struct hwrm_cfa_flow_free_input {
+/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
+struct hwrm_cfa_ntuple_filter_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Flow record index. */
- uint16_t flow_handle;
- uint8_t unused_0[6];
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the new_dst_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the new_mirror_vnic_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the new_meter_instance_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
+ UINT32_C(0x4)
+ uint8_t unused_0[4];
+ /* This value is an opaque id into CFA data structures. */
+ uint64_t ntuple_filter_id;
+ /*
+ * If set, this value shall represent the new
+ * Logical VNIC ID of the destination VNIC for the RX
+ * path and new network port id of the destination port for
+ * the TX path.
+ */
+ uint32_t new_dst_id;
+ /*
+ * New Logical VNIC ID of the VNIC where traffic is
+ * mirrored.
+ */
+ uint32_t new_mirror_vnic_id;
+ /*
+ * New meter to attach to the flow. Specifying the
+ * invalid instance ID is used to remove any existing
+ * meter from the flow.
+ */
+ uint16_t new_meter_instance_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
+ uint8_t unused_1[6];
} __attribute__((packed));
-/* hwrm_cfa_flow_free_output (size:256b/32B) */
-struct hwrm_cfa_flow_free_output {
+/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
+struct hwrm_cfa_ntuple_filter_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* packet is 64 b */
- uint64_t packet;
- /* byte is 64 b */
- uint64_t byte;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_cfa_flow_info *
- **********************/
+/**************************
+ * hwrm_cfa_em_flow_alloc *
+ **************************/
-/* hwrm_cfa_flow_info_input (size:192b/24B) */
-struct hwrm_cfa_flow_info_input {
+/* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
+struct hwrm_cfa_em_flow_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Flow record index. */
- uint16_t flow_handle;
- /* Max flow handle */
- #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
- UINT32_C(0xfff)
- #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
- /* CNP flow handle */
- #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
+ uint32_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
+ /*
+ * Setting of this flag indicates enabling of a byte counter for a given
+ * flow.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
+ /*
+ * Setting of this flag indicates enabling of a packet counter for a given
+ * flow.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
+ /* Setting of this flag indicates de-capsulation action for the given flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
+ /* Setting of this flag indicates encapsulation action for the given flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
+ /*
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
+ /*
+ * Setting of this flag indicates that a meter is expected to be attached
+ * to this flow. This hint can be used when choosing the action record
+ * format required for the flow.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the l2_filter_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the tunnel_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the tunnel_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the src_macaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the dst_macaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the ovlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the ivlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the ethertype field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
+ UINT32_C(0x80)
+ /*
+ * This bit must be '1' for the src_ipaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+ UINT32_C(0x100)
+ /*
+ * This bit must be '1' for the dst_ipaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
+ UINT32_C(0x200)
+ /*
+ * This bit must be '1' for the ipaddr_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
+ UINT32_C(0x400)
+ /*
+ * This bit must be '1' for the ip_protocol field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
+ UINT32_C(0x800)
+ /*
+ * This bit must be '1' for the src_port field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
UINT32_C(0x1000)
- /* Direction rx = 1 */
- #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
+ /*
+ * This bit must be '1' for the dst_port field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
+ UINT32_C(0x2000)
+ /*
+ * This bit must be '1' for the dst_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
+ UINT32_C(0x4000)
+ /*
+ * This bit must be '1' for the mirror_vnic_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
UINT32_C(0x8000)
- uint8_t unused_0[6];
-} __attribute__((packed));
-
-/* hwrm_cfa_flow_info_output (size:448b/56B) */
-struct hwrm_cfa_flow_info_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* flags is 8 b */
- uint8_t flags;
- /* profile is 8 b */
- uint8_t profile;
- /* src_fid is 16 b */
- uint16_t src_fid;
- /* dst_fid is 16 b */
- uint16_t dst_fid;
- /* l2_ctxt_id is 16 b */
- uint16_t l2_ctxt_id;
- /* em_info is 64 b */
- uint64_t em_info;
- /* tcam_info is 64 b */
- uint64_t tcam_info;
- /* vfp_tcam_info is 64 b */
- uint64_t vfp_tcam_info;
- /* ar_id is 16 b */
- uint16_t ar_id;
- /* flow_handle is 16 b */
- uint16_t flow_handle;
- /* tunnel_handle is 32 b */
- uint32_t tunnel_handle;
- uint8_t unused_0[7];
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * This bit must be '1' for the encap_record_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
+ UINT32_C(0x10000)
+ /*
+ * This bit must be '1' for the meter_instance_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
+ UINT32_C(0x20000)
+ /*
+ * This value identifies a set of CFA data structures used for an L2
+ * context.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/***********************
- * hwrm_cfa_flow_flush *
- ***********************/
-
-
-/* hwrm_cfa_flow_flush_input (size:192b/24B) */
-struct hwrm_cfa_flow_flush_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint64_t l2_filter_id;
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused_0[3];
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Tunnel identifier.
+ * Virtual Network Identifier (VNI). Only valid with
+ * tunnel_types VXLAN, NVGRE, and Geneve.
+ * Only lower 24-bits of VNI field are used
+ * in setting up the filter.
*/
- uint16_t cmpl_ring;
+ uint32_t tunnel_id;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * This value indicates the source MAC address in
+ * the Ethernet header.
*/
- uint16_t seq_id;
+ uint8_t src_macaddr[6];
+ /* The meter instance to attach to the flow. */
+ uint16_t meter_instance_id;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
*/
- uint16_t target_id;
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * This value indicates the destination MAC address in
+ * the Ethernet header.
*/
- uint64_t resp_addr;
- uint32_t flags;
- uint8_t unused_0[4];
-} __attribute__((packed));
-
-/* hwrm_cfa_flow_flush_output (size:128b/16B) */
-struct hwrm_cfa_flow_flush_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
+ uint8_t dst_macaddr[6];
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * This value indicates the VLAN ID of the outer VLAN tag
+ * in the Ethernet header.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/***********************
- * hwrm_cfa_flow_stats *
- ***********************/
-
-
-/* hwrm_cfa_flow_stats_input (size:320b/40B) */
-struct hwrm_cfa_flow_stats_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint16_t ovlan_vid;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This value indicates the VLAN ID of the inner VLAN tag
+ * in the Ethernet header.
*/
- uint16_t cmpl_ring;
+ uint16_t ivlan_vid;
+ /* This value indicates the ethertype in the Ethernet header. */
+ uint16_t ethertype;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * This value indicates the type of IP address.
+ * 4 - IPv4
+ * 6 - IPv6
+ * All others are invalid.
*/
- uint16_t seq_id;
+ uint8_t ip_addr_type;
+ /* invalid */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
+ /* IPv4 */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
+ /* IPv6 */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * The value of protocol filed in IP header.
+ * Applies to UDP and TCP traffic.
+ * 6 - TCP
+ * 17 - UDP
*/
- uint16_t target_id;
+ uint8_t ip_protocol;
+ /* invalid */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
+ /* TCP */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
+ /* UDP */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
+ uint8_t unused_1[2];
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * The value of source IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
*/
- uint64_t resp_addr;
- /* Flow handle. */
- uint16_t num_flows;
- /* Flow handle. */
- uint16_t flow_handle_0;
- /* Flow handle. */
- uint16_t flow_handle_1;
- /* Flow handle. */
- uint16_t flow_handle_2;
- /* Flow handle. */
- uint16_t flow_handle_3;
- /* Flow handle. */
- uint16_t flow_handle_4;
- /* Flow handle. */
- uint16_t flow_handle_5;
- /* Flow handle. */
- uint16_t flow_handle_6;
- /* Flow handle. */
- uint16_t flow_handle_7;
- /* Flow handle. */
- uint16_t flow_handle_8;
- /* Flow handle. */
- uint16_t flow_handle_9;
- uint8_t unused_0[2];
-} __attribute__((packed));
-
-/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
-struct hwrm_cfa_flow_stats_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* packet_0 is 64 b */
- uint64_t packet_0;
- /* packet_1 is 64 b */
- uint64_t packet_1;
- /* packet_2 is 64 b */
- uint64_t packet_2;
- /* packet_3 is 64 b */
- uint64_t packet_3;
- /* packet_4 is 64 b */
- uint64_t packet_4;
- /* packet_5 is 64 b */
- uint64_t packet_5;
- /* packet_6 is 64 b */
- uint64_t packet_6;
- /* packet_7 is 64 b */
- uint64_t packet_7;
- /* packet_8 is 64 b */
- uint64_t packet_8;
- /* packet_9 is 64 b */
- uint64_t packet_9;
- /* byte_0 is 64 b */
- uint64_t byte_0;
- /* byte_1 is 64 b */
- uint64_t byte_1;
- /* byte_2 is 64 b */
- uint64_t byte_2;
- /* byte_3 is 64 b */
- uint64_t byte_3;
- /* byte_4 is 64 b */
- uint64_t byte_4;
- /* byte_5 is 64 b */
- uint64_t byte_5;
- /* byte_6 is 64 b */
- uint64_t byte_6;
- /* byte_7 is 64 b */
- uint64_t byte_7;
- /* byte_8 is 64 b */
- uint64_t byte_8;
- /* byte_9 is 64 b */
- uint64_t byte_9;
- uint8_t unused_0[7];
+ uint32_t src_ipaddr[4];
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * big_endian = True
+ * The value of destination IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/**************************
- * hwrm_cfa_vf_pair_alloc *
- **************************/
-
-
-/* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */
-struct hwrm_cfa_vf_pair_alloc_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint32_t dst_ipaddr[4];
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * The value of source port to be used in filtering.
+ * Applies to UDP and TCP traffic.
*/
- uint16_t cmpl_ring;
+ uint16_t src_port;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * The value of destination port to be used in filtering.
+ * Applies to UDP and TCP traffic.
*/
- uint16_t seq_id;
+ uint16_t dst_port;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * If set, this value shall represent the
+ * Logical VNIC ID of the destination VNIC for the RX
+ * path and network port id of the destination port for
+ * the TX path.
*/
- uint16_t target_id;
+ uint16_t dst_id;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Logical VNIC ID of the VNIC where traffic is
+ * mirrored.
*/
- uint64_t resp_addr;
- /* Logical VF number (range: 0 -> MAX_VFS -1). */
- uint16_t vf_a_id;
- /* Logical VF number (range: 0 -> MAX_VFS -1). */
- uint16_t vf_b_id;
- uint8_t unused_0[4];
- /* VF Pair name (32 byte string). */
- char pair_name[32];
+ uint16_t mirror_vnic_id;
+ /* Logical ID of the encapsulation record. */
+ uint32_t encap_record_id;
+ uint8_t unused_2[4];
} __attribute__((packed));
-/* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */
-struct hwrm_cfa_vf_pair_alloc_output {
+/* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
+struct hwrm_cfa_em_flow_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /* This value is an opaque id into CFA data structures. */
+ uint64_t em_filter_id;
+ /*
+ * This is the ID of the flow associated with this
+ * filter.
+ * This value shall be used to match and associate the
+ * flow identifier returned in completion records.
+ * A value of 0xFFFFFFFF shall indicate no flow id.
+ */
+ uint32_t flow_id;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
} __attribute__((packed));
/*************************
- * hwrm_cfa_vf_pair_free *
+ * hwrm_cfa_em_flow_free *
*************************/
-/* hwrm_cfa_vf_pair_free_input (size:384b/48B) */
-struct hwrm_cfa_vf_pair_free_input {
+/* hwrm_cfa_em_flow_free_input (size:192b/24B) */
+struct hwrm_cfa_em_flow_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* VF Pair name (32 byte string). */
- char pair_name[32];
+ /* This value is an opaque id into CFA data structures. */
+ uint64_t em_filter_id;
} __attribute__((packed));
-/* hwrm_cfa_vf_pair_free_output (size:128b/16B) */
-struct hwrm_cfa_vf_pair_free_output {
+/* hwrm_cfa_em_flow_free_output (size:128b/16B) */
+struct hwrm_cfa_em_flow_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/*************************
- * hwrm_cfa_vf_pair_info *
- *************************/
+/*******************************
+ * hwrm_cfa_decap_filter_alloc *
+ *******************************/
-/* hwrm_cfa_vf_pair_info_input (size:448b/56B) */
-struct hwrm_cfa_vf_pair_info_input {
+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
+struct hwrm_cfa_decap_filter_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
*/
uint64_t resp_addr;
uint32_t flags;
- /* If this flag is set, lookup by name else lookup by index. */
- #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
- /* vf pair table index. */
- uint16_t vf_pair_index;
- uint8_t unused_0[2];
- /* VF Pair name (32 byte string). */
- char vf_pair_name[32];
-} __attribute__((packed));
-
-/* hwrm_cfa_vf_pair_info_output (size:512b/64B) */
-struct hwrm_cfa_vf_pair_info_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* vf pair table index. */
- uint16_t next_vf_pair_index;
- /* vf pair member a's vf_fid. */
- uint16_t vf_a_fid;
- /* vf pair member a's Linux logical VF number. */
- uint16_t vf_a_index;
- /* vf pair member b's vf_fid. */
- uint16_t vf_b_fid;
- /* vf pair member a's Linux logical VF number. */
- uint16_t vf_b_index;
- /* vf pair state. */
- uint8_t pair_state;
- /* Pair has been allocated */
- #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
- /* Both pair members are active */
- #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
- #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
- HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
- uint8_t unused_0[5];
- /* VF Pair name (32 byte string). */
- char pair_name[32];
- uint8_t unused_1[7];
+ /* ovs_tunnel is 1 b */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
+ UINT32_C(0x1)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the tunnel_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the tunnel_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the src_macaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the dst_macaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the ovlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the ivlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the t_ovlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the t_ivlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
+ UINT32_C(0x80)
+ /*
+ * This bit must be '1' for the ethertype field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
+ UINT32_C(0x100)
+ /*
+ * This bit must be '1' for the src_ipaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+ UINT32_C(0x200)
+ /*
+ * This bit must be '1' for the dst_ipaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
+ UINT32_C(0x400)
+ /*
+ * This bit must be '1' for the ipaddr_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
+ UINT32_C(0x800)
+ /*
+ * This bit must be '1' for the ip_protocol field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
+ UINT32_C(0x1000)
+ /*
+ * This bit must be '1' for the src_port field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
+ UINT32_C(0x2000)
+ /*
+ * This bit must be '1' for the dst_port field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
+ UINT32_C(0x4000)
+ /*
+ * This bit must be '1' for the dst_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
+ UINT32_C(0x8000)
+ /*
+ * This bit must be '1' for the mirror_vnic_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
+ UINT32_C(0x10000)
+ /*
+ * Tunnel identifier.
+ * Virtual Network Identifier (VNI). Only valid with
+ * tunnel_types VXLAN, NVGRE, and Geneve.
+ * Only lower 24-bits of VNI field are used
+ * in setting up the filter.
+ */
+ uint32_t tunnel_id;
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused_0;
+ uint16_t unused_1;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * This value indicates the source MAC address in
+ * the Ethernet header.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/***********************
- * hwrm_cfa_pair_alloc *
- ***********************/
-
-
-/* hwrm_cfa_pair_alloc_input (size:576b/72B) */
-struct hwrm_cfa_pair_alloc_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint8_t src_macaddr[6];
+ uint8_t unused_2[2];
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This value indicates the destination MAC address in
+ * the Ethernet header.
*/
- uint16_t cmpl_ring;
+ uint8_t dst_macaddr[6];
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * This value indicates the VLAN ID of the outer VLAN tag
+ * in the Ethernet header.
*/
- uint16_t seq_id;
+ uint16_t ovlan_vid;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * This value indicates the VLAN ID of the inner VLAN tag
+ * in the Ethernet header.
*/
- uint16_t target_id;
+ uint16_t ivlan_vid;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * This value indicates the VLAN ID of the outer VLAN tag
+ * in the tunnel Ethernet header.
*/
- uint64_t resp_addr;
- /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair, 5-rep2fn_mod). */
- uint8_t pair_mode;
- /* Pair between VF on local host with PF or VF on specified host. */
- #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
- /* Pair between REP on local host with PF or VF on specified host. */
- #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
- /* Pair between REP on local host with REP on specified host. */
- #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
- /* Pair for the proxy interface. */
- #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
- /* Pair for the PF interface. */
- #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
- /* Modify exiting rep2fn pair and move pair to new PF. */
- #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
- /* Modify exiting rep2fn pairs paired with same PF and move pairs to new PF. */
- #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
- #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \
- HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL
- uint8_t unused_0;
- /* Logical VF number (range: 0 -> MAX_VFS -1). */
- uint16_t vf_a_id;
- /* Logical Host (0xff-local host). */
- uint8_t host_b_id;
- /* Logical PF (0xff-PF for command channel). */
- uint8_t pf_b_id;
- /* Logical VF number (range: 0 -> MAX_VFS -1). */
- uint16_t vf_b_id;
- /* Loopback port (0xff-internal loopback), valid for mode-3. */
- uint8_t port_id;
- /* Priority used for encap of loopback packets valid for mode-3. */
- uint8_t pri;
- /* New PF for rep2fn modify, valid for mode 5. */
- uint16_t new_pf_fid;
- uint32_t enables;
+ uint16_t t_ovlan_vid;
/*
- * This bit must be '1' for the q_ab field to be
- * configured.
+ * This value indicates the VLAN ID of the inner VLAN tag
+ * in the tunnel Ethernet header.
*/
- #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)
+ uint16_t t_ivlan_vid;
+ /* This value indicates the ethertype in the Ethernet header. */
+ uint16_t ethertype;
/*
- * This bit must be '1' for the q_ba field to be
- * configured.
+ * This value indicates the type of IP address.
+ * 4 - IPv4
+ * 6 - IPv6
+ * All others are invalid.
*/
- #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)
+ uint8_t ip_addr_type;
+ /* invalid */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
+ UINT32_C(0x0)
+ /* IPv4 */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
+ UINT32_C(0x4)
+ /* IPv6 */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
+ UINT32_C(0x6)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
/*
- * This bit must be '1' for the fc_ab field to be
- * configured.
+ * The value of protocol filed in IP header.
+ * Applies to UDP and TCP traffic.
+ * 6 - TCP
+ * 17 - UDP
+ */
+ uint8_t ip_protocol;
+ /* invalid */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
+ UINT32_C(0x0)
+ /* TCP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
+ UINT32_C(0x6)
+ /* UDP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
+ UINT32_C(0x11)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
+ uint16_t unused_3;
+ uint32_t unused_4;
+ /*
+ * The value of source IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
*/
- #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)
+ uint32_t src_ipaddr[4];
/*
- * This bit must be '1' for the fc_ba field to be
- * configured.
+ * The value of destination IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
*/
- #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)
- /* VF Pair name (32 byte string). */
- char pair_name[32];
+ uint32_t dst_ipaddr[4];
/*
- * The q_ab value specifies the logical index of the TX/RX CoS
- * queue to be assigned for traffic in the A to B direction of
- * the interface pair. The default value is 0.
+ * The value of source port to be used in filtering.
+ * Applies to UDP and TCP traffic.
*/
- uint8_t q_ab;
+ uint16_t src_port;
/*
- * The q_ba value specifies the logical index of the TX/RX CoS
- * queue to be assigned for traffic in the B to A direction of
- * the interface pair. The default value is 1.
+ * The value of destination port to be used in filtering.
+ * Applies to UDP and TCP traffic.
*/
- uint8_t q_ba;
+ uint16_t dst_port;
/*
- * Specifies whether RX ring flow control is disabled (0) or enabled
- * (1) in the A to B direction. The default value is 0, meaning that
- * packets will be dropped when the B-side RX rings are full.
+ * If set, this value shall represent the
+ * Logical VNIC ID of the destination VNIC for the RX
+ * path.
*/
- uint8_t fc_ab;
+ uint16_t dst_id;
/*
- * Specifies whether RX ring flow control is disabled (0) or enabled
- * (1) in the B to A direction. The default value is 1, meaning that
- * the RX CoS queue will be flow controlled when the A-side RX rings
- * are full.
+ * If set, this value shall represent the L2 context that matches the L2
+ * information of the decap filter.
*/
- uint8_t fc_ba;
- uint8_t unused_1[4];
+ uint16_t l2_ctxt_ref_id;
} __attribute__((packed));
-/* hwrm_cfa_pair_alloc_output (size:192b/24B) */
-struct hwrm_cfa_pair_alloc_output {
+/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
+struct hwrm_cfa_decap_filter_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Only valid for modes 1 and 2. */
- uint16_t rx_cfa_code_a;
- /* Only valid for modes 1 and 2. */
- uint16_t tx_cfa_action_a;
- /* Only valid for mode 2. */
- uint16_t rx_cfa_code_b;
- /* Only valid for mode 2. */
- uint16_t tx_cfa_action_b;
- uint8_t unused_0[7];
+ /* This value is an opaque id into CFA data structures. */
+ uint32_t decap_filter_id;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_cfa_pair_free *
- **********************/
+/******************************
+ * hwrm_cfa_decap_filter_free *
+ ******************************/
-/* hwrm_cfa_pair_free_input (size:384b/48B) */
-struct hwrm_cfa_pair_free_input {
+/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
+struct hwrm_cfa_decap_filter_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* VF Pair name (32 byte string). */
- char pair_name[32];
+ /* This value is an opaque id into CFA data structures. */
+ uint32_t decap_filter_id;
+ uint8_t unused_0[4];
} __attribute__((packed));
-/* hwrm_cfa_pair_free_output (size:128b/16B) */
-struct hwrm_cfa_pair_free_output {
+/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
+struct hwrm_cfa_decap_filter_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_cfa_pair_info *
- **********************/
+/***********************
+ * hwrm_cfa_flow_alloc *
+ ***********************/
-/* hwrm_cfa_pair_info_input (size:448b/56B) */
-struct hwrm_cfa_pair_info_input {
+/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
+struct hwrm_cfa_flow_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* If this flag is set, lookup by name else lookup by index. */
- #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
- /* If this flag is set, lookup by PF id and VF id. */
- #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
- /* Pair table index. */
- uint16_t pair_index;
- /* Pair pf index. */
- uint8_t pair_pfid;
- /* Pair vf index. */
- uint8_t pair_vfid;
- /* Pair name (32 byte string). */
- char pair_name[32];
-} __attribute__((packed));
-
-/* hwrm_cfa_pair_info_output (size:576b/72B) */
-struct hwrm_cfa_pair_info_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* Pair table index. */
- uint16_t next_pair_index;
- /* Pair member a's fid. */
- uint16_t a_fid;
- /* Logical host number. */
- uint8_t host_a_index;
- /* Logical PF number. */
- uint8_t pf_a_index;
- /* Pair member a's Linux logical VF number. */
- uint16_t vf_a_index;
- /* Rx CFA code. */
- uint16_t rx_cfa_code_a;
- /* Tx CFA action. */
- uint16_t tx_cfa_action_a;
- /* Pair member b's fid. */
- uint16_t b_fid;
- /* Logical host number. */
- uint8_t host_b_index;
- /* Logical PF number. */
- uint8_t pf_b_index;
- /* Pair member a's Linux logical VF number. */
- uint16_t vf_b_index;
- /* Rx CFA code. */
- uint16_t rx_cfa_code_b;
- /* Tx CFA action. */
- uint16_t tx_cfa_action_b;
- /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
- uint8_t pair_mode;
- /* Pair between VF on local host with PF or VF on specified host. */
- #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
- /* Pair between REP on local host with PF or VF on specified host. */
- #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
- /* Pair between REP on local host with REP on specified host. */
- #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
- /* Pair for the proxy interface. */
- #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
- /* Pair for the PF interface. */
- #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
- #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
- HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
- /* Pair state. */
- uint8_t pair_state;
- /* Pair has been allocated */
- #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
- /* Both pair members are active */
- #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
- #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
- HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
- /* Pair name (32 byte string). */
- char pair_name[32];
- uint8_t unused_0[7];
+ uint16_t flags;
+ /* tunnel is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
+ UINT32_C(0x1)
+ /* num_vlan is 2 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
+ UINT32_C(0x6)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
+ /* no tags */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
+ (UINT32_C(0x0) << 1)
+ /* 1 tag */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
+ (UINT32_C(0x1) << 1)
+ /* 2 tags */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
+ (UINT32_C(0x2) << 1)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
+ /* Enumeration denoting the Flow Type. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
+ UINT32_C(0x38)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
+ /* L2 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
+ (UINT32_C(0x0) << 3)
+ /* IPV4 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
+ (UINT32_C(0x1) << 3)
+ /* IPV6 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
+ (UINT32_C(0x2) << 3)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * when set to 1, indicates TX flow offload for function specified in src_fid and
+ * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
+ * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
+ * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
+ * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
+ * belong to the children VFs of the same PF to indicate VM to VM flow.
*/
- uint8_t valid;
-} __attribute__((packed));
-
-/**********************
- * hwrm_cfa_vfr_alloc *
- **********************/
-
-
-/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
-struct hwrm_cfa_vfr_alloc_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x40)
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * when set to 1, indicates RX flow offload for function specified in dst_fid and
+ * the src_fid should be set to invalid value.
*/
- uint16_t cmpl_ring;
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x80)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
+ * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
+ * This flag is only valid when the flow direction is RX.
*/
- uint16_t seq_id;
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
+ UINT32_C(0x100)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * Tx Flow: vf fid.
+ * Rx Flow: pf fid.
*/
- uint16_t target_id;
+ uint16_t src_fid;
+ /* Tunnel handle valid when tunnel flag is set. */
+ uint32_t tunnel_handle;
+ uint16_t action_flags;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
*/
- uint64_t resp_addr;
- /* Logical VF number (range: 0 -> MAX_VFS -1). */
- uint16_t vf_id;
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
+ UINT32_C(0x1)
+ /* recycle is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
+ UINT32_C(0x2)
/*
- * This field is reserved for the future use.
- * It shall be set to 0.
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
*/
- uint16_t reserved;
- uint8_t unused_0[4];
- /* VF Representor name (32 byte string). */
- char vfr_name[32];
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
+ UINT32_C(0x4)
+ /* meter is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
+ UINT32_C(0x8)
+ /* tunnel is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
+ UINT32_C(0x10)
+ /* nat_src is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
+ UINT32_C(0x20)
+ /* nat_dest is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
+ UINT32_C(0x40)
+ /* nat_ipv4_address is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
+ UINT32_C(0x80)
+ /* l2_header_rewrite is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
+ UINT32_C(0x100)
+ /* ttl_decrement is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
+ UINT32_C(0x200)
+ /*
+ * If set to 1 and flow direction is TX, it indicates decap of L2 header
+ * and encap of tunnel header. If set to 1 and flow direction is RX, it
+ * indicates decap of tunnel header and encap L2 header. The type of tunnel
+ * is specified in the tunnel_type field.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
+ UINT32_C(0x400)
+ /*
+ * Tx Flow: pf or vf fid.
+ * Rx Flow: vf fid.
+ */
+ uint16_t dst_fid;
+ /* VLAN tpid, valid when push_vlan flag is set. */
+ uint16_t l2_rewrite_vlan_tpid;
+ /* VLAN tci, valid when push_vlan flag is set. */
+ uint16_t l2_rewrite_vlan_tci;
+ /* Meter id, valid when meter flag is set. */
+ uint16_t act_meter_id;
+ /* Flow with the same l2 context tcam key. */
+ uint16_t ref_flow_handle;
+ /* This value sets the match value for the ethertype. */
+ uint16_t ethertype;
+ /* valid when num tags is 1 or 2. */
+ uint16_t outer_vlan_tci;
+ /* This value sets the match value for the Destination MAC address. */
+ uint16_t dmac[3];
+ /* valid when num tags is 2. */
+ uint16_t inner_vlan_tci;
+ /* This value sets the match value for the Source MAC address. */
+ uint16_t smac[3];
+ /* The bit length of destination IP address mask. */
+ uint8_t ip_dst_mask_len;
+ /* The bit length of source IP address mask. */
+ uint8_t ip_src_mask_len;
+ /* The value of destination IPv4/IPv6 address. */
+ uint32_t ip_dst[4];
+ /* The source IPv4/IPv6 address. */
+ uint32_t ip_src[4];
+ /*
+ * The value of source port.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t l4_src_port;
+ /*
+ * The value of source port mask.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t l4_src_port_mask;
+ /*
+ * The value of destination port.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t l4_dst_port;
+ /*
+ * The value of destination port mask.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t l4_dst_port_mask;
+ /*
+ * NAT IPv4/6 address based on address type flag.
+ * 0 values are ignored.
+ */
+ uint32_t nat_ip_address[4];
+ /* L2 header re-write Destination MAC address. */
+ uint16_t l2_rewrite_dmac[3];
+ /*
+ * The NAT source/destination port based on direction flag.
+ * Applies to UDP and TCP traffic.
+ * 0 values are ignored.
+ */
+ uint16_t nat_port;
+ /* L2 header re-write Source MAC address. */
+ uint16_t l2_rewrite_smac[3];
+ /* The value of ip protocol. */
+ uint8_t ip_proto;
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
} __attribute__((packed));
-/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
-struct hwrm_cfa_vfr_alloc_output {
+/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
+struct hwrm_cfa_flow_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Rx CFA code. */
- uint16_t rx_cfa_code;
- /* Tx CFA action. */
- uint16_t tx_cfa_action;
- uint8_t unused_0[3];
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[2];
+ /*
+ * This is the ID of the flow associated with this
+ * filter.
+ * This value shall be used to match and associate the
+ * flow identifier returned in completion records.
+ * A value of 0xFFFFFFFF shall indicate no flow id.
+ */
+ uint32_t flow_id;
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/*********************
- * hwrm_cfa_vfr_free *
- *********************/
+/**********************
+ * hwrm_cfa_flow_free *
+ **********************/
-/* hwrm_cfa_vfr_free_input (size:384b/48B) */
-struct hwrm_cfa_vfr_free_input {
+/* hwrm_cfa_flow_free_input (size:256b/32B) */
+struct hwrm_cfa_flow_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* VF Representor name (32 byte string). */
- char vfr_name[32];
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
} __attribute__((packed));
-/* hwrm_cfa_vfr_free_output (size:128b/16B) */
-struct hwrm_cfa_vfr_free_output {
+/* hwrm_cfa_flow_free_output (size:256b/32B) */
+struct hwrm_cfa_flow_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ /* packet is 64 b */
+ uint64_t packet;
+ /* byte is 64 b */
+ uint64_t byte;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
uint8_t valid;
} __attribute__((packed));
-/******************************
- * hwrm_tunnel_dst_port_query *
- ******************************/
+/***********************
+ * hwrm_cfa_flow_flush *
+ ***********************/
-/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
-struct hwrm_tunnel_dst_port_query_input {
+/* hwrm_cfa_flow_flush_input (size:192b/24B) */
+struct hwrm_cfa_flow_flush_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Tunnel Type. */
- uint8_t tunnel_type;
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
- UINT32_C(0x1)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
- UINT32_C(0x5)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
- UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
- #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
- UINT32_C(0xa)
- #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1
- uint8_t unused_0[7];
+ uint32_t flags;
+ uint8_t unused_0[4];
} __attribute__((packed));
-/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
-struct hwrm_tunnel_dst_port_query_output {
+/* hwrm_cfa_flow_flush_output (size:128b/16B) */
+struct hwrm_cfa_flow_flush_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /*
- * This field represents the identifier of L4 destination port
- * used for the given tunnel type. This field is valid for
- * specific tunnel types that use layer 4 (e.g. UDP)
- * transports for tunneling.
- */
- uint16_t tunnel_dst_port_id;
- /*
- * This field represents the value of L4 destination port
- * identified by tunnel_dst_port_id. This field is valid for
- * specific tunnel types that use layer 4 (e.g. UDP)
- * transports for tunneling.
- * This field is in network byte order.
- *
- * A value of 0 means that the destination port is not
- * configured.
- */
- uint16_t tunnel_dst_port_val;
- uint8_t unused_0[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/******************************
- * hwrm_tunnel_dst_port_alloc *
- ******************************/
+/***********************
+ * hwrm_cfa_flow_stats *
+ ***********************/
-/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
-struct hwrm_tunnel_dst_port_alloc_input {
+/* hwrm_cfa_flow_stats_input (size:640b/80B) */
+struct hwrm_cfa_flow_stats_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Tunnel Type. */
- uint8_t tunnel_type;
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
- UINT32_C(0x1)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
- UINT32_C(0x5)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
- UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
- #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
- UINT32_C(0xa)
- #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1
- uint8_t unused_0;
- /*
- * This field represents the value of L4 destination port used
- * for the given tunnel type. This field is valid for
- * specific tunnel types that use layer 4 (e.g. UDP)
- * transports for tunneling.
- *
- * This field is in network byte order.
- *
- * A value of 0 shall fail the command.
- */
- uint16_t tunnel_dst_port_val;
- uint8_t unused_1[4];
+ /* Flow handle. */
+ uint16_t num_flows;
+ /* Flow handle. */
+ uint16_t flow_handle_0;
+ /* Flow handle. */
+ uint16_t flow_handle_1;
+ /* Flow handle. */
+ uint16_t flow_handle_2;
+ /* Flow handle. */
+ uint16_t flow_handle_3;
+ /* Flow handle. */
+ uint16_t flow_handle_4;
+ /* Flow handle. */
+ uint16_t flow_handle_5;
+ /* Flow handle. */
+ uint16_t flow_handle_6;
+ /* Flow handle. */
+ uint16_t flow_handle_7;
+ /* Flow handle. */
+ uint16_t flow_handle_8;
+ /* Flow handle. */
+ uint16_t flow_handle_9;
+ uint8_t unused_0[2];
+ /* Flow ID of a flow. */
+ uint32_t flow_id_0;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_1;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_2;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_3;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_4;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_5;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_6;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_7;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_8;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_9;
} __attribute__((packed));
-/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
-struct hwrm_tunnel_dst_port_alloc_output {
+/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
+struct hwrm_cfa_flow_stats_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /*
- * Identifier of a tunnel L4 destination port value. Only applies to tunnel
- * types that has l4 destination port parameters.
- */
- uint16_t tunnel_dst_port_id;
- uint8_t unused_0[5];
+ /* packet_0 is 64 b */
+ uint64_t packet_0;
+ /* packet_1 is 64 b */
+ uint64_t packet_1;
+ /* packet_2 is 64 b */
+ uint64_t packet_2;
+ /* packet_3 is 64 b */
+ uint64_t packet_3;
+ /* packet_4 is 64 b */
+ uint64_t packet_4;
+ /* packet_5 is 64 b */
+ uint64_t packet_5;
+ /* packet_6 is 64 b */
+ uint64_t packet_6;
+ /* packet_7 is 64 b */
+ uint64_t packet_7;
+ /* packet_8 is 64 b */
+ uint64_t packet_8;
+ /* packet_9 is 64 b */
+ uint64_t packet_9;
+ /* byte_0 is 64 b */
+ uint64_t byte_0;
+ /* byte_1 is 64 b */
+ uint64_t byte_1;
+ /* byte_2 is 64 b */
+ uint64_t byte_2;
+ /* byte_3 is 64 b */
+ uint64_t byte_3;
+ /* byte_4 is 64 b */
+ uint64_t byte_4;
+ /* byte_5 is 64 b */
+ uint64_t byte_5;
+ /* byte_6 is 64 b */
+ uint64_t byte_6;
+ /* byte_7 is 64 b */
+ uint64_t byte_7;
+ /* byte_8 is 64 b */
+ uint64_t byte_8;
+ /* byte_9 is 64 b */
+ uint64_t byte_9;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/*****************************
- * hwrm_tunnel_dst_port_free *
- *****************************/
+/**********************
+ * hwrm_cfa_pair_info *
+ **********************/
-/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
-struct hwrm_tunnel_dst_port_free_input {
+/* hwrm_cfa_pair_info_input (size:448b/56B) */
+struct hwrm_cfa_pair_info_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Tunnel Type. */
- uint8_t tunnel_type;
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
- UINT32_C(0x1)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
- UINT32_C(0x5)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
- UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
- #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
- UINT32_C(0xa)
- #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1
- uint8_t unused_0;
- /*
- * Identifier of a tunnel L4 destination port value. Only applies to tunnel
- * types that has l4 destination port parameters.
- */
- uint16_t tunnel_dst_port_id;
- uint8_t unused_1[4];
+ uint32_t flags;
+ /* If this flag is set, lookup by name else lookup by index. */
+ #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
+ /* If this flag is set, lookup by PF id and VF id. */
+ #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
+ /* Pair table index. */
+ uint16_t pair_index;
+ /* Pair pf index. */
+ uint8_t pair_pfid;
+ /* Pair vf index. */
+ uint8_t pair_vfid;
+ /* Pair name (32 byte string). */
+ char pair_name[32];
} __attribute__((packed));
-/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
-struct hwrm_tunnel_dst_port_free_output {
+/* hwrm_cfa_pair_info_output (size:576b/72B) */
+struct hwrm_cfa_pair_info_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_1[7];
+ /* Pair table index. */
+ uint16_t next_pair_index;
+ /* Pair member a's fid. */
+ uint16_t a_fid;
+ /* Logical host number. */
+ uint8_t host_a_index;
+ /* Logical PF number. */
+ uint8_t pf_a_index;
+ /* Pair member a's Linux logical VF number. */
+ uint16_t vf_a_index;
+ /* Rx CFA code. */
+ uint16_t rx_cfa_code_a;
+ /* Tx CFA action. */
+ uint16_t tx_cfa_action_a;
+ /* Pair member b's fid. */
+ uint16_t b_fid;
+ /* Logical host number. */
+ uint8_t host_b_index;
+ /* Logical PF number. */
+ uint8_t pf_b_index;
+ /* Pair member a's Linux logical VF number. */
+ uint16_t vf_b_index;
+ /* Rx CFA code. */
+ uint16_t rx_cfa_code_b;
+ /* Tx CFA action. */
+ uint16_t tx_cfa_action_b;
+ /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
+ uint8_t pair_mode;
+ /* Pair between VF on local host with PF or VF on specified host. */
+ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
+ /* Pair between REP on local host with PF or VF on specified host. */
+ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
+ /* Pair between REP on local host with REP on specified host. */
+ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
+ /* Pair for the proxy interface. */
+ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
+ /* Pair for the PF interface. */
+ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
+ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
+ HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
+ /* Pair state. */
+ uint8_t pair_state;
+ /* Pair has been allocated */
+ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
+ /* Both pair members are active */
+ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
+ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
+ HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
+ /* Pair name (32 byte string). */
+ char pair_name[32];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/* ctx_hw_stats (size:1280b/160B) */
-struct ctx_hw_stats {
- /* Number of received unicast packets */
- uint64_t rx_ucast_pkts;
- /* Number of received multicast packets */
- uint64_t rx_mcast_pkts;
- /* Number of received broadcast packets */
- uint64_t rx_bcast_pkts;
- /* Number of discarded packets on received path */
- uint64_t rx_discard_pkts;
- /* Number of dropped packets on received path */
- uint64_t rx_drop_pkts;
- /* Number of received bytes for unicast traffic */
- uint64_t rx_ucast_bytes;
- /* Number of received bytes for multicast traffic */
- uint64_t rx_mcast_bytes;
- /* Number of received bytes for broadcast traffic */
- uint64_t rx_bcast_bytes;
- /* Number of transmitted unicast packets */
- uint64_t tx_ucast_pkts;
- /* Number of transmitted multicast packets */
- uint64_t tx_mcast_pkts;
- /* Number of transmitted broadcast packets */
- uint64_t tx_bcast_pkts;
- /* Number of discarded packets on transmit path */
- uint64_t tx_discard_pkts;
- /* Number of dropped packets on transmit path */
- uint64_t tx_drop_pkts;
- /* Number of transmitted bytes for unicast traffic */
- uint64_t tx_ucast_bytes;
- /* Number of transmitted bytes for multicast traffic */
- uint64_t tx_mcast_bytes;
- /* Number of transmitted bytes for broadcast traffic */
- uint64_t tx_bcast_bytes;
- /* Number of TPA packets */
- uint64_t tpa_pkts;
- /* Number of TPA bytes */
- uint64_t tpa_bytes;
- /* Number of TPA events */
- uint64_t tpa_events;
- /* Number of TPA aborts */
- uint64_t tpa_aborts;
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_stat_ctx_alloc *
- ***********************/
+/***************************************
+ * hwrm_cfa_redirect_query_tunnel_type *
+ ***************************************/
-/* hwrm_stat_ctx_alloc_input (size:256b/32B) */
-struct hwrm_stat_ctx_alloc_input {
+/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
+struct hwrm_cfa_redirect_query_tunnel_type_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* This is the address for statistic block. */
- uint64_t stats_dma_addr;
- /*
- * The statistic block update period in ms.
- * e.g. 250ms, 500ms, 750ms, 1000ms.
- * If update_period_ms is 0, then the stats update
- * shall be never done and the DMA address shall not be used.
- * In this case, the stat block can only be read by
- * hwrm_stat_ctx_query command.
- */
- uint32_t update_period_ms;
- /*
- * This field is used to specify statistics context specific
- * configuration flags.
- */
- uint8_t stat_ctx_flags;
- /*
- * When this bit is set to '1', the statistics context shall be
- * allocated for RoCE traffic only. In this case, traffic other
- * than offloaded RoCE traffic shall not be included in this
- * statistic context.
- * When this bit is set to '0', the statistics context shall be
- * used for the network traffic other than offloaded RoCE traffic.
- */
- #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
- uint8_t unused_0[3];
+ /* The source function id. */
+ uint16_t src_fid;
+ uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_stat_ctx_alloc_output (size:128b/16B) */
-struct hwrm_stat_ctx_alloc_output {
+/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
+struct hwrm_cfa_redirect_query_tunnel_type_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* This is the statistics context ID value. */
- uint32_t stat_ctx_id;
+ /* Tunnel Mask. */
+ uint32_t tunnel_mask;
+ /* Non-tunnel */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
+ UINT32_C(0x1)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
+ UINT32_C(0x2)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
+ UINT32_C(0x4)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
+ UINT32_C(0x8)
+ /* IP in IP */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
+ UINT32_C(0x10)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
+ UINT32_C(0x20)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
+ UINT32_C(0x40)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
+ UINT32_C(0x80)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
+ UINT32_C(0x100)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
+ UINT32_C(0x200)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
+ UINT32_C(0x400)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
+ UINT32_C(0x800)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_stat_ctx_free *
- **********************/
+/******************************
+ * hwrm_tunnel_dst_port_query *
+ ******************************/
-/* hwrm_stat_ctx_free_input (size:192b/24B) */
-struct hwrm_stat_ctx_free_input {
+/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
+struct hwrm_tunnel_dst_port_query_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* ID of the statistics context that is being queried. */
- uint32_t stat_ctx_id;
- uint8_t unused_0[4];
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1
+ uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_stat_ctx_free_output (size:128b/16B) */
-struct hwrm_stat_ctx_free_output {
+/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
+struct hwrm_tunnel_dst_port_query_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* This is the statistics context ID value. */
- uint32_t stat_ctx_id;
+ /*
+ * This field represents the identifier of L4 destination port
+ * used for the given tunnel type. This field is valid for
+ * specific tunnel types that use layer 4 (e.g. UDP)
+ * transports for tunneling.
+ */
+ uint16_t tunnel_dst_port_id;
+ /*
+ * This field represents the value of L4 destination port
+ * identified by tunnel_dst_port_id. This field is valid for
+ * specific tunnel types that use layer 4 (e.g. UDP)
+ * transports for tunneling.
+ * This field is in network byte order.
+ *
+ * A value of 0 means that the destination port is not
+ * configured.
+ */
+ uint16_t tunnel_dst_port_val;
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_stat_ctx_query *
- ***********************/
+/******************************
+ * hwrm_tunnel_dst_port_alloc *
+ ******************************/
-/* hwrm_stat_ctx_query_input (size:192b/24B) */
-struct hwrm_stat_ctx_query_input {
+/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
+struct hwrm_tunnel_dst_port_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* ID of the statistics context that is being queried. */
- uint32_t stat_ctx_id;
- uint8_t unused_0[4];
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1
+ uint8_t unused_0;
+ /*
+ * This field represents the value of L4 destination port used
+ * for the given tunnel type. This field is valid for
+ * specific tunnel types that use layer 4 (e.g. UDP)
+ * transports for tunneling.
+ *
+ * This field is in network byte order.
+ *
+ * A value of 0 shall fail the command.
+ */
+ uint16_t tunnel_dst_port_val;
+ uint8_t unused_1[4];
} __attribute__((packed));
-/* hwrm_stat_ctx_query_output (size:1408b/176B) */
-struct hwrm_stat_ctx_query_output {
+/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
+struct hwrm_tunnel_dst_port_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Number of transmitted unicast packets */
- uint64_t tx_ucast_pkts;
- /* Number of transmitted multicast packets */
- uint64_t tx_mcast_pkts;
- /* Number of transmitted broadcast packets */
- uint64_t tx_bcast_pkts;
- /* Number of transmitted packets with error */
- uint64_t tx_err_pkts;
- /* Number of dropped packets on transmit path */
- uint64_t tx_drop_pkts;
- /* Number of transmitted bytes for unicast traffic */
- uint64_t tx_ucast_bytes;
- /* Number of transmitted bytes for multicast traffic */
- uint64_t tx_mcast_bytes;
- /* Number of transmitted bytes for broadcast traffic */
- uint64_t tx_bcast_bytes;
- /* Number of received unicast packets */
- uint64_t rx_ucast_pkts;
- /* Number of received multicast packets */
- uint64_t rx_mcast_pkts;
- /* Number of received broadcast packets */
- uint64_t rx_bcast_pkts;
- /* Number of received packets with error */
- uint64_t rx_err_pkts;
- /* Number of dropped packets on received path */
- uint64_t rx_drop_pkts;
- /* Number of received bytes for unicast traffic */
- uint64_t rx_ucast_bytes;
- /* Number of received bytes for multicast traffic */
- uint64_t rx_mcast_bytes;
- /* Number of received bytes for broadcast traffic */
- uint64_t rx_bcast_bytes;
- /* Number of aggregated unicast packets */
- uint64_t rx_agg_pkts;
- /* Number of aggregated unicast bytes */
- uint64_t rx_agg_bytes;
- /* Number of aggregation events */
- uint64_t rx_agg_events;
- /* Number of aborted aggregations */
- uint64_t rx_agg_aborts;
- uint8_t unused_0[7];
+ /*
+ * Identifier of a tunnel L4 destination port value. Only applies to tunnel
+ * types that has l4 destination port parameters.
+ */
+ uint16_t tunnel_dst_port_id;
+ uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/***************************
- * hwrm_stat_ctx_clr_stats *
- ***************************/
+/*****************************
+ * hwrm_tunnel_dst_port_free *
+ *****************************/
-/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
-struct hwrm_stat_ctx_clr_stats_input {
+/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
+struct hwrm_tunnel_dst_port_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* ID of the statistics context that is being queried. */
- uint32_t stat_ctx_id;
- uint8_t unused_0[4];
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1
+ uint8_t unused_0;
+ /*
+ * Identifier of a tunnel L4 destination port value. Only applies to tunnel
+ * types that has l4 destination port parameters.
+ */
+ uint16_t tunnel_dst_port_id;
+ uint8_t unused_1[4];
} __attribute__((packed));
-
-/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
-struct hwrm_stat_ctx_clr_stats_output {
+
+/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
+struct hwrm_tunnel_dst_port_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
-/********************
- * hwrm_pcie_qstats *
- ********************/
+/* Periodic statistics context DMA to host. */
+/* ctx_hw_stats (size:1280b/160B) */
+struct ctx_hw_stats {
+ /* Number of received unicast packets */
+ uint64_t rx_ucast_pkts;
+ /* Number of received multicast packets */
+ uint64_t rx_mcast_pkts;
+ /* Number of received broadcast packets */
+ uint64_t rx_bcast_pkts;
+ /* Number of discarded packets on received path */
+ uint64_t rx_discard_pkts;
+ /* Number of dropped packets on received path */
+ uint64_t rx_drop_pkts;
+ /* Number of received bytes for unicast traffic */
+ uint64_t rx_ucast_bytes;
+ /* Number of received bytes for multicast traffic */
+ uint64_t rx_mcast_bytes;
+ /* Number of received bytes for broadcast traffic */
+ uint64_t rx_bcast_bytes;
+ /* Number of transmitted unicast packets */
+ uint64_t tx_ucast_pkts;
+ /* Number of transmitted multicast packets */
+ uint64_t tx_mcast_pkts;
+ /* Number of transmitted broadcast packets */
+ uint64_t tx_bcast_pkts;
+ /* Number of discarded packets on transmit path */
+ uint64_t tx_discard_pkts;
+ /* Number of dropped packets on transmit path */
+ uint64_t tx_drop_pkts;
+ /* Number of transmitted bytes for unicast traffic */
+ uint64_t tx_ucast_bytes;
+ /* Number of transmitted bytes for multicast traffic */
+ uint64_t tx_mcast_bytes;
+ /* Number of transmitted bytes for broadcast traffic */
+ uint64_t tx_bcast_bytes;
+ /* Number of TPA packets */
+ uint64_t tpa_pkts;
+ /* Number of TPA bytes */
+ uint64_t tpa_bytes;
+ /* Number of TPA events */
+ uint64_t tpa_events;
+ /* Number of TPA aborts */
+ uint64_t tpa_aborts;
+} __attribute__((packed));
+/***********************
+ * hwrm_stat_ctx_alloc *
+ ***********************/
-/* hwrm_pcie_qstats_input (size:256b/32B) */
-struct hwrm_pcie_qstats_input {
+
+/* hwrm_stat_ctx_alloc_input (size:256b/32B) */
+struct hwrm_stat_ctx_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ /* This is the address for statistic block. */
+ uint64_t stats_dma_addr;
/*
- * The size of PCIe statistics block in bytes.
- * Firmware will DMA the PCIe statistics to
- * the host with this field size in the response.
- */
- uint16_t pcie_stat_size;
- uint8_t unused_0[6];
- /*
- * This is the host address where
- * PCIe statistics will be stored
- */
- uint64_t pcie_stat_host_addr;
-} __attribute__((packed));
-
-/* hwrm_pcie_qstats_output (size:128b/16B) */
-struct hwrm_pcie_qstats_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* The size of PCIe statistics block in bytes. */
- uint16_t pcie_stat_size;
- uint8_t unused_0[5];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/* Port Tx Statistics Formats */
-/* tx_port_stats (size:3264b/408B) */
-struct tx_port_stats {
- /* Total Number of 64 Bytes frames transmitted */
- uint64_t tx_64b_frames;
- /* Total Number of 65-127 Bytes frames transmitted */
- uint64_t tx_65b_127b_frames;
- /* Total Number of 128-255 Bytes frames transmitted */
- uint64_t tx_128b_255b_frames;
- /* Total Number of 256-511 Bytes frames transmitted */
- uint64_t tx_256b_511b_frames;
- /* Total Number of 512-1023 Bytes frames transmitted */
- uint64_t tx_512b_1023b_frames;
- /* Total Number of 1024-1518 Bytes frames transmitted */
- uint64_t tx_1024b_1518_frames;
- /*
- * Total Number of each good VLAN (exludes FCS errors)
- * frame transmitted which is 1519 to 1522 bytes in length
- * inclusive (excluding framing bits but including FCS bytes).
- */
- uint64_t tx_good_vlan_frames;
- /* Total Number of 1519-2047 Bytes frames transmitted */
- uint64_t tx_1519b_2047_frames;
- /* Total Number of 2048-4095 Bytes frames transmitted */
- uint64_t tx_2048b_4095b_frames;
- /* Total Number of 4096-9216 Bytes frames transmitted */
- uint64_t tx_4096b_9216b_frames;
- /* Total Number of 9217-16383 Bytes frames transmitted */
- uint64_t tx_9217b_16383b_frames;
- /* Total Number of good frames transmitted */
- uint64_t tx_good_frames;
- /* Total Number of frames transmitted */
- uint64_t tx_total_frames;
- /* Total number of unicast frames transmitted */
- uint64_t tx_ucast_frames;
- /* Total number of multicast frames transmitted */
- uint64_t tx_mcast_frames;
- /* Total number of broadcast frames transmitted */
- uint64_t tx_bcast_frames;
- /* Total number of PAUSE control frames transmitted */
- uint64_t tx_pause_frames;
- /*
- * Total number of PFC/per-priority PAUSE
- * control frames transmitted
- */
- uint64_t tx_pfc_frames;
- /* Total number of jabber frames transmitted */
- uint64_t tx_jabber_frames;
- /* Total number of frames transmitted with FCS error */
- uint64_t tx_fcs_err_frames;
- /* Total number of control frames transmitted */
- uint64_t tx_control_frames;
- /* Total number of over-sized frames transmitted */
- uint64_t tx_oversz_frames;
- /* Total number of frames with single deferral */
- uint64_t tx_single_dfrl_frames;
- /* Total number of frames with multiple deferrals */
- uint64_t tx_multi_dfrl_frames;
- /* Total number of frames with single collision */
- uint64_t tx_single_coll_frames;
- /* Total number of frames with multiple collisions */
- uint64_t tx_multi_coll_frames;
- /* Total number of frames with late collisions */
- uint64_t tx_late_coll_frames;
- /* Total number of frames with excessive collisions */
- uint64_t tx_excessive_coll_frames;
- /* Total number of fragmented frames transmitted */
- uint64_t tx_frag_frames;
- /* Total number of transmit errors */
- uint64_t tx_err;
- /* Total number of single VLAN tagged frames transmitted */
- uint64_t tx_tagged_frames;
- /* Total number of double VLAN tagged frames transmitted */
- uint64_t tx_dbl_tagged_frames;
- /* Total number of runt frames transmitted */
- uint64_t tx_runt_frames;
- /* Total number of TX FIFO under runs */
- uint64_t tx_fifo_underruns;
- /*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 0 transmitted
- */
- uint64_t tx_pfc_ena_frames_pri0;
- /*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 1 transmitted
- */
- uint64_t tx_pfc_ena_frames_pri1;
- /*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 2 transmitted
- */
- uint64_t tx_pfc_ena_frames_pri2;
- /*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 3 transmitted
- */
- uint64_t tx_pfc_ena_frames_pri3;
- /*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 4 transmitted
- */
- uint64_t tx_pfc_ena_frames_pri4;
- /*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 5 transmitted
- */
- uint64_t tx_pfc_ena_frames_pri5;
- /*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 6 transmitted
- */
- uint64_t tx_pfc_ena_frames_pri6;
- /*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 7 transmitted
- */
- uint64_t tx_pfc_ena_frames_pri7;
- /* Total number of EEE LPI Events on TX */
- uint64_t tx_eee_lpi_events;
- /* EEE LPI Duration Counter on TX */
- uint64_t tx_eee_lpi_duration;
- /*
- * Total number of Link Level Flow Control (LLFC) messages
- * transmitted
+ * The statistic block update period in ms.
+ * e.g. 250ms, 500ms, 750ms, 1000ms.
+ * If update_period_ms is 0, then the stats update
+ * shall be never done and the DMA address shall not be used.
+ * In this case, the stat block can only be read by
+ * hwrm_stat_ctx_query command.
*/
- uint64_t tx_llfc_logical_msgs;
- /* Total number of HCFC messages transmitted */
- uint64_t tx_hcfc_msgs;
- /* Total number of TX collisions */
- uint64_t tx_total_collisions;
- /* Total number of transmitted bytes */
- uint64_t tx_bytes;
- /* Total number of end-to-end HOL frames */
- uint64_t tx_xthol_frames;
- /* Total Tx Drops per Port reported by STATS block */
- uint64_t tx_stat_discard;
- /* Total Tx Error Drops per Port reported by STATS block */
- uint64_t tx_stat_error;
-} __attribute__((packed));
-
-/* Port Rx Statistics Formats */
-/* rx_port_stats (size:4224b/528B) */
-struct rx_port_stats {
- /* Total Number of 64 Bytes frames received */
- uint64_t rx_64b_frames;
- /* Total Number of 65-127 Bytes frames received */
- uint64_t rx_65b_127b_frames;
- /* Total Number of 128-255 Bytes frames received */
- uint64_t rx_128b_255b_frames;
- /* Total Number of 256-511 Bytes frames received */
- uint64_t rx_256b_511b_frames;
- /* Total Number of 512-1023 Bytes frames received */
- uint64_t rx_512b_1023b_frames;
- /* Total Number of 1024-1518 Bytes frames received */
- uint64_t rx_1024b_1518_frames;
+ uint32_t update_period_ms;
/*
- * Total Number of each good VLAN (exludes FCS errors)
- * frame received which is 1519 to 1522 bytes in length
- * inclusive (excluding framing bits but including FCS bytes).
+ * This field is used to specify statistics context specific
+ * configuration flags.
*/
- uint64_t rx_good_vlan_frames;
- /* Total Number of 1519-2047 Bytes frames received */
- uint64_t rx_1519b_2047b_frames;
- /* Total Number of 2048-4095 Bytes frames received */
- uint64_t rx_2048b_4095b_frames;
- /* Total Number of 4096-9216 Bytes frames received */
- uint64_t rx_4096b_9216b_frames;
- /* Total Number of 9217-16383 Bytes frames received */
- uint64_t rx_9217b_16383b_frames;
- /* Total number of frames received */
- uint64_t rx_total_frames;
- /* Total number of unicast frames received */
- uint64_t rx_ucast_frames;
- /* Total number of multicast frames received */
- uint64_t rx_mcast_frames;
- /* Total number of broadcast frames received */
- uint64_t rx_bcast_frames;
- /* Total number of received frames with FCS error */
- uint64_t rx_fcs_err_frames;
- /* Total number of control frames received */
- uint64_t rx_ctrl_frames;
- /* Total number of PAUSE frames received */
- uint64_t rx_pause_frames;
- /* Total number of PFC frames received */
- uint64_t rx_pfc_frames;
+ uint8_t stat_ctx_flags;
/*
- * Total number of frames received with an unsupported
- * opcode
+ * When this bit is set to '1', the statistics context shall be
+ * allocated for RoCE traffic only. In this case, traffic other
+ * than offloaded RoCE traffic shall not be included in this
+ * statistic context.
+ * When this bit is set to '0', the statistics context shall be
+ * used for the network traffic other than offloaded RoCE traffic.
*/
- uint64_t rx_unsupported_opcode_frames;
+ #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
+ uint8_t unused_0[3];
+} __attribute__((packed));
+
+/* hwrm_stat_ctx_alloc_output (size:128b/16B) */
+struct hwrm_stat_ctx_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This is the statistics context ID value. */
+ uint32_t stat_ctx_id;
+ uint8_t unused_0[3];
/*
- * Total number of frames received with an unsupported
- * DA for pause and PFC
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint64_t rx_unsupported_da_pausepfc_frames;
- /* Total number of frames received with an unsupported SA */
- uint64_t rx_wrong_sa_frames;
- /* Total number of received packets with alignment error */
- uint64_t rx_align_err_frames;
- /* Total number of received frames with out-of-range length */
- uint64_t rx_oor_len_frames;
- /* Total number of received frames with error termination */
- uint64_t rx_code_err_frames;
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_stat_ctx_free *
+ **********************/
+
+
+/* hwrm_stat_ctx_free_input (size:192b/24B) */
+struct hwrm_stat_ctx_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * Total number of received frames with a false carrier is
- * detected during idle, as defined by RX_ER samples active
- * and RXD is 0xE. The event is reported along with the
- * statistics generated on the next received frame. Only
- * one false carrier condition can be detected and logged
- * between frames.
- *
- * Carrier event, valid for 10M/100M speed modes only.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint64_t rx_false_carrier_frames;
- /* Total number of over-sized frames received */
- uint64_t rx_ovrsz_frames;
- /* Total number of jabber packets received */
- uint64_t rx_jbr_frames;
- /* Total number of received frames with MTU error */
- uint64_t rx_mtu_err_frames;
- /* Total number of received frames with CRC match */
- uint64_t rx_match_crc_frames;
- /* Total number of frames received promiscuously */
- uint64_t rx_promiscuous_frames;
+ uint16_t cmpl_ring;
/*
- * Total number of received frames with one or two VLAN
- * tags
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint64_t rx_tagged_frames;
- /* Total number of received frames with two VLAN tags */
- uint64_t rx_double_tagged_frames;
- /* Total number of truncated frames received */
- uint64_t rx_trunc_frames;
- /* Total number of good frames (without errors) received */
- uint64_t rx_good_frames;
+ uint16_t seq_id;
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 0
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint64_t rx_pfc_xon2xoff_frames_pri0;
+ uint16_t target_id;
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 1
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint64_t rx_pfc_xon2xoff_frames_pri1;
+ uint64_t resp_addr;
+ /* ID of the statistics context that is being queried. */
+ uint32_t stat_ctx_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_stat_ctx_free_output (size:128b/16B) */
+struct hwrm_stat_ctx_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This is the statistics context ID value. */
+ uint32_t stat_ctx_id;
+ uint8_t unused_0[3];
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 2
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint64_t rx_pfc_xon2xoff_frames_pri2;
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_stat_ctx_query *
+ ***********************/
+
+
+/* hwrm_stat_ctx_query_input (size:192b/24B) */
+struct hwrm_stat_ctx_query_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 3
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint64_t rx_pfc_xon2xoff_frames_pri3;
+ uint16_t cmpl_ring;
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 4
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint64_t rx_pfc_xon2xoff_frames_pri4;
+ uint16_t seq_id;
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 5
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint64_t rx_pfc_xon2xoff_frames_pri5;
+ uint16_t target_id;
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 6
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint64_t rx_pfc_xon2xoff_frames_pri6;
+ uint64_t resp_addr;
+ /* ID of the statistics context that is being queried. */
+ uint32_t stat_ctx_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_stat_ctx_query_output (size:1408b/176B) */
+struct hwrm_stat_ctx_query_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Number of transmitted unicast packets */
+ uint64_t tx_ucast_pkts;
+ /* Number of transmitted multicast packets */
+ uint64_t tx_mcast_pkts;
+ /* Number of transmitted broadcast packets */
+ uint64_t tx_bcast_pkts;
+ /* Number of transmitted packets with error */
+ uint64_t tx_err_pkts;
+ /* Number of dropped packets on transmit path */
+ uint64_t tx_drop_pkts;
+ /* Number of transmitted bytes for unicast traffic */
+ uint64_t tx_ucast_bytes;
+ /* Number of transmitted bytes for multicast traffic */
+ uint64_t tx_mcast_bytes;
+ /* Number of transmitted bytes for broadcast traffic */
+ uint64_t tx_bcast_bytes;
+ /* Number of received unicast packets */
+ uint64_t rx_ucast_pkts;
+ /* Number of received multicast packets */
+ uint64_t rx_mcast_pkts;
+ /* Number of received broadcast packets */
+ uint64_t rx_bcast_pkts;
+ /* Number of received packets with error */
+ uint64_t rx_err_pkts;
+ /* Number of dropped packets on received path */
+ uint64_t rx_drop_pkts;
+ /* Number of received bytes for unicast traffic */
+ uint64_t rx_ucast_bytes;
+ /* Number of received bytes for multicast traffic */
+ uint64_t rx_mcast_bytes;
+ /* Number of received bytes for broadcast traffic */
+ uint64_t rx_bcast_bytes;
+ /* Number of aggregated unicast packets */
+ uint64_t rx_agg_pkts;
+ /* Number of aggregated unicast bytes */
+ uint64_t rx_agg_bytes;
+ /* Number of aggregation events */
+ uint64_t rx_agg_events;
+ /* Number of aborted aggregations */
+ uint64_t rx_agg_aborts;
+ uint8_t unused_0[7];
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 7
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint64_t rx_pfc_xon2xoff_frames_pri7;
+ uint8_t valid;
+} __attribute__((packed));
+
+/***************************
+ * hwrm_stat_ctx_clr_stats *
+ ***************************/
+
+
+/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
+struct hwrm_stat_ctx_clr_stats_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 0
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint64_t rx_pfc_ena_frames_pri0;
+ uint16_t cmpl_ring;
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 1
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint64_t rx_pfc_ena_frames_pri1;
+ uint16_t seq_id;
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 2
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint64_t rx_pfc_ena_frames_pri2;
+ uint16_t target_id;
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 3
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint64_t rx_pfc_ena_frames_pri3;
+ uint64_t resp_addr;
+ /* ID of the statistics context that is being queried. */
+ uint32_t stat_ctx_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
+struct hwrm_stat_ctx_clr_stats_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 4
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint64_t rx_pfc_ena_frames_pri4;
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************
+ * hwrm_pcie_qstats *
+ ********************/
+
+
+/* hwrm_pcie_qstats_input (size:256b/32B) */
+struct hwrm_pcie_qstats_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 5
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint64_t rx_pfc_ena_frames_pri5;
+ uint16_t cmpl_ring;
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 6
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint64_t rx_pfc_ena_frames_pri6;
+ uint16_t seq_id;
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 7
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint64_t rx_pfc_ena_frames_pri7;
- /* Total Number of frames received with SCH CRC error */
- uint64_t rx_sch_crc_err_frames;
- /* Total Number of under-sized frames received */
- uint64_t rx_undrsz_frames;
- /* Total Number of fragmented frames received */
- uint64_t rx_frag_frames;
- /* Total number of RX EEE LPI Events */
- uint64_t rx_eee_lpi_events;
- /* EEE LPI Duration Counter on RX */
- uint64_t rx_eee_lpi_duration;
+ uint16_t target_id;
/*
- * Total number of physical type Link Level Flow Control
- * (LLFC) messages received
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint64_t rx_llfc_physical_msgs;
+ uint64_t resp_addr;
/*
- * Total number of logical type Link Level Flow Control
- * (LLFC) messages received
+ * The size of PCIe statistics block in bytes.
+ * Firmware will DMA the PCIe statistics to
+ * the host with this field size in the response.
*/
- uint64_t rx_llfc_logical_msgs;
+ uint16_t pcie_stat_size;
+ uint8_t unused_0[6];
/*
- * Total number of logical type Link Level Flow Control
- * (LLFC) messages received with CRC error
+ * This is the host address where
+ * PCIe statistics will be stored
*/
- uint64_t rx_llfc_msgs_with_crc_err;
- /* Total number of HCFC messages received */
- uint64_t rx_hcfc_msgs;
- /* Total number of HCFC messages received with CRC error */
- uint64_t rx_hcfc_msgs_with_crc_err;
- /* Total number of received bytes */
- uint64_t rx_bytes;
- /* Total number of bytes received in runt frames */
- uint64_t rx_runt_bytes;
- /* Total number of runt frames received */
- uint64_t rx_runt_frames;
- /* Total Rx Discards per Port reported by STATS block */
- uint64_t rx_stat_discard;
- uint64_t rx_stat_err;
+ uint64_t pcie_stat_host_addr;
} __attribute__((packed));
-/* Port Rx Statistics extended Formats */
-/* rx_port_stats_ext (size:320b/40B) */
-struct rx_port_stats_ext {
- /* Number of times link state changed to down */
- uint64_t link_down_events;
- /* Number of times the idle rings with pause bit are found */
- uint64_t continuous_pause_events;
- /* Number of times the active rings pause bit resumed back */
- uint64_t resume_pause_events;
- /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
- uint64_t continuous_roce_pause_events;
- /* Number of times, the ROCE cos queue PFC is enabled back */
- uint64_t resume_roce_pause_events;
+/* hwrm_pcie_qstats_output (size:128b/16B) */
+struct hwrm_pcie_qstats_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The size of PCIe statistics block in bytes. */
+ uint16_t pcie_stat_size;
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
} __attribute__((packed));
/* PCIe Statistics Formats */
uint8_t unused_0[7];
} __attribute__((packed));
-/*****************************
- * hwrm_nvm_factory_defaults *
- *****************************/
-
-
-/* hwrm_nvm_factory_defaults_input (size:192b/24B) */
-struct hwrm_nvm_factory_defaults_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- /* mode is 8 b */
- uint8_t mode;
- /* If set to 1, it will trigger restoration of factory default settings */
- #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_RESTORE UINT32_C(0x0)
- /* If set to 1, it will trigger creation of factory default settings */
- #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE UINT32_C(0x1)
- #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_LAST \
- HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE
- uint8_t unused_0[7];
-} __attribute__((packed));
-
-/* hwrm_nvm_factory_defaults_output (size:128b/16B) */
-struct hwrm_nvm_factory_defaults_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t result;
- /* factory defaults created successfully. */
- #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_OK \
- UINT32_C(0x0)
- /* factory defaults restored successfully. */
- #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_RESTORE_OK \
- UINT32_C(0x1)
- /* factory defaults already created. */
- #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY \
- UINT32_C(0x2)
- #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_LAST \
- HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY
- uint8_t unused_0[6];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __attribute__((packed));
-
-/* hwrm_nvm_factory_defaults_cmd_err (size:64b/8B) */
-struct hwrm_nvm_factory_defaults_cmd_err {
- /*
- * command specific error codes that goes to
- * the cmd_err field in Common HWRM Error Response.
- */
- uint8_t code;
- /* Unknown error */
- #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN \
- UINT32_C(0x0)
- /* valid configuration not present to create defaults */
- #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG \
- UINT32_C(0x1)
- /* No saved configuration present to restore, restore failed */
- #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG \
- UINT32_C(0x2)
- #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_LAST \
- HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG
- uint8_t unused_0[7];
-} __attribute__((packed));
-
#endif /* _HSI_STRUCT_DEF_DPDK_H_ */
Code Review / deb_dpdk.git / blobdiff