/* word 1 : */
/* ethernet control
- * 3:0 : l3_proto_idx - L3 protocol, if
- * tunnel_ctrl[0] is set, then this is the inner
- * packet L3. This field required when
- * l3_csum_en,l3_csum or tso_en are set.
+ * 3:0 : l3_proto_idx - L3 protocol. This field
+ * required when l3_csum_en,l3_csum or tso_en are set.
* 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and
* DF flags of the IPv4 header is 0. Otherwise must
* be set to 1
* 6:5 : reserved5
- * 7 : tso_en - Enable TSO, For TCP only. For packets
- * with tunnel (tunnel_ctrl[0]=1), then the inner
- * packet will be segmented while the outer tunnel is
- * duplicated
- * 12:8 : l4_proto_idx - L4 protocol, if
- * tunnel_ctrl[0] is set, then this is the inner
- * packet L4. This field need to be set when
- * l4_csum_en or tso_en are set.
- * 13 : l3_csum_en - enable IPv4 header checksum. if
- * tunnel_ctrl[0] is set, then this will enable
- * checksum for the inner packet IPv4
- * 14 : l4_csum_en - enable TCP/UDP checksum. if
- * tunnel_ctrl[0] is set, then this will enable
- * checksum on the inner packet TCP/UDP checksum
+ * 7 : tso_en - Enable TSO, For TCP only.
+ * 12:8 : l4_proto_idx - L4 protocol. This field need
+ * to be set when l4_csum_en or tso_en are set.
+ * 13 : l3_csum_en - enable IPv4 header checksum.
+ * 14 : l4_csum_en - enable TCP/UDP checksum.
* 15 : ethernet_fcs_dis - when set, the controller
* will not append the 802.3 Ethernet Frame Check
* Sequence to the packet
* must not include the tcp length field. L4 partial
* checksum should be used for IPv6 packet that
* contains Routing Headers.
- * 20:18 : tunnel_ctrl - Bit 0: tunneling exists, Bit
- * 1: tunnel packet actually uses UDP as L4, Bit 2:
- * tunnel packet L3 protocol: 0: IPv4 1: IPv6
- * 21 : ts_req - Indicates that the packet is IEEE
- * 1588v2 packet requiring the timestamp
+ * 20:18 : reserved18 - MBZ
+ * 21 : reserved21 - MBZ
* 31:22 : req_id_lo - Request ID[9:0]
*/
uint32_t meta_ctrl;
/* word 0 : */
/* length, request id and control flags
* 9:0 : req_id_lo - Request ID[9:0]
- * 11:10 : outr_l3_off_hi - valid if
- * tunnel_ctrl[0]=1. bits[4:3] of outer packet L3
- * offset
+ * 11:10 : reserved10 - MBZ
* 12 : reserved12 - MBZ
* 13 : reserved13 - MBZ
* 14 : ext_valid - if set, offset fields in Word2
/* word 2 : */
/* word 2
* 7:0 : l3_hdr_len - the header length L3 IP header.
- * if tunnel_ctrl[0]=1, this is the IP header length
- * of the inner packet. FIXME - check if includes IP
- * options hdr_len
* 15:8 : l3_hdr_off - the offset of the first byte
* in the L3 header from the beginning of the to-be
- * transmitted packet. if tunnel_ctrl[0]=1, this is
- * the offset the L3 header of the inner packet
+ * transmitted packet.
* 21:16 : l4_hdr_len_in_words - counts the L4 header
* length in words. there is an explicit assumption
* that L4 header appears right after L3 header and
- * L4 offset is based on l3_hdr_off+l3_hdr_len FIXME
- * - pls confirm
+ * L4 offset is based on l3_hdr_off+l3_hdr_len
* 31:22 : mss_lo
*/
uint32_t word2;
/* word 3 : */
- /* word 3
- * 23:0 : crypto_info
- * 28:24 : outr_l3_hdr_len_words - valid if
- * tunnel_ctrl[0]=1. Counts in words
- * 31:29 : outr_l3_off_lo - valid if
- * tunnel_ctrl[0]=1. bits[2:0] of outer packet L3
- * offset. Counts the offset of the tunnel IP header
- * from beginning of the packet. NOTE: if the tunnel
- * header requires CRC or checksum, it is expected to
- * be done by the driver as it is not done by the HW
- */
- uint32_t word3;
+ uint32_t reserved;
};
/* ENA IO Queue Tx completions descriptor */
/* word 0 : */
/* 4:0 : l3_proto_idx - L3 protocol index
* 6:5 : src_vlan_cnt - Source VLAN count
- * 7 : tunnel - Tunnel exists
+ * 7 : reserved7 - MBZ
* 12:8 : l4_proto_idx - L4 protocol index
* 13 : l3_csum_err - when set, either the L3
* checksum error detected, or, the controller didn't
- * validate the checksum, If tunnel exists, this
- * result is for the inner packet. This bit is valid
- * only when l3_proto_idx indicates IPv4 packet
+ * validate the checksum. This bit is valid only when
+ * l3_proto_idx indicates IPv4 packet
* 14 : l4_csum_err - when set, either the L4
* checksum error detected, or, the controller didn't
- * validate the checksum. If tunnel exists, this
- * result is for the inner packet. This bit is valid
- * only when l4_proto_idx indicates TCP/UDP packet,
- * and, ipv4_frag is not set
+ * validate the checksum. This bit is valid only when
+ * l4_proto_idx indicates TCP/UDP packet, and,
+ * ipv4_frag is not set
* 15 : ipv4_frag - Indicates IPv4 fragmented packet
- * 17:16 : reserved16
- * 19:18 : reserved18
- * 20 : secured_pkt - Set if packet was handled by
- * inline crypto engine
- * 22:21 : crypto_status - bit 0 secured direction:
- * 0: decryption, 1: encryption. bit 1 reserved
- * 23 : reserved23
+ * 23:16 : reserved16
* 24 : phase
* 25 : l3_csum2 - second checksum engine result
* 26 : first - Indicates first descriptor in
* transaction
* 27 : last - Indicates last descriptor in
* transaction
- * 28 : inr_l4_csum - TCP/UDP checksum results for
- * inner packet
- * 29 : reserved29
+ * 29:28 : reserved28
* 30 : buffer - 0: Metadata descriptor. 1: Buffer
* Descriptor was used
* 31 : reserved31
uint32_t intr_control;
};
+/* ENA NUMA Node configuration register */
+struct ena_eth_io_numa_node_cfg_reg {
+ /* word 0 : */
+ /* 7:0 : numa
+ * 30:8 : reserved
+ * 31 : enabled
+ */
+ uint32_t numa_cfg;
+};
+
/* tx_desc */
#define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
-#define ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_SHIFT 18
-#define ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_MASK GENMASK(20, 18)
-#define ENA_ETH_IO_TX_DESC_TS_REQ_SHIFT 21
-#define ENA_ETH_IO_TX_DESC_TS_REQ_MASK BIT(21)
#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
/* tx_meta_desc */
#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
-#define ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_SHIFT 10
-#define ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_MASK GENMASK(11, 10)
#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
#define ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT 15
#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
-#define ENA_ETH_IO_TX_META_DESC_CRYPTO_INFO_MASK GENMASK(23, 0)
-#define ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_SHIFT 24
-#define ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_MASK GENMASK(28, 24)
-#define ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_SHIFT 29
-#define ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_MASK GENMASK(31, 29)
/* tx_cdesc */
#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
-#define ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_SHIFT 7
-#define ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_MASK BIT(7)
#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
-#define ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_SHIFT 20
-#define ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_MASK BIT(20)
-#define ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_SHIFT 21
-#define ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_MASK GENMASK(22, 21)
#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
-#define ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_SHIFT 28
-#define ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_MASK BIT(28)
#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
+/* numa_node_cfg_reg */
+#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
+#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
+#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
+
#if !defined(ENA_DEFS_LINUX_MAINLINE)
static inline uint32_t get_ena_eth_io_tx_desc_length(
const struct ena_eth_io_tx_desc *p)
& ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK;
}
-static inline uint32_t get_ena_eth_io_tx_desc_tunnel_ctrl(
- const struct ena_eth_io_tx_desc *p)
-{
- return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_MASK)
- >> ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_SHIFT;
-}
-
-static inline void set_ena_eth_io_tx_desc_tunnel_ctrl(
- struct ena_eth_io_tx_desc *p,
- uint32_t val)
-{
- p->meta_ctrl |=
- (val << ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_SHIFT)
- & ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_MASK;
-}
-
-static inline uint32_t get_ena_eth_io_tx_desc_ts_req(
- const struct ena_eth_io_tx_desc *p)
-{
- return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TS_REQ_MASK)
- >> ENA_ETH_IO_TX_DESC_TS_REQ_SHIFT;
-}
-
-static inline void set_ena_eth_io_tx_desc_ts_req(
- struct ena_eth_io_tx_desc *p,
- uint32_t val)
-{
- p->meta_ctrl |=
- (val << ENA_ETH_IO_TX_DESC_TS_REQ_SHIFT)
- & ENA_ETH_IO_TX_DESC_TS_REQ_MASK;
-}
-
static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(
const struct ena_eth_io_tx_desc *p)
{
}
static inline void set_ena_eth_io_tx_desc_req_id_lo(
- struct ena_eth_io_tx_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_desc *p, uint32_t val)
{
- p->meta_ctrl |=
- (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT)
+ p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT)
& ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;
}
p->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK;
}
-static inline uint32_t get_ena_eth_io_tx_meta_desc_outr_l3_off_hi(
- const struct ena_eth_io_tx_meta_desc *p)
-{
- return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_MASK)
- >> ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_SHIFT;
-}
-
-static inline void set_ena_eth_io_tx_meta_desc_outr_l3_off_hi(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
-{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_SHIFT)
- & ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_MASK;
-}
-
static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(
const struct ena_eth_io_tx_meta_desc *p)
{
}
static inline void set_ena_eth_io_tx_meta_desc_ext_valid(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT)
& ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;
}
}
static inline void set_ena_eth_io_tx_meta_desc_word3_valid(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT)
& ENA_ETH_IO_TX_META_DESC_WORD3_VALID_MASK;
}
}
static inline void set_ena_eth_io_tx_meta_desc_mss_hi_ptp(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT)
& ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_MASK;
}
}
static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT)
& ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;
}
}
static inline void set_ena_eth_io_tx_meta_desc_meta_store(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT)
& ENA_ETH_IO_TX_META_DESC_META_STORE_MASK;
}
}
static inline void set_ena_eth_io_tx_meta_desc_meta_desc(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT)
& ENA_ETH_IO_TX_META_DESC_META_DESC_MASK;
}
}
static inline void set_ena_eth_io_tx_meta_desc_phase(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT)
& ENA_ETH_IO_TX_META_DESC_PHASE_MASK;
}
}
static inline void set_ena_eth_io_tx_meta_desc_first(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT)
& ENA_ETH_IO_TX_META_DESC_FIRST_MASK;
}
}
static inline void set_ena_eth_io_tx_meta_desc_last(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT)
& ENA_ETH_IO_TX_META_DESC_LAST_MASK;
}
}
static inline void set_ena_eth_io_tx_meta_desc_comp_req(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT)
& ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK;
}
& ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;
}
-static inline uint32_t get_ena_eth_io_tx_meta_desc_crypto_info(
- const struct ena_eth_io_tx_meta_desc *p)
-{
- return p->word3 & ENA_ETH_IO_TX_META_DESC_CRYPTO_INFO_MASK;
-}
-
-static inline void set_ena_eth_io_tx_meta_desc_crypto_info(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
-{
- p->word3 |= val & ENA_ETH_IO_TX_META_DESC_CRYPTO_INFO_MASK;
-}
-
-static inline uint32_t get_ena_eth_io_tx_meta_desc_outr_l3_hdr_len_words(
- const struct ena_eth_io_tx_meta_desc *p)
-{
- return (p->word3 & ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_MASK)
- >> ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_SHIFT;
-}
-
-static inline void set_ena_eth_io_tx_meta_desc_outr_l3_hdr_len_words(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
-{
- p->word3 |=
- (val << ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_SHIFT)
- & ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_MASK;
-}
-
-static inline uint32_t get_ena_eth_io_tx_meta_desc_outr_l3_off_lo(
- const struct ena_eth_io_tx_meta_desc *p)
-{
- return (p->word3 & ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_MASK)
- >> ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_SHIFT;
-}
-
-static inline void set_ena_eth_io_tx_meta_desc_outr_l3_off_lo(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
-{
- p->word3 |=
- (val << ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_SHIFT)
- & ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_MASK;
-}
-
static inline uint8_t get_ena_eth_io_tx_cdesc_phase(
const struct ena_eth_io_tx_cdesc *p)
{
& ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK;
}
-static inline uint32_t get_ena_eth_io_rx_cdesc_base_tunnel(
- const struct ena_eth_io_rx_cdesc_base *p)
-{
- return (p->status & ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_MASK)
- >> ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_SHIFT;
-}
-
-static inline void set_ena_eth_io_rx_cdesc_base_tunnel(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
-{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_SHIFT)
- & ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_MASK;
-}
-
static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(
const struct ena_eth_io_rx_cdesc_base *p)
{
}
static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK;
}
}
static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK;
}
}
static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK;
}
}
static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK;
}
-static inline uint32_t get_ena_eth_io_rx_cdesc_base_secured_pkt(
- const struct ena_eth_io_rx_cdesc_base *p)
-{
- return (p->status & ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_MASK)
- >> ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_SHIFT;
-}
-
-static inline void set_ena_eth_io_rx_cdesc_base_secured_pkt(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
-{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_SHIFT)
- & ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_MASK;
-}
-
-static inline uint32_t get_ena_eth_io_rx_cdesc_base_crypto_status(
- const struct ena_eth_io_rx_cdesc_base *p)
-{
- return (p->status & ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_MASK)
- >> ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_SHIFT;
-}
-
-static inline void set_ena_eth_io_rx_cdesc_base_crypto_status(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
-{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_SHIFT)
- & ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_MASK;
-}
-
static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(
const struct ena_eth_io_rx_cdesc_base *p)
{
}
static inline void set_ena_eth_io_rx_cdesc_base_phase(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK;
}
}
static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK;
}
}
static inline void set_ena_eth_io_rx_cdesc_base_first(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK;
}
}
static inline void set_ena_eth_io_rx_cdesc_base_last(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK;
}
-static inline uint32_t get_ena_eth_io_rx_cdesc_base_inr_l4_csum(
- const struct ena_eth_io_rx_cdesc_base *p)
-{
- return (p->status & ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_MASK)
- >> ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_SHIFT;
-}
-
-static inline void set_ena_eth_io_rx_cdesc_base_inr_l4_csum(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
-{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_SHIFT)
- & ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_MASK;
-}
-
static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(
const struct ena_eth_io_rx_cdesc_base *p)
{
}
static inline void set_ena_eth_io_rx_cdesc_base_buffer(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK;
}
}
static inline void set_ena_eth_io_intr_reg_rx_intr_delay(
- struct ena_eth_io_intr_reg *p,
- uint32_t val)
+ struct ena_eth_io_intr_reg *p, uint32_t val)
{
p->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
}
}
static inline void set_ena_eth_io_intr_reg_tx_intr_delay(
- struct ena_eth_io_intr_reg *p,
- uint32_t val)
+ struct ena_eth_io_intr_reg *p, uint32_t val)
{
- p->intr_control |=
- (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
+ p->intr_control |= (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
& ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
}
}
static inline void set_ena_eth_io_intr_reg_intr_unmask(
- struct ena_eth_io_intr_reg *p,
- uint32_t val)
+ struct ena_eth_io_intr_reg *p, uint32_t val)
{
- p->intr_control |=
- (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT)
+ p->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT)
& ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
}
+static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(
+ const struct ena_eth_io_numa_node_cfg_reg *p)
+{
+ return p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;
+}
+
+static inline void set_ena_eth_io_numa_node_cfg_reg_numa(
+ struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)
+{
+ p->numa_cfg |= val & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;
+}
+
+static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_enabled(
+ const struct ena_eth_io_numa_node_cfg_reg *p)
+{
+ return (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK)
+ >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT;
+}
+
+static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(
+ struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)
+{
+ p->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT)
+ & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
+}
+
#endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */
#endif /*_ENA_ETH_IO_H_ */
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