New upstream version 18.08

[deb_dpdk.git] / drivers / net / ena / base / ena_defs / ena_regs_defs.h

diff --git a/drivers/net/ena/base/ena_defs/ena_regs_defs.h b/drivers/net/ena/base/ena_defs/ena_regs_defs.h
index d024127..b0870f2 100644 (file)
--- a/drivers/net/ena/base/ena_defs/ena_regs_defs.h
+++ b/drivers/net/ena/base/ena_defs/ena_regs_defs.h
@@ -34,6 +34,38 @@
 #ifndef _ENA_REGS_H_
 #define _ENA_REGS_H_
 
+enum ena_regs_reset_reason_types {
+       ENA_REGS_RESET_NORMAL                   = 0,
+
+       ENA_REGS_RESET_KEEP_ALIVE_TO            = 1,
+
+       ENA_REGS_RESET_ADMIN_TO                 = 2,
+
+       ENA_REGS_RESET_MISS_TX_CMPL             = 3,
+
+       ENA_REGS_RESET_INV_RX_REQ_ID            = 4,
+
+       ENA_REGS_RESET_INV_TX_REQ_ID            = 5,
+
+       ENA_REGS_RESET_TOO_MANY_RX_DESCS        = 6,
+
+       ENA_REGS_RESET_INIT_ERR                 = 7,
+
+       ENA_REGS_RESET_DRIVER_INVALID_STATE     = 8,
+
+       ENA_REGS_RESET_OS_TRIGGER               = 9,
+
+       ENA_REGS_RESET_OS_NETDEV_WD             = 10,
+
+       ENA_REGS_RESET_SHUTDOWN                 = 11,
+
+       ENA_REGS_RESET_USER_TRIGGER             = 12,
+
+       ENA_REGS_RESET_GENERIC                  = 13,
+
+       ENA_REGS_RESET_MISS_INTERRUPT           = 14,
+};
+
 /* ena_registers offsets */
 #define ENA_REGS_VERSION_OFF           0x0
 #define ENA_REGS_CONTROLLER_VERSION_OFF                0x4
@@ -80,6 +112,8 @@
 #define ENA_REGS_CAPS_RESET_TIMEOUT_MASK               0x3e
 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT             8
 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK              0xff00
+#define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT               16
+#define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK                0xf0000
 
 /* aq_caps register */
 #define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK         0xffff
@@ -104,6 +138,8 @@
 #define ENA_REGS_DEV_CTL_QUIESCENT_MASK                0x4
 #define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT               3
 #define ENA_REGS_DEV_CTL_IO_RESUME_MASK                0x8
+#define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT            28
+#define ENA_REGS_DEV_CTL_RESET_REASON_MASK             0xf0000000
 
 /* dev_sts register */
 #define ENA_REGS_DEV_STS_READY_MASK            0x1