Imported Upstream version 16.07-rc1

[deb_dpdk.git] / drivers / net / i40e / base / i40e_adminq_cmd.h

diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h
index fe9d5b5..2b7a760 100644 (file)
--- a/drivers/net/i40e/base/i40e_adminq_cmd.h
+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h
@@ -224,10 +224,6 @@ enum i40e_admin_queue_opc {
        i40e_aqc_opc_resume_port_tx                             = 0x041C,
        i40e_aqc_opc_configure_partition_bw                     = 0x041D,
 
-       /* hmc */
-       i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
-       i40e_aqc_opc_set_hmc_resource_profile   = 0x0501,
-
        /* phy commands*/
        i40e_aqc_opc_get_phy_abilities          = 0x0600,
        i40e_aqc_opc_set_phy_config             = 0x0601,
@@ -450,6 +446,7 @@ struct i40e_aqc_list_capabilities_element_resp {
 #define I40E_AQ_CAP_ID_SDP             0x0062
 #define I40E_AQ_CAP_ID_MDIO            0x0063
 #define I40E_AQ_CAP_ID_WSR_PROT                0x0064
+#define I40E_AQ_CAP_ID_NVM_MGMT                0x0080
 #define I40E_AQ_CAP_ID_FLEX10          0x00F1
 #define I40E_AQ_CAP_ID_CEM             0x00F2
 
@@ -931,7 +928,7 @@ struct i40e_aqc_vsi_properties_data {
        u8      up_enable_bits;
        u8      sched_reserved;
        /* outer up section */
-       __le32  outer_up_table; /* same structure and defines as ingress table */
+       __le32  outer_up_table; /* same structure and defines as ingress tbl */
        u8      cmd_reserved[8];
        /* last 32 bytes are written by FW */
        __le16  qs_handle[8];
@@ -1571,7 +1568,8 @@ struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
        u8      reserved1[28];
 };
 
-I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data);
+I40E_CHECK_STRUCT_LEN(0x40,
+                     i40e_aqc_configure_switching_comp_ets_bw_limit_data);
 
 /* Configure Switching Component Bandwidth Allocation per Tc
  * (indirect 0x0417)
@@ -1646,27 +1644,6 @@ struct i40e_aqc_configure_partition_bw_data {
 
 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
 
-/* Get and set the active HMC resource profile and status.
- * (direct 0x0500) and (direct 0x0501)
- */
-struct i40e_aq_get_set_hmc_resource_profile {
-       u8      pm_profile;
-       u8      pe_vf_enabled;
-       u8      reserved[14];
-};
-
-I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
-
-enum i40e_aq_hmc_profile {
-       /* I40E_HMC_PROFILE_NO_CHANGE    = 0, reserved */
-       I40E_HMC_PROFILE_DEFAULT        = 1,
-       I40E_HMC_PROFILE_FAVOR_VF       = 2,
-       I40E_HMC_PROFILE_EQUAL          = 3,
-};
-
-#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK       0xF
-#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK    0x3F
-
 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
 
 /* set in param0 for get phy abilities to report qualified modules */
@@ -1702,6 +1679,10 @@ enum i40e_aq_phy_type {
        I40E_PHY_TYPE_1000BASE_LX               = 0x1C,
        I40E_PHY_TYPE_1000BASE_T_OPTICAL        = 0x1D,
        I40E_PHY_TYPE_20GBASE_KR2               = 0x1E,
+       I40E_PHY_TYPE_25GBASE_KR                = 0x1F,
+       I40E_PHY_TYPE_25GBASE_CR                = 0x20,
+       I40E_PHY_TYPE_25GBASE_SR                = 0x21,
+       I40E_PHY_TYPE_25GBASE_LR                = 0x22,
        I40E_PHY_TYPE_MAX
 };
 
@@ -1918,7 +1899,10 @@ struct i40e_aqc_set_phy_debug {
 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE  0x00
 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD  0x01
 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT  0x02
+/* Disable link manageability on a single port */
 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW      0x10
+/* Disable link manageability on all ports needs both bits 4 and 5 */
+#define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW  0x20
        u8      reserved[15];
 };
 
@@ -1966,7 +1950,7 @@ struct i40e_aqc_nvm_config_read {
 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE               0
 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES            1
        __le16  element_count;
-       __le16  element_id;     /* Feature/field ID */
+       __le16  element_id;     /* Feature/field ID */
        __le16  element_id_msw; /* MSWord of field ID */
        __le32  address_high;
        __le32  address_low;
@@ -1987,9 +1971,10 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
 
 /* Used for 0x0704 as well as for 0x0705 commands */
 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT                1
-#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK         (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
-#define I40E_AQ_ANVM_FEATURE                           0
-#define I40E_AQ_ANVM_IMMEDIATE_FIELD                   (1 << FEATURE_OR_IMMEDIATE_SHIFT)
+#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
+                               (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
+#define I40E_AQ_ANVM_FEATURE           0
+#define I40E_AQ_ANVM_IMMEDIATE_FIELD   (1 << FEATURE_OR_IMMEDIATE_SHIFT)
 struct i40e_aqc_nvm_config_data_feature {
        __le16 feature_id;
 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY           0x01
@@ -2013,7 +1998,7 @@ I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
 /* OEM Post Update (indirect 0x0720)
  * no command data struct used
  */
- struct i40e_aqc_nvm_oem_post_update {
+struct i40e_aqc_nvm_oem_post_update {
 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA      0x01
        u8 sel_data;
        u8 reserved[7];
@@ -2303,7 +2288,8 @@ I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
  */
 struct i40e_aqc_lldp_stop_start_specific_agent {
 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT    0
-#define I40E_AQC_START_SPECIFIC_AGENT_MASK     (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
+#define I40E_AQC_START_SPECIFIC_AGENT_MASK \
+                               (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
        u8      command;
        u8      reserved[15];
 };
@@ -2325,7 +2311,7 @@ struct i40e_aqc_add_udp_tunnel {
 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
 
 struct i40e_aqc_add_udp_tunnel_completion {
-       __le16 udp_port;
+       __le16  udp_port;
        u8      filter_entry_index;
        u8      multiple_pfs;
 #define I40E_AQC_SINGLE_PF             0x0