New upstream version 16.11.9

[deb_dpdk.git] / drivers / net / i40e / i40e_ethdev.c

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 3061296..62b36c9 100644 (file)
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -1081,9 +1081,6 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
        /* Make sure all is clean before doing PF reset */
        i40e_clear_hw(hw);
 
-       /* Initialize the hardware */
-       i40e_hw_init(dev);
-
        /* Reset here to make sure all is clean for each PF */
        ret = i40e_pf_reset(hw);
        if (ret) {
@@ -1098,20 +1095,6 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
                return ret;
        }
 
-       i40e_config_automask(pf);
-
-       /*
-        * To work around the NVM issue, initialize registers
-        * for flexible payload and packet type of QinQ by
-        * software. It should be removed once issues are fixed
-        * in NVM.
-        */
-       if (!pf->support_multi_driver)
-               i40e_GLQF_reg_init(hw);
-
-       /* Initialize the input set for filters (hash and fd) to default value */
-       i40e_filter_input_set_init(pf);
-
        /* Initialize the parameters for adminq */
        i40e_init_adminq_parameter(hw);
        ret = i40e_init_adminq(hw);
@@ -1126,6 +1109,23 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
                     ((hw->nvm.version >> 4) & 0xff),
                     (hw->nvm.version & 0xf), hw->nvm.eetrack);
 
+       /* Initialize the hardware */
+       i40e_hw_init(dev);
+
+       i40e_config_automask(pf);
+
+       /*
+        * To work around the NVM issue, initialize registers
+        * for flexible payload and packet type of QinQ by
+        * software. It should be removed once issues are fixed
+        * in NVM.
+        */
+       if (!pf->support_multi_driver)
+               i40e_GLQF_reg_init(hw);
+
+       /* Initialize the input set for filters (hash and fd) to default value */
+       i40e_filter_input_set_init(pf);
+
        /* Need the special FW version to support floating VEB */
        config_floating_veb(dev);
        /* Clear PXE mode */
@@ -2085,6 +2085,10 @@ i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
        if (status != I40E_SUCCESS)
                PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
 
+       /* must remain in all_multicast mode */
+       if (dev->data->all_multicast == 1)
+               return;
+
        status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
                                                        false, NULL);
        if (status != I40E_SUCCESS)
@@ -4589,7 +4593,7 @@ i40e_enable_pf_lb(struct i40e_pf *pf)
        int ret;
 
        /* Use the FW API if FW >= v5.0 */
-       if (hw->aq.fw_maj_ver < 5) {
+       if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
                PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
                return;
        }
@@ -4858,7 +4862,7 @@ i40e_vsi_setup(struct i40e_pf *pf,
                ctxt.flags = I40E_AQ_VSI_TYPE_VF;
 
                /* Use the VEB configuration if FW >= v5.0 */
-               if (hw->aq.fw_maj_ver >= 5) {
+               if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
                        /* Configure switch ID */
                        ctxt.info.valid_sections |=
                        rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
@@ -10080,6 +10084,32 @@ i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
        return 0;
 }
 
+/**
+ * This function is used to check if the register is valid.
+ * Below is the valid registers list for X722 only:
+ * 0x2b800--0x2bb00
+ * 0x38700--0x38a00
+ * 0x3d800--0x3db00
+ * 0x208e00--0x209000
+ * 0x20be00--0x20c000
+ * 0x263c00--0x264000
+ * 0x265c00--0x266000
+ */
+static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
+{
+       if ((type != I40E_MAC_X722) &&
+           ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
+            (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
+            (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
+            (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
+            (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
+            (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
+            (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
+               return 0;
+       else
+               return 1;
+}
+
 static int i40e_get_regs(struct rte_eth_dev *dev,
                         struct rte_dev_reg_info *regs)
 {
@@ -10121,8 +10151,11 @@ static int i40e_get_regs(struct rte_eth_dev *dev,
                                reg_offset = arr_idx * reg_info->stride1 +
                                        arr_idx2 * reg_info->stride2;
                                reg_offset += reg_info->base_addr;
-                               ptr_data[reg_offset >> 2] =
-                                       I40E_READ_REG(hw, reg_offset);
+                               if (!i40e_valid_regs(hw->mac.type, reg_offset))
+                                       ptr_data[reg_offset >> 2] = 0;
+                               else
+                                       ptr_data[reg_offset >> 2] =
+                                               I40E_READ_REG(hw, reg_offset);
                        }
        }