New upstream version 17.11.1

[deb_dpdk.git] / drivers / net / i40e / i40e_ethdev.h

diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index cd67453..229c974 100644 (file)
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -106,6 +106,15 @@
        (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
        ((vf)->version_minor == 1))
 
+#define I40E_WRITE_GLB_REG(hw, reg, value)                             \
+       do {                                                            \
+               I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw),              \
+                                                    (reg)), (value));  \
+               PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified " \
+                           "with value 0x%08x",                        \
+                           (reg), (value));                            \
+       } while (0)
+
 /* index flex payload per layer */
 enum i40e_flxpld_layer_idx {
        I40E_FLXPLD_L2_IDX    = 0,
@@ -957,6 +966,7 @@ struct i40e_pf {
        bool gtp_replace_flag;   /* 1 - GTP-C/U filter replace is done */
        bool qinq_replace_flag;  /* QINQ filter replace is done */
        struct i40e_tm_conf tm_conf;
+       bool support_multi_driver; /* 1 - support multiple driver */
 
        /* Dynamic Device Personalization */
        bool gtp_support; /* 1 - support GTP-C and GTP-U */
@@ -1084,6 +1094,22 @@ struct i40e_valid_pattern {
        parse_filter_t parse_filter;
 };
 
+enum I40E_WARNING_IDX {
+       I40E_WARNING_DIS_FLX_PLD,
+       I40E_WARNING_ENA_FLX_PLD,
+       I40E_WARNING_QINQ_PARSER,
+       I40E_WARNING_QINQ_CLOUD_FILTER,
+       I40E_WARNING_TPID,
+       I40E_WARNING_FLOW_CTL,
+       I40E_WARNING_GRE_KEY_LEN,
+       I40E_WARNING_QF_CTL,
+       I40E_WARNING_HASH_INSET,
+       I40E_WARNING_HSYM,
+       I40E_WARNING_HASH_MSK,
+       I40E_WARNING_FD_MSK,
+       I40E_WARNING_RPL_CLD_FILTER,
+};
+
 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
 int i40e_vsi_release(struct i40e_vsi *vsi);
 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
@@ -1186,6 +1212,8 @@ int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
                                 uint8_t nb_elem);
 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
+void i40e_check_write_global_reg(struct i40e_hw *hw,
+                                uint32_t addr, uint32_t val);
 
 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
 void i40e_tm_conf_init(struct rte_eth_dev *dev);
@@ -1274,15 +1302,44 @@ i40e_align_floor(int n)
 }
 
 static inline uint16_t
-i40e_calc_itr_interval(int16_t interval)
+i40e_calc_itr_interval(int16_t interval, bool is_multi_drv)
 {
-       if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
+       if (is_multi_drv)
+               interval = I40E_QUEUE_ITR_INTERVAL_MAX;
+       else if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
                interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 
        /* Convert to hardware count, as writing each 1 represents 2 us */
        return interval / 2;
 }
 
+static inline void
+i40e_global_cfg_warning(enum I40E_WARNING_IDX idx)
+{
+       const char *warning;
+       static const char *const warning_list[] = {
+               [I40E_WARNING_DIS_FLX_PLD] = "disable FDIR flexible payload",
+               [I40E_WARNING_ENA_FLX_PLD] = "enable FDIR flexible payload",
+               [I40E_WARNING_QINQ_PARSER] = "support QinQ parser",
+               [I40E_WARNING_QINQ_CLOUD_FILTER] = "support QinQ cloud filter",
+               [I40E_WARNING_TPID] = "support TPID configuration",
+               [I40E_WARNING_FLOW_CTL] = "configure water marker",
+               [I40E_WARNING_GRE_KEY_LEN] = "support GRE key length setting",
+               [I40E_WARNING_QF_CTL] = "support hash function setting",
+               [I40E_WARNING_HASH_INSET] = "configure hash input set",
+               [I40E_WARNING_HSYM] = "set symmetric hash",
+               [I40E_WARNING_HASH_MSK] = "configure hash mask",
+               [I40E_WARNING_FD_MSK] = "configure fdir mask",
+               [I40E_WARNING_RPL_CLD_FILTER] = "replace cloud filter",
+       };
+
+       warning = warning_list[idx];
+
+       RTE_LOG(WARNING, PMD,
+               "Global register is changed during %s\n",
+               warning);
+}
+
 #define I40E_VALID_FLOW(flow_type) \
        ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
        (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \