Imported Upstream version 16.11

[deb_dpdk.git] / drivers / net / ixgbe / base / ixgbe_type.h

diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h
index 83818a9..4982e03 100644 (file)
--- a/drivers/net/ixgbe/base/ixgbe_type.h
+++ b/drivers/net/ixgbe/base/ixgbe_type.h
@@ -105,11 +105,11 @@ POSSIBILITY OF SUCH DAMAGE.
 #define IXGBE_SUBDEV_ID_82599_560FLR           0x17D0
 #define IXGBE_SUBDEV_ID_82599_ECNA_DP          0x0470
 #define IXGBE_SUBDEV_ID_82599_SP_560FLR                0x211B
-#define IXGBE_SUBDEV_ID_82599_LOM_SFP          0x8976
 #define IXGBE_SUBDEV_ID_82599_LOM_SNAP6                0x2159
 #define IXGBE_SUBDEV_ID_82599_SFP_1OCP         0x000D
 #define IXGBE_SUBDEV_ID_82599_SFP_2OCP         0x0008
-#define IXGBE_SUBDEV_ID_82599_SFP_LOM          0x06EE
+#define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1     0x8976
+#define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2     0x06EE
 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE      0x152A
 #define IXGBE_DEV_ID_82599_SFP_FCOE            0x1529
 #define IXGBE_DEV_ID_82599_SFP_EM              0x1507
@@ -565,6 +565,13 @@ struct ixgbe_thermal_sensor_data {
 #define IXGBE_PROXYFC  0x05F64 /* Proxying Filter Control Register */
 #define IXGBE_VXLANCTRL        0x0000507C /* Rx filter VXLAN UDPPORT Register */
 
+/* masks for accessing VXLAN and GENEVE UDP ports */
+#define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK     0x0000ffff /* VXLAN port */
+#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK    0xffff0000 /* GENEVE port */
+#define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK       0xffffffff /* GENEVE/VXLAN */
+
+#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT   16
+
 #define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
 /* Ext Flexible Host Filter Table */
 #define IXGBE_FHFT_EXT(_n)     (0x09800 + ((_n) * 0x100))
@@ -1644,13 +1651,14 @@ struct ixgbe_dmac_config {
 #define X550_PHY_ID2   0x01540223
 #define X550_PHY_ID3   0x01540221
 #define X557_PHY_ID    0x01540240
+#define X557_PHY_ID2   0x01540250
 #define AQ_FW_REV      0x20
 #define QT2022_PHY_ID  0x0043A400
 #define ATH_PHY_ID     0x03429050
 
 /* PHY Types */
-#define IXGBE_M88E1500_E_PHY_ID                0x01410DD0
-#define IXGBE_M88E1543_E_PHY_ID                0x01410EA0
+#define IXGBE_M88E1500_E_PHY_ID        0x01410DD0
+#define IXGBE_M88E1543_E_PHY_ID        0x01410EA0
 
 /* Special PHY Init Routine */
 #define IXGBE_PHY_INIT_OFFSET_NL       0x002B
@@ -1765,6 +1773,8 @@ enum {
 #define IXGBE_VT_CTL_POOL_MASK         (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
 
 /* VMOLR bitmasks */
+#define IXGBE_VMOLR_UPE                0x00400000 /* unicast promiscuous */
+#define IXGBE_VMOLR_VPE                0x00800000 /* VLAN promiscuous */
 #define IXGBE_VMOLR_AUPE       0x01000000 /* accept untagged packets */
 #define IXGBE_VMOLR_ROMPE      0x02000000 /* accept packets in MTA tbl */
 #define IXGBE_VMOLR_ROPE       0x04000000 /* accept packets in UC tbl */
@@ -2203,6 +2213,7 @@ enum {
 #define IXGBE_LINKS_SPEED_10G_82599    0x30000000
 #define IXGBE_LINKS_SPEED_1G_82599     0x20000000
 #define IXGBE_LINKS_SPEED_100_82599    0x10000000
+#define IXGBE_LINKS_SPEED_10_X550EM_A  0x00000000
 #define IXGBE_LINK_UP_TIME             90 /* 9.0 Seconds */
 #define IXGBE_AUTO_NEG_TIME            45 /* 4.5 Seconds */
 
@@ -2335,7 +2346,9 @@ enum {
 
 #define IXGBE_SAN_MAC_ADDR_PTR         0x28
 #define IXGBE_DEVICE_CAPS              0x2C
-#define IXGBE_SERIAL_NUMBER_MAC_ADDR   0x11
+#define IXGBE_82599_SERIAL_NUMBER_MAC_ADDR     0x11
+#define IXGBE_X550_SERIAL_NUMBER_MAC_ADDR      0x04
+
 #define IXGBE_PCIE_MSIX_82599_CAPS     0x72
 #define IXGBE_MAX_MSIX_VECTORS_82599   0x40
 #define IXGBE_PCIE_MSIX_82598_CAPS     0x62
@@ -2780,6 +2793,7 @@ enum {
 #define IXGBE_RXDADV_PKTTYPE_UDP       0x00000200 /* UDP hdr present */
 #define IXGBE_RXDADV_PKTTYPE_SCTP      0x00000400 /* SCTP hdr present */
 #define IXGBE_RXDADV_PKTTYPE_NFS       0x00000800 /* NFS hdr present */
+#define IXGBE_RXDADV_PKTTYPE_GENEVE    0x00000800 /* GENEVE hdr present */
 #define IXGBE_RXDADV_PKTTYPE_VXLAN     0x00000800 /* VXLAN hdr present */
 #define IXGBE_RXDADV_PKTTYPE_TUNNEL    0x00010000 /* Tunnel type */
 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
@@ -3054,7 +3068,7 @@ enum ixgbe_fdir_pballoc_type {
 #ifdef C99
 #pragma pack(push, 1)
 #else
-#pragma pack(1)
+#pragma pack (1)
 #endif /* C99 */
 
 struct ixgbe_hic_hdr {
@@ -3136,13 +3150,13 @@ struct ixgbe_hic_internal_phy_req {
        u8 command_type;
        __be16 address;
        u16 rsv1;
-       __le32 write_data;
+       __be32 write_data;
        u16 pad;
 };
 
 struct ixgbe_hic_internal_phy_resp {
        struct ixgbe_hic_hdr hdr;
-       __le32 read_data;
+       __be32 read_data;
 };
 
 #ifdef C99
@@ -3305,7 +3319,7 @@ typedef u32 ixgbe_autoneg_advertised;
 /* Link speed */
 typedef u32 ixgbe_link_speed;
 #define IXGBE_LINK_SPEED_UNKNOWN       0
-#define IXGBE_LINK_SPEED_10_FULL       0x0004
+#define IXGBE_LINK_SPEED_10_FULL       0x0002
 #define IXGBE_LINK_SPEED_100_FULL      0x0008
 #define IXGBE_LINK_SPEED_1GB_FULL      0x0020
 #define IXGBE_LINK_SPEED_2_5GB_FULL    0x0400
@@ -3840,6 +3854,7 @@ struct ixgbe_mac_operations {
        void (*init_swfw_sync)(struct ixgbe_hw *);
        s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
        s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
+       s32 (*negotiate_api_version)(struct ixgbe_hw *hw, int api);
 
        /* Link */
        void (*disable_tx_laser)(struct ixgbe_hw *);
@@ -3883,6 +3898,8 @@ struct ixgbe_mac_operations {
        s32 (*init_uta_tables)(struct ixgbe_hw *);
        void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
        void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
+       s32 (*update_xcast_mode)(struct ixgbe_hw *, int);
+       s32 (*set_rlpml)(struct ixgbe_hw *, u16);
 
        /* Flow Control */
        s32 (*fc_enable)(struct ixgbe_hw *);
@@ -4078,6 +4095,7 @@ struct ixgbe_hw {
        bool force_full_reset;
        bool allow_unsupported_sfp;
        bool wol_enabled;
+       bool need_crosstalk_fix;
 };
 
 #define ixgbe_call_func(hw, func, params, error) \
@@ -4136,16 +4154,35 @@ struct ixgbe_hw {
 #define IXGBE_KRM_LINK_S1(P)           ((P) ? 0x8200 : 0x4200)
 #define IXGBE_KRM_LINK_CTRL_1(P)       ((P) ? 0x820C : 0x420C)
 #define IXGBE_KRM_AN_CNTL_1(P)         ((P) ? 0x822C : 0x422C)
+#define IXGBE_KRM_AN_CNTL_4(P)         ((P) ? 0x8238 : 0x4238)
 #define IXGBE_KRM_AN_CNTL_8(P)         ((P) ? 0x8248 : 0x4248)
+#define IXGBE_KRM_PCS_KX_AN(P)         ((P) ? 0x9918 : 0x5918)
+#define IXGBE_KRM_PCS_KX_AN_LP(P)      ((P) ? 0x991C : 0x591C)
 #define IXGBE_KRM_SGMII_CTRL(P)                ((P) ? 0x82A0 : 0x42A0)
 #define IXGBE_KRM_LP_BASE_PAGE_HIGH(P) ((P) ? 0x836C : 0x436C)
 #define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)
 #define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)
 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P)        ((P) ? 0x8B00 : 0x4B00)
 #define IXGBE_KRM_PMD_DFX_BURNIN(P)    ((P) ? 0x8E00 : 0x4E00)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20(P) ((P) ? 0x9054 : 0x5054)
 #define IXGBE_KRM_TX_COEFF_CTRL_1(P)   ((P) ? 0x9520 : 0x5520)
 #define IXGBE_KRM_RX_ANA_CTL(P)                ((P) ? 0x9A00 : 0x5A00)
 
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA         ~(0x3 << 20)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR         (1u << 20)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR         (0x2 << 20)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN           (1u << 25)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN            (1u << 26)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN              (1u << 27)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M          ~(0x7 << 28)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M         (1u << 28)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G           (0x2 << 28)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G          (0x3 << 28)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN           (0x4 << 28)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G         (0x7 << 28)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK         (0x7 << 28)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART      (1u << 31)
+
 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B           (1 << 9)
 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS         (1 << 11)
 
@@ -4166,9 +4203,14 @@ struct ixgbe_hw {
 
 #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE                  (1 << 28)
 #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE                  (1 << 29)
-
+#define IXGBE_KRM_PCS_KX_AN_SYM_PAUSE                  (1 << 1)
+#define IXGBE_KRM_PCS_KX_AN_ASM_PAUSE                  (1 << 2)
+#define IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE               (1 << 2)
+#define IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE               (1 << 3)
+#define IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73          (1 << 29)
 #define IXGBE_KRM_AN_CNTL_8_LINEAR                     (1 << 0)
 #define IXGBE_KRM_AN_CNTL_8_LIMITING                   (1 << 1)
+
 #define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE          (1 << 10)
 #define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE          (1 << 11)
 
@@ -4207,11 +4249,18 @@ struct ixgbe_hw {
 #define IXGBE_SB_IOSF_TARGET_KR_PHY    0
 
 #define IXGBE_NW_MNG_IF_SEL            0x00011178
-#define IXGBE_NW_MNG_IF_SEL_MDIO_ACT   (1 << 1)
+#define IXGBE_NW_MNG_IF_SEL_MDIO_ACT   (1u << 1)
+#define IXGBE_NW_MNG_IF_SEL_MDIO_IF_MODE       (1u << 2)
+#define IXGBE_NW_MNG_IF_SEL_EN_SHARED_MDIO     (1u << 13)
+#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M      (1u << 17)
+#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M     (1u << 18)
+#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G       (1u << 19)
+#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G     (1u << 20)
+#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G      (1u << 21)
 #define IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M (1 << 23)
 #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24)
 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3
 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD       \
-               (0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
+                               (0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
 
 #endif /* _IXGBE_TYPE_H_ */