New upstream version 17.11.3

[deb_dpdk.git] / drivers / net / mlx4 / mlx4_rxtx.c

diff --git a/drivers/net/mlx4/mlx4_rxtx.c b/drivers/net/mlx4/mlx4_rxtx.c
index 3985e06..05c4892 100644 (file)
--- a/drivers/net/mlx4/mlx4_rxtx.c
+++ b/drivers/net/mlx4/mlx4_rxtx.c
@@ -88,7 +88,8 @@ uint32_t mlx4_ptype_table[0x100] __rte_cache_aligned = {
         * giving a total of up to 256 entries.
         */
        [0x00] = RTE_PTYPE_L2_ETHER,
-       [0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
+       [0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
+                    RTE_PTYPE_L4_NONFRAG,
        [0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                     RTE_PTYPE_L4_FRAG,
        [0x03] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
@@ -336,6 +337,7 @@ mlx4_txq_complete(struct txq *txq, const unsigned int elts_n,
 {
        unsigned int elts_comp = txq->elts_comp;
        unsigned int elts_tail = txq->elts_tail;
+       unsigned int sq_tail = sq->tail;
        struct mlx4_cq *cq = &txq->mcq;
        volatile struct mlx4_cqe *cqe;
        uint32_t cons_index = cq->cons_index;
@@ -372,13 +374,13 @@ mlx4_txq_complete(struct txq *txq, const unsigned int elts_n,
                        rte_be_to_cpu_16(cqe->wqe_index) & sq->txbb_cnt_mask;
                do {
                        /* Free next descriptor. */
-                       nr_txbbs +=
+                       sq_tail += nr_txbbs;
+                       nr_txbbs =
                                mlx4_txq_stamp_freed_wqe(sq,
-                                    (sq->tail + nr_txbbs) & sq->txbb_cnt_mask,
-                                    !!((sq->tail + nr_txbbs) & sq->txbb_cnt));
+                                    sq_tail & sq->txbb_cnt_mask,
+                                    !!(sq_tail & sq->txbb_cnt));
                        pkts++;
-               } while (((sq->tail + nr_txbbs) & sq->txbb_cnt_mask) !=
-                        new_index);
+               } while ((sq_tail & sq->txbb_cnt_mask) != new_index);
                cons_index++;
        } while (1);
        if (unlikely(pkts == 0))
@@ -386,7 +388,7 @@ mlx4_txq_complete(struct txq *txq, const unsigned int elts_n,
        /* Update CQ. */
        cq->cons_index = cons_index;
        *cq->set_ci_db = rte_cpu_to_be_32(cq->cons_index & MLX4_CQ_DB_CI_MASK);
-       sq->tail = sq->tail + nr_txbbs;
+       sq->tail = sq_tail + nr_txbbs;
        /* Update the list of packets posted for transmission. */
        elts_comp -= pkts;
        assert(elts_comp <= txq->elts_comp);
@@ -467,7 +469,6 @@ mlx4_tx_burst_segs(struct rte_mbuf *buf, struct txq *txq,
                /* Memory region key (big endian) for this memory pool. */
                lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
                dseg->lkey = rte_cpu_to_be_32(lkey);
-#ifndef NDEBUG
                /* Calculate the needed work queue entry size for this packet */
                if (unlikely(dseg->lkey == rte_cpu_to_be_32((uint32_t)-1))) {
                        /* MR does not exist. */
@@ -485,7 +486,6 @@ mlx4_tx_burst_segs(struct rte_mbuf *buf, struct txq *txq,
                                        (sq->head & sq->txbb_cnt) ? 0 : 1);
                        return -1;
                }
-#endif /* NDEBUG */
                if (likely(sbuf->data_len)) {
                        byte_count = rte_cpu_to_be_32(sbuf->data_len);
                } else {
@@ -635,7 +635,6 @@ mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
                        /* Memory region key (big endian). */
                        lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(buf));
                        dseg->lkey = rte_cpu_to_be_32(lkey);
-#ifndef NDEBUG
                        if (unlikely(dseg->lkey ==
                                rte_cpu_to_be_32((uint32_t)-1))) {
                                /* MR does not exist. */
@@ -654,7 +653,6 @@ mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
                                elt->buf = NULL;
                                break;
                        }
-#endif /* NDEBUG */
                        /* Never be TXBB aligned, no need compiler barrier. */
                        dseg->byte_count = rte_cpu_to_be_32(buf->data_len);
                        /* Fill the control parameters for this packet. */
@@ -751,7 +749,8 @@ mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
  *   Packet type for struct rte_mbuf.
  */
 static inline uint32_t
-rxq_cq_to_pkt_type(volatile struct mlx4_cqe *cqe)
+rxq_cq_to_pkt_type(volatile struct mlx4_cqe *cqe,
+                  uint32_t l2tun_offload)
 {
        uint8_t idx = 0;
        uint32_t pinfo = rte_be_to_cpu_32(cqe->vlan_my_qpn);
@@ -762,7 +761,7 @@ rxq_cq_to_pkt_type(volatile struct mlx4_cqe *cqe)
         *  bit[7] - MLX4_CQE_L2_TUNNEL
         *  bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
         */
-       if (!(pinfo & MLX4_CQE_L2_VLAN_MASK) && (pinfo & MLX4_CQE_L2_TUNNEL))
+       if (l2tun_offload && (pinfo & MLX4_CQE_L2_TUNNEL))
                idx |= ((pinfo & MLX4_CQE_L2_TUNNEL) >> 20) |
                       ((pinfo & MLX4_CQE_L2_TUNNEL_IPV4) >> 19);
        /*
@@ -960,8 +959,10 @@ mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
                        }
                        pkt = seg;
                        /* Update packet information. */
-                       pkt->packet_type = rxq_cq_to_pkt_type(cqe);
-                       pkt->ol_flags = 0;
+                       pkt->packet_type =
+                               rxq_cq_to_pkt_type(cqe, rxq->l2tun_offload);
+                       pkt->ol_flags = PKT_RX_RSS_HASH;
+                       pkt->hash.rss = cqe->immed_rss_invalid;
                        pkt->pkt_len = len;
                        if (rxq->csum | rxq->csum_l2tun) {
                                uint32_t flags =