Imported Upstream version 17.05

[deb_dpdk.git] / drivers / net / mlx5 / mlx5_prm.h

diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index ed088ee..608072f 100644 (file)
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -34,6 +34,8 @@
 #ifndef RTE_PMD_MLX5_PRM_H_
 #define RTE_PMD_MLX5_PRM_H_
 
+#include <assert.h>
+
 /* Verbs header. */
 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
 #ifdef PEDANTIC
@@ -44,6 +46,7 @@
 #pragma GCC diagnostic error "-Wpedantic"
 #endif
 
+#include <rte_vect.h>
 #include "mlx5_autoconf.h"
 
 /* Get CQE owner bit. */
@@ -70,6 +73,9 @@
 /* WQE size */
 #define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)
 
+/* Max size of a WQE session. */
+#define MLX5_WQE_SIZE_MAX 960U
+
 /* Compute the number of DS. */
 #define MLX5_WQE_DS(n) \
        (((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)
@@ -77,10 +83,19 @@
 /* Room for inline data in multi-packet WQE. */
 #define MLX5_MWQE64_INL_DATA 28
 
+/* Default minimum number of Tx queues for inlining packets. */
+#define MLX5_EMPW_MIN_TXQS 8
+
+/* Default max packet length to be inlined. */
+#define MLX5_EMPW_MAX_INLINE_LEN (4U * MLX5_WQE_SIZE)
+
 #ifndef HAVE_VERBS_MLX5_OPCODE_TSO
 #define MLX5_OPCODE_TSO MLX5_OPCODE_LSO_MPW /* Compat with OFED 3.3. */
 #endif
 
+#define MLX5_OPC_MOD_ENHANCED_MPSW 0
+#define MLX5_OPCODE_ENHANCED_MPSW 0x29
+
 /* CQE value to inform that VLAN is stripped. */
 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
 
@@ -117,6 +132,28 @@
 /* Tunnel packet bit in the CQE. */
 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
 
+/* Inner L3 checksum offload (Tunneled packets only). */
+#define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
+
+/* Inner L4 checksum offload (Tunneled packets only). */
+#define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
+
+/* Is flow mark valid. */
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+#define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
+#else
+#define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
+#endif
+
+/* INVALID is used by packets matching no flow rules. */
+#define MLX5_FLOW_MARK_INVALID 0
+
+/* Maximum allowed value to mark a packet. */
+#define MLX5_FLOW_MARK_MAX 0xfffff0
+
+/* Default mark value used when none is provided. */
+#define MLX5_FLOW_MARK_DEFAULT 0xffffff
+
 /* Subset of struct mlx5_wqe_eth_seg. */
 struct mlx5_wqe_eth_seg_small {
        uint32_t rsvd0;
@@ -126,12 +163,19 @@ struct mlx5_wqe_eth_seg_small {
        uint32_t rsvd2;
        uint16_t inline_hdr_sz;
        uint8_t inline_hdr[2];
-};
+} __rte_aligned(MLX5_WQE_DWORD_SIZE);
 
 struct mlx5_wqe_inl_small {
        uint32_t byte_cnt;
        uint8_t raw;
-};
+} __rte_aligned(MLX5_WQE_DWORD_SIZE);
+
+struct mlx5_wqe_ctrl {
+       uint32_t ctrl0;
+       uint32_t ctrl1;
+       uint32_t ctrl2;
+       uint32_t ctrl3;
+} __rte_aligned(MLX5_WQE_DWORD_SIZE);
 
 /* Small common part of the WQE. */
 struct mlx5_wqe {
@@ -139,16 +183,30 @@ struct mlx5_wqe {
        struct mlx5_wqe_eth_seg_small eseg;
 };
 
+/* Vectorize WQE header. */
+struct mlx5_wqe_v {
+       rte_v128u32_t ctrl;
+       rte_v128u32_t eseg;
+};
+
 /* WQE. */
 struct mlx5_wqe64 {
        struct mlx5_wqe hdr;
        uint8_t raw[32];
-} __rte_aligned(64);
+} __rte_aligned(MLX5_WQE_SIZE);
+
+/* MPW mode. */
+enum mlx5_mpw_mode {
+       MLX5_MPW_DISABLED,
+       MLX5_MPW,
+       MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
+};
 
 /* MPW session status. */
 enum mlx5_mpw_state {
        MLX5_MPW_STATE_OPENED,
        MLX5_MPW_INL_STATE_OPENED,
+       MLX5_MPW_ENHANCED_STATE_OPENED,
        MLX5_MPW_STATE_CLOSED,
 };
 
@@ -180,10 +238,68 @@ struct mlx5_cqe {
        uint8_t rsvd2[12];
        uint32_t byte_cnt;
        uint64_t timestamp;
-       uint8_t rsvd3[4];
+       uint32_t sop_drop_qpn;
        uint16_t wqe_counter;
        uint8_t rsvd4;
        uint8_t op_own;
 };
 
+/**
+ * Convert a user mark to flow mark.
+ *
+ * @param val
+ *   Mark value to convert.
+ *
+ * @return
+ *   Converted mark value.
+ */
+static inline uint32_t
+mlx5_flow_mark_set(uint32_t val)
+{
+       uint32_t ret;
+
+       /*
+        * Add one to the user value to differentiate un-marked flows from
+        * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
+        * remains untouched.
+        */
+       if (val != MLX5_FLOW_MARK_DEFAULT)
+               ++val;
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+       /*
+        * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
+        * word, byte-swapped by the kernel on little-endian systems. In this
+        * case, left-shifting the resulting big-endian value ensures the
+        * least significant 24 bits are retained when converting it back.
+        */
+       ret = rte_cpu_to_be_32(val) >> 8;
+#else
+       ret = val;
+#endif
+       return ret;
+}
+
+/**
+ * Convert a mark to user mark.
+ *
+ * @param val
+ *   Mark value to convert.
+ *
+ * @return
+ *   Converted mark value.
+ */
+static inline uint32_t
+mlx5_flow_mark_get(uint32_t val)
+{
+       /*
+        * Subtract one from the retrieved value. It was added by
+        * mlx5_flow_mark_set() to distinguish unmarked flows.
+        */
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+       return (val >> 8) - 1;
+#else
+       return val - 1;
+#endif
+}
+
 #endif /* RTE_PMD_MLX5_PRM_H_ */