Imported Upstream version 16.11

[deb_dpdk.git] / drivers / net / mlx5 / mlx5_prm.h

diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 1c369ca..7f31a2f 100644 (file)
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -67,8 +67,15 @@
 /* Maximum number of packets a multi-packet WQE can handle. */
 #define MLX5_MPW_DSEG_MAX 5
 
-/* Room for inline data in regular work queue element. */
-#define MLX5_WQE64_INL_DATA 12
+/* WQE DWORD size */
+#define MLX5_WQE_DWORD_SIZE 16
+
+/* WQE size */
+#define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)
+
+/* Compute the number of DS. */
+#define MLX5_WQE_DS(n) \
+       (((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)
 
 /* Room for inline data in multi-packet WQE. */
 #define MLX5_MWQE64_INL_DATA 28
@@ -106,59 +113,26 @@ struct mlx5_wqe_eth_seg_small {
        uint16_t mss;
        uint32_t rsvd2;
        uint16_t inline_hdr_sz;
+       uint8_t inline_hdr[2];
 };
 
-/* Regular WQE. */
-struct mlx5_wqe_regular {
-       union {
-               struct mlx5_wqe_ctrl_seg ctrl;
-               uint32_t data[4];
-       } ctrl;
-       struct mlx5_wqe_eth_seg eseg;
-       struct mlx5_wqe_data_seg dseg;
-} __rte_aligned(64);
-
-/* Inline WQE. */
-struct mlx5_wqe_inl {
-       union {
-               struct mlx5_wqe_ctrl_seg ctrl;
-               uint32_t data[4];
-       } ctrl;
-       struct mlx5_wqe_eth_seg eseg;
+struct mlx5_wqe_inl_small {
        uint32_t byte_cnt;
-       uint8_t data[MLX5_WQE64_INL_DATA];
-} __rte_aligned(64);
+       uint8_t raw;
+};
 
-/* Multi-packet WQE. */
-struct mlx5_wqe_mpw {
-       union {
-               struct mlx5_wqe_ctrl_seg ctrl;
-               uint32_t data[4];
-       } ctrl;
+/* Small common part of the WQE. */
+struct mlx5_wqe {
+       uint32_t ctrl[4];
        struct mlx5_wqe_eth_seg_small eseg;
-       struct mlx5_wqe_data_seg dseg[2];
-} __rte_aligned(64);
+};
 
-/* Multi-packet WQE with inline. */
-struct mlx5_wqe_mpw_inl {
-       union {
-               struct mlx5_wqe_ctrl_seg ctrl;
-               uint32_t data[4];
-       } ctrl;
-       struct mlx5_wqe_eth_seg_small eseg;
-       uint32_t byte_cnt;
-       uint8_t data[MLX5_MWQE64_INL_DATA];
+/* WQE. */
+struct mlx5_wqe64 {
+       struct mlx5_wqe hdr;
+       uint8_t raw[32];
 } __rte_aligned(64);
 
-/* Union of all WQE types. */
-union mlx5_wqe {
-       struct mlx5_wqe_regular wqe;
-       struct mlx5_wqe_inl inl;
-       struct mlx5_wqe_mpw mpw;
-       struct mlx5_wqe_mpw_inl mpw_inl;
-       uint8_t data[64];
-};
-
 /* MPW session status. */
 enum mlx5_mpw_state {
        MLX5_MPW_STATE_OPENED,
@@ -172,7 +146,7 @@ struct mlx5_mpw {
        unsigned int pkts_n;
        unsigned int len;
        unsigned int total_len;
-       volatile union mlx5_wqe *wqe;
+       volatile struct mlx5_wqe *wqe;
        union {
                volatile struct mlx5_wqe_data_seg *dseg[MLX5_MPW_DSEG_MAX];
                volatile uint8_t *raw;
@@ -184,7 +158,21 @@ struct mlx5_cqe {
 #if (RTE_CACHE_LINE_SIZE == 128)
        uint8_t padding[64];
 #endif
-       struct mlx5_cqe64 cqe64;
+       uint8_t pkt_info;
+       uint8_t rsvd0[11];
+       uint32_t rx_hash_res;
+       uint8_t rx_hash_type;
+       uint8_t rsvd1[11];
+       uint8_t hds_ip_ext;
+       uint8_t l4_hdr_type_etc;
+       uint16_t vlan_info;
+       uint8_t rsvd2[12];
+       uint32_t byte_cnt;
+       uint64_t timestamp;
+       uint8_t rsvd3[4];
+       uint16_t wqe_counter;
+       uint8_t rsvd4;
+       uint8_t op_own;
 };
 
 #endif /* RTE_PMD_MLX5_PRM_H_ */