New upstream version 18.08

[deb_dpdk.git] / drivers / net / sfc / base / ef10_impl.h

diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h
index e79f4d5..4751faf 100644 (file)
--- a/drivers/net/sfc/base/ef10_impl.h
+++ b/drivers/net/sfc/base/ef10_impl.h
@@ -11,13 +11,27 @@
 extern "C" {
 #endif
 
-#if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD)
-#define        EF10_MAX_PIOBUF_NBUFS   MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS)
-#elif EFSYS_OPT_HUNTINGTON
-#define        EF10_MAX_PIOBUF_NBUFS   HUNT_PIOBUF_NBUFS
-#elif EFSYS_OPT_MEDFORD
-#define        EF10_MAX_PIOBUF_NBUFS   MEDFORD_PIOBUF_NBUFS
-#endif
+
+/* Number of hardware PIO buffers (for compile-time resource dimensions) */
+#define        EF10_MAX_PIOBUF_NBUFS   (16)
+
+#if EFSYS_OPT_HUNTINGTON
+# if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
+#  error "EF10_MAX_PIOBUF_NBUFS too small"
+# endif
+#endif /* EFSYS_OPT_HUNTINGTON */
+#if EFSYS_OPT_MEDFORD
+# if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
+#  error "EF10_MAX_PIOBUF_NBUFS too small"
+# endif
+#endif /* EFSYS_OPT_MEDFORD */
+#if EFSYS_OPT_MEDFORD2
+# if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
+#  error "EF10_MAX_PIOBUF_NBUFS too small"
+# endif
+#endif /* EFSYS_OPT_MEDFORD2 */
+
+
 
 /*
  * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
@@ -742,6 +756,7 @@ extern      void
 ef10_tx_qdesc_tso2_create(
        __in                    efx_txq_t *etp,
        __in                    uint16_t ipv4_id,
+       __in                    uint16_t outer_ipv4_id,
        __in                    uint32_t tcp_seq,
        __in                    uint16_t tcp_mss,
        __out_ecount(count)     efx_desc_t *edp,
@@ -753,6 +768,11 @@ ef10_tx_qdesc_vlantci_create(
        __in    uint16_t vlan_tci,
        __out   efx_desc_t *edp);
 
+extern void
+ef10_tx_qdesc_checksum_create(
+       __in    efx_txq_t *etp,
+       __in    uint16_t flags,
+       __out   efx_desc_t *edp);
 
 #if EFSYS_OPT_QSTATS
 
@@ -947,13 +967,15 @@ extern            void
 ef10_rx_qenable(
        __in            efx_rxq_t *erp);
 
+union efx_rxq_type_data_u;
+
 extern __checkReturn   efx_rc_t
 ef10_rx_qcreate(
        __in            efx_nic_t *enp,
        __in            unsigned int index,
        __in            unsigned int label,
        __in            efx_rxq_type_t type,
-       __in            uint32_t type_data,
+       __in            const union efx_rxq_type_data_u *type_data,
        __in            efsys_mem_t *esmp,
        __in            size_t ndescs,
        __in            uint32_t id,
@@ -1130,6 +1152,11 @@ efx_mcdi_get_clock(
        __out           uint32_t *dpcpu_freqp);
 
 
+extern __checkReturn   efx_rc_t
+efx_mcdi_get_rxdp_config(
+       __in            efx_nic_t *enp,
+       __out           uint32_t *end_paddingp);
+
 extern __checkReturn   efx_rc_t
 efx_mcdi_get_vector_cfg(
        __in            efx_nic_t *enp,
@@ -1137,20 +1164,27 @@ efx_mcdi_get_vector_cfg(
        __out_opt       uint32_t *pf_nvecp,
        __out_opt       uint32_t *vf_nvecp);
 
-extern __checkReturn   efx_rc_t
-ef10_get_datapath_caps(
-       __in            efx_nic_t *enp);
-
 extern __checkReturn           efx_rc_t
 ef10_get_privilege_mask(
        __in                    efx_nic_t *enp,
        __out                   uint32_t *maskp);
 
+#if EFSYS_OPT_FW_SUBVARIANT_AWARE
+
 extern __checkReturn   efx_rc_t
-ef10_external_port_mapping(
+efx_mcdi_get_nic_global(
        __in            efx_nic_t *enp,
-       __in            uint32_t port,
-       __out           uint8_t *external_portp);
+       __in            uint32_t key,
+       __out           uint32_t *valuep);
+
+extern __checkReturn   efx_rc_t
+efx_mcdi_set_nic_global(
+       __in            efx_nic_t *enp,
+       __in            uint32_t key,
+       __in            uint32_t value);
+
+#endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
+
 
 #if EFSYS_OPT_RX_PACKED_STREAM
 
@@ -1182,6 +1216,16 @@ ef10_external_port_mapping(
 
 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
 
+#if EFSYS_OPT_RX_ES_SUPER_BUFFER
+
+/*
+ * Maximum DMA length and buffer stride alignment.
+ * (see SF-119419-TC, 3.2)
+ */
+#define        EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT    64
+
+#endif
+
 #ifdef __cplusplus
 }
 #endif