New upstream version 17.11~rc4

[deb_dpdk.git] / drivers / net / virtio / virtio_pci.c

diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c
index 55b717c..9574498 100644 (file)
--- a/drivers/net/virtio/virtio_pci.c
+++ b/drivers/net/virtio/virtio_pci.c
@@ -57,7 +57,8 @@
  * The remaining space is defined by each driver as the per-driver
  * configuration space.
  */
-#define VIRTIO_PCI_CONFIG(hw) (((hw)->use_msix) ? 24 : 20)
+#define VIRTIO_PCI_CONFIG(hw) \
+               (((hw)->use_msix == VIRTIO_MSIX_ENABLED) ? 24 : 20)
 
 static inline int
 check_vq_phys_addr_ok(struct virtqueue *vq)
@@ -617,7 +618,9 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)
                        uint16_t flags = ((uint16_t *)&cap)[1];
 
                        if (flags & PCI_MSIX_ENABLE)
-                               hw->use_msix = 1;
+                               hw->use_msix = VIRTIO_MSIX_ENABLED;
+                       else
+                               hw->use_msix = VIRTIO_MSIX_DISABLED;
                }
 
                if (cap.cap_vndr != PCI_CAP_ID_VNDR) {
@@ -710,3 +713,39 @@ vtpci_init(struct rte_pci_device *dev, struct virtio_hw *hw)
 
        return 0;
 }
+
+enum virtio_msix_status
+vtpci_msix_detect(struct rte_pci_device *dev)
+{
+       uint8_t pos;
+       struct virtio_pci_cap cap;
+       int ret;
+
+       ret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
+       if (ret < 0) {
+               PMD_INIT_LOG(DEBUG, "failed to read pci capability list");
+               return VIRTIO_MSIX_NONE;
+       }
+
+       while (pos) {
+               ret = rte_pci_read_config(dev, &cap, sizeof(cap), pos);
+               if (ret < 0) {
+                       PMD_INIT_LOG(ERR,
+                               "failed to read pci cap at pos: %x", pos);
+                       break;
+               }
+
+               if (cap.cap_vndr == PCI_CAP_ID_MSIX) {
+                       uint16_t flags = ((uint16_t *)&cap)[1];
+
+                       if (flags & PCI_MSIX_ENABLE)
+                               return VIRTIO_MSIX_ENABLED;
+                       else
+                               return VIRTIO_MSIX_DISABLED;
+               }
+
+               pos = cap.cap_next;
+       }
+
+       return VIRTIO_MSIX_NONE;
+}