X-Git-Url: https://gerrit.fd.io/r/gitweb?p=deb_dpdk.git;a=blobdiff_plain;f=examples%2Fip_pipeline%2Fconfig%2Fedge_router_downstream.cfg;h=c6b4e1f29e37800ae9f7dbeaee794dc825b02b4d;hp=85bbab8ff565339eec29845d87ec55601e2e337f;hb=8b25d1ad5d2264bdfc2818c7bda74ee2697df6db;hpb=97f17497d162afdb82c8704bf097f0fee3724b2e

diff --git a/examples/ip_pipeline/config/edge_router_downstream.cfg b/examples/ip_pipeline/config/edge_router_downstream.cfg
index 85bbab8f..c6b4e1f2 100644
--- a/examples/ip_pipeline/config/edge_router_downstream.cfg
+++ b/examples/ip_pipeline/config/edge_router_downstream.cfg
@@ -1,6 +1,6 @@
 ;   BSD LICENSE
 ;
-;   Copyright(c) 2015 Intel Corporation. All rights reserved.
+;   Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
 ;   All rights reserved.
 ;
 ;   Redistribution and use in source and binary forms, with or without
@@ -36,9 +36,9 @@
 ;   network) contains the following functional blocks: Packet RX & Routing,
 ;   Traffic management and Packet TX. The input packets are assumed to be
 ;   IPv4, while the output packets are Q-in-Q IPv4.
-
+;
 ;  A simple implementation for this functional pipeline is presented below.
-
+;
 ;                  Packet Rx &                Traffic Management               Packet Tx
 ;                   Routing                    (Pass-Through)                (Pass-Through)
 ;             _____________________  SWQ0  ______________________  SWQ4  _____________________
@@ -50,11 +50,23 @@
 ;            |                     | SWQ3 |                      | SWQ7 |                     |
 ; RXQ3.0 --->|                     |----->|                      |----->|                     |---> TXQ3.0
 ;            |_____________________|      |______________________|      |_____________________|
-;                       |                 _|_ ^ _|_ ^ _|_ ^ _|_ ^
-;                       |                |___|||___|||___|||___||
-;                       +--> SINK0       |___|||___|||___|||___||
-;                      (route miss)        |__|  |__|  |__|  |__|
-;                                          TM0   TM1   TM2   TM3
+;                       |                  |  ^  |  ^  |  ^  |  ^
+;                       |                  |__|  |__|  |__|  |__|
+;                       +--> SINK0          TM0   TM1   TM2   TM3
+;                      (Default)
+;
+; Input packet: Ethernet/IPv4
+; Output packet: Ethernet/QinQ/IPv4
+;
+; Packet buffer layout:
+; #	Field Name		Offset (Bytes)	Size (Bytes)
+; 0	Mbuf			0 		128
+; 1	Headroom		128 		128
+; 2	Ethernet header		256 		14
+; 3	IPv4 header		270 		20
+
+[EAL]
+log_level = 0
 
 [PIPELINE0]
 type = MASTER
@@ -67,7 +79,7 @@ pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
 pktq_out = SWQ0 SWQ1 SWQ2 SWQ3 SINK0
 encap = ethernet_qinq
 qinq_sched = test
-ip_hdr_offset = 270; mbuf (128) + headroom (128) + ethernet header (14) = 270
+ip_hdr_offset = 270
 
 [PIPELINE2]
 type = PASS-THROUGH