uword save_vpm_start, save_vpm_end, save_vpm_size;
struct rte_mempool_memhdr *memhdr;
- this_pool_start = ~0ULL;
- this_pool_end = 0LL;
+ this_pool_start = ~0;
+ this_pool_end = 0;
STAILQ_FOREACH (memhdr, &rmp->mem_list, next)
{
if (((uword) memhdr->addr) < this_pool_start)
this_pool_start = (uword) (memhdr->addr);
}
- ASSERT (this_pool_start < ~0ULL && this_pool_end > 0);
+ ASSERT (this_pool_start < ~0 && this_pool_end > 0);
this_pool_size = this_pool_end - this_pool_start;
if (CLIB_DEBUG > 1)