#undef _
};
+#ifndef MLX5_ETH_L2_INLINE_HEADER_SIZE
+#define MLX5_ETH_L2_INLINE_HEADER_SIZE 18
+#endif
+
typedef struct
{
CLIB_ALIGN_MARK (align0, MLX5_SEND_WQE_BB);
- struct mlx5_wqe_ctrl_seg ctrl;
+ union
+ {
+ struct mlx5_wqe_ctrl_seg ctrl;
+ struct
+ {
+ u8 opc_mod;
+ u8 wqe_index_hi;
+ u8 wqe_index_lo;
+ u8 opcode;
+ };
+ };
struct mlx5_wqe_eth_seg eseg;
struct mlx5_wqe_data_seg dseg;
} rdma_mlx5_wqe_t;
struct ibv_context *ctx;
struct ibv_pd *pd;
struct ibv_mr *mr;
- struct ibv_qp *rx_qp;
+ struct ibv_qp *rx_qp4;
+ struct ibv_qp *rx_qp6;
struct ibv_rwq_ind_table *rx_rwq_ind_tbl;
- struct ibv_flow *flow_ucast;
- struct ibv_flow *flow_mcast;
+ struct ibv_flow *flow_ucast4;
+ struct ibv_flow *flow_mcast4;
+ struct ibv_flow *flow_ucast6;
+ struct ibv_flow *flow_mcast6;
clib_error_t *error;
} rdma_device_t;