u16 size;
u8 int_mode;
u8 buffer_pool_index;
+ u32 queue_index;
vmxnet3_rx_ring rx_ring[VMXNET3_RX_RING_SIZE];
vmxnet3_rx_desc *rx_desc[VMXNET3_RX_RING_SIZE];
vmxnet3_rx_comp *rx_comp;
{
CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
u16 size;
+ u32 queue_index;
u32 reg_txprod;
clib_spinlock_t lock;
void *queues;
vmxnet3_rss_shared *rss;
u32 link_speed;
- u8 lro_enable;
+ u8 gso_enable;
vmxnet3_tx_stats *tx_stats;
vmxnet3_rx_stats *rx_stats;
} vmxnet3_device_t;
vmxnet3_device_t *devices;
u16 msg_id_base;
vlib_log_class_t log_default;
- u8 lro_configured;
} vmxnet3_main_t;
extern vmxnet3_main_t vmxnet3_main;
u16 rxq_num;
u16 txq_size;
u16 txq_num;
+ u8 bind;
+ u8 enable_gso;
/* return */
i32 rv;
u32 sw_if_index;