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(parent: 5a58e7c) | patch
ip: speed up reassembly code compilation 27/34327/2
authorKlement Sekera <ksekera@cisco.com>
Tue, 2 Nov 2021 14:33:55 +0000 (15:33 +0100)
committerOle Tr�an <otroan@employees.org>
Thu, 4 Nov 2021 13:30:21 +0000 (13:30 +0000)
commitd4ba0d1883d24cc03f5435fe71368d49e01761cb
tree974921788a927c6c537b5d28c3edcf1dc3a7b2d4tree | snapshot
parent5a58e7c546239da5c500611d60cf4e7635f138c5commit | diff
ip: speed up reassembly code compilation

Refactor code so that code is inlined in one place instead of in
multiple to speed up compilation.

Type: refactor
Change-Id: I41357b89715b66ebdc8c0d5ccd69347a254fc266
Signed-off-by: Klement Sekera <ksekera@cisco.com>
src/vnet/ip/reass/ip4_full_reass.c diff | blob | history
src/vnet/ip/reass/ip4_sv_reass.c diff | blob | history
src/vnet/ip/reass/ip6_full_reass.c diff | blob | history
src/vnet/ip/reass/ip6_sv_reass.c diff | blob | history
Vector Packet Processing