4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_ethdev.h>
39 #include <rte_malloc.h>
40 #include <rte_cycles.h>
44 #include "bnxt_filter.h"
45 #include "bnxt_hwrm.h"
47 #include "bnxt_ring.h"
50 #include "bnxt_stats.h"
53 #include "bnxt_vnic.h"
54 #include "hsi_struct_def_dpdk.h"
56 #define DRV_MODULE_NAME "bnxt"
57 static const char bnxt_version[] =
58 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
60 #define PCI_VENDOR_ID_BROADCOM 0x14E4
62 #define BROADCOM_DEV_ID_57301 0x16c8
63 #define BROADCOM_DEV_ID_57302 0x16c9
64 #define BROADCOM_DEV_ID_57304_PF 0x16ca
65 #define BROADCOM_DEV_ID_57304_VF 0x16cb
66 #define BROADCOM_DEV_ID_57417_MF 0x16cc
67 #define BROADCOM_DEV_ID_NS2 0x16cd
68 #define BROADCOM_DEV_ID_57311 0x16ce
69 #define BROADCOM_DEV_ID_57312 0x16cf
70 #define BROADCOM_DEV_ID_57402 0x16d0
71 #define BROADCOM_DEV_ID_57404 0x16d1
72 #define BROADCOM_DEV_ID_57406_PF 0x16d2
73 #define BROADCOM_DEV_ID_57406_VF 0x16d3
74 #define BROADCOM_DEV_ID_57402_MF 0x16d4
75 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
76 #define BROADCOM_DEV_ID_57412 0x16d6
77 #define BROADCOM_DEV_ID_57414 0x16d7
78 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
79 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
80 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
81 #define BROADCOM_DEV_ID_57412_MF 0x16de
82 #define BROADCOM_DEV_ID_57314 0x16df
83 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
84 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
85 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
86 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
87 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
88 #define BROADCOM_DEV_ID_57404_MF 0x16e7
89 #define BROADCOM_DEV_ID_57406_MF 0x16e8
90 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
91 #define BROADCOM_DEV_ID_57407_MF 0x16ea
92 #define BROADCOM_DEV_ID_57414_MF 0x16ec
93 #define BROADCOM_DEV_ID_57416_MF 0x16ee
95 static struct rte_pci_id bnxt_pci_id_map[] = {
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
128 { .vendor_id = 0, /* sentinel */ },
131 #define BNXT_ETH_RSS_SUPPORT ( \
133 ETH_RSS_NONFRAG_IPV4_TCP | \
134 ETH_RSS_NONFRAG_IPV4_UDP | \
136 ETH_RSS_NONFRAG_IPV6_TCP | \
137 ETH_RSS_NONFRAG_IPV6_UDP)
139 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
140 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
142 /***********************/
145 * High level utility functions
148 static void bnxt_free_mem(struct bnxt *bp)
150 bnxt_free_filter_mem(bp);
151 bnxt_free_vnic_attributes(bp);
152 bnxt_free_vnic_mem(bp);
155 bnxt_free_tx_rings(bp);
156 bnxt_free_rx_rings(bp);
157 bnxt_free_def_cp_ring(bp);
160 static int bnxt_alloc_mem(struct bnxt *bp)
164 /* Default completion ring */
165 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
169 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
170 bp->def_cp_ring, "def_cp");
174 rc = bnxt_alloc_vnic_mem(bp);
178 rc = bnxt_alloc_vnic_attributes(bp);
182 rc = bnxt_alloc_filter_mem(bp);
193 static int bnxt_init_chip(struct bnxt *bp)
195 unsigned int i, rss_idx, fw_idx;
196 struct rte_eth_link new;
199 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
201 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
205 rc = bnxt_alloc_hwrm_rings(bp);
207 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
211 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
213 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
217 rc = bnxt_mq_rx_configure(bp);
219 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
223 /* VNIC configuration */
224 for (i = 0; i < bp->nr_vnics; i++) {
225 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
226 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
228 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
229 if (!vnic->fw_grp_ids) {
231 "Failed to alloc %d bytes for group ids\n",
236 memset(vnic->fw_grp_ids, -1, size);
238 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
240 RTE_LOG(ERR, PMD, "HWRM vnic alloc failure rc: %x\n",
245 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
248 "HWRM vnic ctx alloc failure rc: %x\n", rc);
252 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
254 RTE_LOG(ERR, PMD, "HWRM vnic cfg failure rc: %x\n", rc);
258 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
260 RTE_LOG(ERR, PMD, "HWRM vnic filter failure rc: %x\n",
264 if (vnic->rss_table && vnic->hash_type) {
266 * Fill the RSS hash & redirection table with
267 * ring group ids for all VNICs
269 for (rss_idx = 0, fw_idx = 0;
270 rss_idx < HW_HASH_INDEX_SIZE;
271 rss_idx++, fw_idx++) {
272 if (vnic->fw_grp_ids[fw_idx] ==
275 vnic->rss_table[rss_idx] =
276 vnic->fw_grp_ids[fw_idx];
278 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
281 "HWRM vnic set RSS failure rc: %x\n",
287 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
290 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
294 rc = bnxt_get_hwrm_link_config(bp, &new);
296 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
300 if (!bp->link_info.link_up) {
301 rc = bnxt_set_hwrm_link_config(bp, true);
304 "HWRM link config failure rc: %x\n", rc);
308 bnxt_print_link_info(bp->eth_dev);
313 bnxt_free_all_hwrm_resources(bp);
318 static int bnxt_shutdown_nic(struct bnxt *bp)
320 bnxt_free_all_hwrm_resources(bp);
321 bnxt_free_all_filters(bp);
322 bnxt_free_all_vnics(bp);
326 static int bnxt_init_nic(struct bnxt *bp)
330 rc = bnxt_init_ring_grps(bp);
334 bnxt_init_filters(bp);
336 rc = bnxt_init_chip(bp);
344 * Device configuration and status function
347 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
348 struct rte_eth_dev_info *dev_info)
350 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
351 uint16_t max_vnics, i, j, vpool, vrxq;
354 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
355 dev_info->max_hash_mac_addrs = 0;
357 /* PF/VF specifics */
359 dev_info->max_rx_queues = bp->pf.max_rx_rings;
360 dev_info->max_tx_queues = bp->pf.max_tx_rings;
361 dev_info->max_vfs = bp->pf.active_vfs;
362 dev_info->reta_size = HW_HASH_INDEX_SIZE;
363 max_vnics = bp->pf.max_vnics;
365 dev_info->max_rx_queues = bp->vf.max_rx_rings;
366 dev_info->max_tx_queues = bp->vf.max_tx_rings;
367 dev_info->reta_size = HW_HASH_INDEX_SIZE;
368 max_vnics = bp->vf.max_vnics;
371 /* Fast path specifics */
372 dev_info->min_rx_bufsize = 1;
373 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
375 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
376 DEV_RX_OFFLOAD_IPV4_CKSUM |
377 DEV_RX_OFFLOAD_UDP_CKSUM |
378 DEV_RX_OFFLOAD_TCP_CKSUM |
379 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
380 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
381 DEV_TX_OFFLOAD_IPV4_CKSUM |
382 DEV_TX_OFFLOAD_TCP_CKSUM |
383 DEV_TX_OFFLOAD_UDP_CKSUM |
384 DEV_TX_OFFLOAD_TCP_TSO;
387 dev_info->default_rxconf = (struct rte_eth_rxconf) {
393 .rx_free_thresh = 32,
394 /* If no descriptors available, pkts are dropped by default */
398 dev_info->default_txconf = (struct rte_eth_txconf) {
404 .tx_free_thresh = 32,
406 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
407 ETH_TXQ_FLAGS_NOOFFLOADS,
409 eth_dev->data->dev_conf.intr_conf.lsc = 1;
414 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
415 * need further investigation.
419 vpool = 64; /* ETH_64_POOLS */
420 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
421 for (i = 0; i < 4; vpool >>= 1, i++) {
422 if (max_vnics > vpool) {
423 for (j = 0; j < 5; vrxq >>= 1, j++) {
424 if (dev_info->max_rx_queues > vrxq) {
430 /* Not enough resources to support VMDq */
434 /* Not enough resources to support VMDq */
438 dev_info->max_vmdq_pools = vpool;
439 dev_info->vmdq_queue_num = vrxq;
441 dev_info->vmdq_pool_base = 0;
442 dev_info->vmdq_queue_base = 0;
445 /* Configure the device based on the configuration provided */
446 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
448 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
450 bp->rx_queues = (void *)eth_dev->data->rx_queues;
451 bp->tx_queues = (void *)eth_dev->data->tx_queues;
453 /* Inherit new configurations */
454 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
455 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
456 bp->rx_cp_nr_rings = bp->rx_nr_rings;
457 bp->tx_cp_nr_rings = bp->tx_nr_rings;
459 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
461 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
462 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
466 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
468 struct rte_eth_link *link = ð_dev->data->dev_link;
470 if (link->link_status)
471 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
472 (uint8_t)(eth_dev->data->port_id),
473 (uint32_t)link->link_speed,
474 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
475 ("full-duplex") : ("half-duplex\n"));
477 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
478 (uint8_t)(eth_dev->data->port_id));
481 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
483 bnxt_print_link_info(eth_dev);
487 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
489 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
493 rc = bnxt_hwrm_func_reset(bp);
495 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
500 rc = bnxt_setup_int(bp);
504 rc = bnxt_alloc_mem(bp);
508 rc = bnxt_request_int(bp);
512 rc = bnxt_init_nic(bp);
518 bnxt_link_update_op(eth_dev, 1);
522 bnxt_shutdown_nic(bp);
523 bnxt_disable_int(bp);
525 bnxt_free_tx_mbufs(bp);
526 bnxt_free_rx_mbufs(bp);
531 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
533 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
536 if (!bp->link_info.link_up)
537 rc = bnxt_set_hwrm_link_config(bp, true);
539 eth_dev->data->dev_link.link_status = 1;
541 bnxt_print_link_info(eth_dev);
545 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
547 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
549 eth_dev->data->dev_link.link_status = 0;
550 bnxt_set_hwrm_link_config(bp, false);
551 bp->link_info.link_up = 0;
556 /* Unload the driver, release resources */
557 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
559 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
561 if (bp->eth_dev->data->dev_started) {
562 /* TBD: STOP HW queues DMA */
563 eth_dev->data->dev_link.link_status = 0;
565 bnxt_set_hwrm_link_config(bp, false);
566 bnxt_disable_int(bp);
568 bnxt_free_tx_mbufs(bp);
569 bnxt_free_rx_mbufs(bp);
570 bnxt_shutdown_nic(bp);
574 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
576 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
578 if (bp->dev_stopped == 0)
579 bnxt_dev_stop_op(eth_dev);
582 if (eth_dev->data->mac_addrs != NULL) {
583 rte_free(eth_dev->data->mac_addrs);
584 eth_dev->data->mac_addrs = NULL;
586 if (bp->grp_info != NULL) {
587 rte_free(bp->grp_info);
591 bnxt_dev_uninit(eth_dev);
594 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
597 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
598 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
599 struct bnxt_vnic_info *vnic;
600 struct bnxt_filter_info *filter, *temp_filter;
601 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
605 * Loop through all VNICs from the specified filter flow pools to
606 * remove the corresponding MAC addr filter
608 for (i = 0; i < pool; i++) {
609 if (!(pool_mask & (1ULL << i)))
612 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
613 filter = STAILQ_FIRST(&vnic->filter);
615 temp_filter = STAILQ_NEXT(filter, next);
616 if (filter->mac_index == index) {
617 STAILQ_REMOVE(&vnic->filter, filter,
618 bnxt_filter_info, next);
619 bnxt_hwrm_clear_filter(bp, filter);
620 filter->mac_index = INVALID_MAC_INDEX;
621 memset(&filter->l2_addr, 0,
624 &bp->free_filter_list,
627 filter = temp_filter;
633 static void bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
634 struct ether_addr *mac_addr,
635 uint32_t index, uint32_t pool)
637 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
638 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
639 struct bnxt_filter_info *filter;
642 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
647 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
650 /* Attach requested MAC address to the new l2_filter */
651 STAILQ_FOREACH(filter, &vnic->filter, next) {
652 if (filter->mac_index == index) {
654 "MAC addr already existed for pool %d\n", pool);
658 filter = bnxt_alloc_filter(bp);
660 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
663 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
664 filter->mac_index = index;
665 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
666 bnxt_hwrm_set_filter(bp, vnic, filter);
669 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
672 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
673 struct rte_eth_link new;
674 unsigned int cnt = BNXT_LINK_WAIT_CNT;
676 memset(&new, 0, sizeof(new));
678 /* Retrieve link info from hardware */
679 rc = bnxt_get_hwrm_link_config(bp, &new);
681 new.link_speed = ETH_LINK_SPEED_100M;
682 new.link_duplex = ETH_LINK_FULL_DUPLEX;
684 "Failed to retrieve link rc = 0x%x!", rc);
687 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
689 if (!wait_to_complete)
691 } while (!new.link_status && cnt--);
694 /* Timed out or success */
695 if (new.link_status != eth_dev->data->dev_link.link_status ||
696 new.link_speed != eth_dev->data->dev_link.link_speed) {
697 memcpy(ð_dev->data->dev_link, &new,
698 sizeof(struct rte_eth_link));
699 bnxt_print_link_info(eth_dev);
705 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
707 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
708 struct bnxt_vnic_info *vnic;
710 if (bp->vnic_info == NULL)
713 vnic = &bp->vnic_info[0];
715 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
716 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
719 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
721 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
722 struct bnxt_vnic_info *vnic;
724 if (bp->vnic_info == NULL)
727 vnic = &bp->vnic_info[0];
729 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
730 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
733 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
735 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
736 struct bnxt_vnic_info *vnic;
738 if (bp->vnic_info == NULL)
741 vnic = &bp->vnic_info[0];
743 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
744 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
747 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
749 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
750 struct bnxt_vnic_info *vnic;
752 if (bp->vnic_info == NULL)
755 vnic = &bp->vnic_info[0];
757 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
758 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
761 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
762 struct rte_eth_rss_reta_entry64 *reta_conf,
765 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
766 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
767 struct bnxt_vnic_info *vnic;
770 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
773 if (reta_size != HW_HASH_INDEX_SIZE) {
774 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
775 "(%d) must equal the size supported by the hardware "
776 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
779 /* Update the RSS VNIC(s) */
780 for (i = 0; i < MAX_FF_POOLS; i++) {
781 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
782 memcpy(vnic->rss_table, reta_conf, reta_size);
784 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
790 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
791 struct rte_eth_rss_reta_entry64 *reta_conf,
794 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
795 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
797 /* Retrieve from the default VNIC */
800 if (!vnic->rss_table)
803 if (reta_size != HW_HASH_INDEX_SIZE) {
804 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
805 "(%d) must equal the size supported by the hardware "
806 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
809 /* EW - need to revisit here copying from u64 to u16 */
810 memcpy(reta_conf, vnic->rss_table, reta_size);
812 if (rte_intr_allow_others(ð_dev->pci_dev->intr_handle)) {
813 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
814 bnxt_dev_lsc_intr_setup(eth_dev);
820 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
821 struct rte_eth_rss_conf *rss_conf)
823 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
824 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
825 struct bnxt_vnic_info *vnic;
826 uint16_t hash_type = 0;
830 * If RSS enablement were different than dev_configure,
831 * then return -EINVAL
833 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
834 if (!rss_conf->rss_hf)
837 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
840 if (rss_conf->rss_hf & ETH_RSS_IPV4)
841 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
842 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
843 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
844 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
845 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
846 if (rss_conf->rss_hf & ETH_RSS_IPV6)
847 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
848 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
849 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
850 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
851 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
853 /* Update the RSS VNIC(s) */
854 for (i = 0; i < MAX_FF_POOLS; i++) {
855 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
856 vnic->hash_type = hash_type;
859 * Use the supplied key if the key length is
860 * acceptable and the rss_key is not NULL
862 if (rss_conf->rss_key &&
863 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
864 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
865 rss_conf->rss_key_len);
867 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
873 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
874 struct rte_eth_rss_conf *rss_conf)
876 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
877 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
881 /* RSS configuration is the same for all VNICs */
882 if (vnic && vnic->rss_hash_key) {
883 if (rss_conf->rss_key) {
884 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
885 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
886 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
889 hash_types = vnic->hash_type;
890 rss_conf->rss_hf = 0;
891 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
892 rss_conf->rss_hf |= ETH_RSS_IPV4;
893 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
895 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
896 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
898 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
900 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
901 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
903 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
905 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
906 rss_conf->rss_hf |= ETH_RSS_IPV6;
907 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
909 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
910 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
912 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
914 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
915 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
917 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
921 "Unknwon RSS config from firmware (%08x), RSS disabled",
926 rss_conf->rss_hf = 0;
931 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
932 struct rte_eth_fc_conf *fc_conf __rte_unused)
934 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
935 struct rte_eth_link link_info;
938 rc = bnxt_get_hwrm_link_config(bp, &link_info);
942 memset(fc_conf, 0, sizeof(*fc_conf));
943 if (bp->link_info.auto_pause)
944 fc_conf->autoneg = 1;
945 switch (bp->link_info.pause) {
947 fc_conf->mode = RTE_FC_NONE;
949 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
950 fc_conf->mode = RTE_FC_TX_PAUSE;
952 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
953 fc_conf->mode = RTE_FC_RX_PAUSE;
955 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
956 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
957 fc_conf->mode = RTE_FC_FULL;
963 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
964 struct rte_eth_fc_conf *fc_conf)
966 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
968 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
969 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
973 switch (fc_conf->mode) {
975 bp->link_info.auto_pause = 0;
976 bp->link_info.force_pause = 0;
978 case RTE_FC_RX_PAUSE:
979 if (fc_conf->autoneg) {
980 bp->link_info.auto_pause =
981 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
982 bp->link_info.force_pause = 0;
984 bp->link_info.auto_pause = 0;
985 bp->link_info.force_pause =
986 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
989 case RTE_FC_TX_PAUSE:
990 if (fc_conf->autoneg) {
991 bp->link_info.auto_pause =
992 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
993 bp->link_info.force_pause = 0;
995 bp->link_info.auto_pause = 0;
996 bp->link_info.force_pause =
997 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1001 if (fc_conf->autoneg) {
1002 bp->link_info.auto_pause =
1003 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1004 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1005 bp->link_info.force_pause = 0;
1007 bp->link_info.auto_pause = 0;
1008 bp->link_info.force_pause =
1009 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1010 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1014 return bnxt_set_hwrm_link_config(bp, true);
1021 static struct eth_dev_ops bnxt_dev_ops = {
1022 .dev_infos_get = bnxt_dev_info_get_op,
1023 .dev_close = bnxt_dev_close_op,
1024 .dev_configure = bnxt_dev_configure_op,
1025 .dev_start = bnxt_dev_start_op,
1026 .dev_stop = bnxt_dev_stop_op,
1027 .dev_set_link_up = bnxt_dev_set_link_up_op,
1028 .dev_set_link_down = bnxt_dev_set_link_down_op,
1029 .stats_get = bnxt_stats_get_op,
1030 .stats_reset = bnxt_stats_reset_op,
1031 .rx_queue_setup = bnxt_rx_queue_setup_op,
1032 .rx_queue_release = bnxt_rx_queue_release_op,
1033 .tx_queue_setup = bnxt_tx_queue_setup_op,
1034 .tx_queue_release = bnxt_tx_queue_release_op,
1035 .reta_update = bnxt_reta_update_op,
1036 .reta_query = bnxt_reta_query_op,
1037 .rss_hash_update = bnxt_rss_hash_update_op,
1038 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
1039 .link_update = bnxt_link_update_op,
1040 .promiscuous_enable = bnxt_promiscuous_enable_op,
1041 .promiscuous_disable = bnxt_promiscuous_disable_op,
1042 .allmulticast_enable = bnxt_allmulticast_enable_op,
1043 .allmulticast_disable = bnxt_allmulticast_disable_op,
1044 .mac_addr_add = bnxt_mac_addr_add_op,
1045 .mac_addr_remove = bnxt_mac_addr_remove_op,
1046 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
1047 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
1050 static bool bnxt_vf_pciid(uint16_t id)
1052 if (id == BROADCOM_DEV_ID_57304_VF ||
1053 id == BROADCOM_DEV_ID_57406_VF ||
1054 id == BROADCOM_DEV_ID_5731X_VF ||
1055 id == BROADCOM_DEV_ID_5741X_VF)
1060 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
1063 struct bnxt *bp = eth_dev->data->dev_private;
1065 /* enable device (incl. PCI PM wakeup), and bus-mastering */
1066 if (!eth_dev->pci_dev->mem_resource[0].addr) {
1068 "Cannot find PCI device base address, aborting\n");
1070 goto init_err_disable;
1073 bp->eth_dev = eth_dev;
1074 bp->pdev = eth_dev->pci_dev;
1076 bp->bar0 = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1078 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
1080 goto init_err_release;
1094 bnxt_dev_init(struct rte_eth_dev *eth_dev)
1096 static int version_printed;
1100 if (version_printed++ == 0)
1101 RTE_LOG(INFO, PMD, "%s", bnxt_version);
1103 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1104 bp = eth_dev->data->dev_private;
1106 if (bnxt_vf_pciid(eth_dev->pci_dev->id.device_id))
1107 bp->flags |= BNXT_FLAG_VF;
1109 rc = bnxt_init_board(eth_dev);
1112 "Board initialization failed rc: %x\n", rc);
1115 eth_dev->dev_ops = &bnxt_dev_ops;
1116 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
1117 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
1119 rc = bnxt_alloc_hwrm_resources(bp);
1122 "hwrm resource allocation failure rc: %x\n", rc);
1125 rc = bnxt_hwrm_ver_get(bp);
1128 bnxt_hwrm_queue_qportcfg(bp);
1130 bnxt_hwrm_func_qcfg(bp);
1132 /* Get the MAX capabilities for this function */
1133 rc = bnxt_hwrm_func_qcaps(bp);
1135 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
1138 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
1139 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
1140 if (eth_dev->data->mac_addrs == NULL) {
1142 "Failed to alloc %u bytes needed to store MAC addr tbl",
1143 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
1147 /* Copy the permanent MAC from the qcap response address now. */
1149 memcpy(bp->mac_addr, bp->pf.mac_addr, sizeof(bp->mac_addr));
1151 memcpy(bp->mac_addr, bp->vf.mac_addr, sizeof(bp->mac_addr));
1152 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1153 bp->grp_info = rte_zmalloc("bnxt_grp_info",
1154 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1155 if (!bp->grp_info) {
1157 "Failed to alloc %zu bytes needed to store group info table\n",
1158 sizeof(*bp->grp_info) * bp->max_ring_grps);
1163 rc = bnxt_hwrm_func_driver_register(bp, 0,
1167 "Failed to register driver");
1173 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1174 eth_dev->pci_dev->mem_resource[0].phys_addr,
1175 eth_dev->pci_dev->mem_resource[0].addr);
1177 bp->dev_stopped = 0;
1182 eth_dev->driver->eth_dev_uninit(eth_dev);
1188 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1189 struct bnxt *bp = eth_dev->data->dev_private;
1192 if (eth_dev->data->mac_addrs != NULL) {
1193 rte_free(eth_dev->data->mac_addrs);
1194 eth_dev->data->mac_addrs = NULL;
1196 if (bp->grp_info != NULL) {
1197 rte_free(bp->grp_info);
1198 bp->grp_info = NULL;
1200 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1201 bnxt_free_hwrm_resources(bp);
1202 if (bp->dev_stopped == 0)
1203 bnxt_dev_close_op(eth_dev);
1204 eth_dev->dev_ops = NULL;
1205 eth_dev->rx_pkt_burst = NULL;
1206 eth_dev->tx_pkt_burst = NULL;
1211 static struct eth_driver bnxt_rte_pmd = {
1213 .id_table = bnxt_pci_id_map,
1214 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
1215 RTE_PCI_DRV_DETACHABLE | RTE_PCI_DRV_INTR_LSC,
1216 .probe = rte_eth_dev_pci_probe,
1217 .remove = rte_eth_dev_pci_remove
1219 .eth_dev_init = bnxt_dev_init,
1220 .eth_dev_uninit = bnxt_dev_uninit,
1221 .dev_private_size = sizeof(struct bnxt),
1224 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd.pci_drv);
1225 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);