2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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33 #if EFSYS_OPT_MON_STATS
37 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
40 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
42 (_eep)->ee_stat[_stat]++; \
43 _NOTE(CONSTANTCONDITION) \
46 #define EFX_EV_QSTAT_INCR(_eep, _stat)
50 * Non-interrupting event queue requires interrrupting event queue to
51 * refer to for wake-up events even if wake ups are never used.
52 * It could be even non-allocated event queue.
54 #define EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX (0)
56 static __checkReturn boolean_t
59 __in efx_qword_t *eqp,
60 __in const efx_ev_callbacks_t *eecp,
63 static __checkReturn boolean_t
66 __in efx_qword_t *eqp,
67 __in const efx_ev_callbacks_t *eecp,
70 static __checkReturn boolean_t
73 __in efx_qword_t *eqp,
74 __in const efx_ev_callbacks_t *eecp,
77 static __checkReturn boolean_t
80 __in efx_qword_t *eqp,
81 __in const efx_ev_callbacks_t *eecp,
84 static __checkReturn boolean_t
87 __in efx_qword_t *eqp,
88 __in const efx_ev_callbacks_t *eecp,
92 static __checkReturn efx_rc_t
95 __in uint32_t instance,
97 __in uint32_t timer_ns)
100 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_EVQ_TMR_IN_LEN,
101 MC_CMD_SET_EVQ_TMR_OUT_LEN);
104 req.emr_cmd = MC_CMD_SET_EVQ_TMR;
105 req.emr_in_buf = payload;
106 req.emr_in_length = MC_CMD_SET_EVQ_TMR_IN_LEN;
107 req.emr_out_buf = payload;
108 req.emr_out_length = MC_CMD_SET_EVQ_TMR_OUT_LEN;
110 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_INSTANCE, instance);
111 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, timer_ns);
112 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, timer_ns);
113 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_MODE, mode);
115 efx_mcdi_execute(enp, &req);
117 if (req.emr_rc != 0) {
122 if (req.emr_out_length_used < MC_CMD_SET_EVQ_TMR_OUT_LEN) {
132 EFSYS_PROBE1(fail1, efx_rc_t, rc);
137 static __checkReturn efx_rc_t
140 __in unsigned int instance,
141 __in efsys_mem_t *esmp,
146 __in boolean_t low_latency)
149 EFX_MCDI_DECLARE_BUF(payload,
150 MC_CMD_INIT_EVQ_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
151 MC_CMD_INIT_EVQ_OUT_LEN);
152 efx_qword_t *dma_addr;
156 boolean_t interrupting;
160 npages = EFX_EVQ_NBUFS(nevs);
161 if (MC_CMD_INIT_EVQ_IN_LEN(npages) > MC_CMD_INIT_EVQ_IN_LENMAX) {
166 req.emr_cmd = MC_CMD_INIT_EVQ;
167 req.emr_in_buf = payload;
168 req.emr_in_length = MC_CMD_INIT_EVQ_IN_LEN(npages);
169 req.emr_out_buf = payload;
170 req.emr_out_length = MC_CMD_INIT_EVQ_OUT_LEN;
172 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_SIZE, nevs);
173 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_INSTANCE, instance);
174 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_IRQ_NUM, irq);
176 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
177 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
180 * On Huntington RX and TX event batching can only be requested together
181 * (even if the datapath firmware doesn't actually support RX
182 * batching). If event cut through is enabled no RX batching will occur.
184 * So always enable RX and TX event batching, and enable event cut
185 * through if we want low latency operation.
187 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
188 case EFX_EVQ_FLAGS_TYPE_AUTO:
189 ev_cut_through = low_latency ? 1 : 0;
191 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
194 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
201 MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_IN_FLAGS,
202 INIT_EVQ_IN_FLAG_INTERRUPTING, interrupting,
203 INIT_EVQ_IN_FLAG_RPTR_DOS, 0,
204 INIT_EVQ_IN_FLAG_INT_ARMD, 0,
205 INIT_EVQ_IN_FLAG_CUT_THRU, ev_cut_through,
206 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
207 INIT_EVQ_IN_FLAG_TX_MERGE, 1);
209 /* If the value is zero then disable the timer */
211 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
212 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
213 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, 0);
214 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, 0);
218 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
221 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
222 MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF);
223 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, ticks);
224 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, ticks);
227 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_MODE,
228 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
229 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_THRSHLD, 0);
231 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR);
232 addr = EFSYS_MEM_ADDR(esmp);
234 for (i = 0; i < npages; i++) {
235 EFX_POPULATE_QWORD_2(*dma_addr,
236 EFX_DWORD_1, (uint32_t)(addr >> 32),
237 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
240 addr += EFX_BUF_SIZE;
243 efx_mcdi_execute(enp, &req);
245 if (req.emr_rc != 0) {
250 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) {
255 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
268 EFSYS_PROBE1(fail1, efx_rc_t, rc);
274 static __checkReturn efx_rc_t
275 efx_mcdi_init_evq_v2(
277 __in unsigned int instance,
278 __in efsys_mem_t *esmp,
285 EFX_MCDI_DECLARE_BUF(payload,
286 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
287 MC_CMD_INIT_EVQ_V2_OUT_LEN);
288 boolean_t interrupting;
289 unsigned int evq_type;
290 efx_qword_t *dma_addr;
296 npages = EFX_EVQ_NBUFS(nevs);
297 if (MC_CMD_INIT_EVQ_V2_IN_LEN(npages) > MC_CMD_INIT_EVQ_V2_IN_LENMAX) {
302 req.emr_cmd = MC_CMD_INIT_EVQ;
303 req.emr_in_buf = payload;
304 req.emr_in_length = MC_CMD_INIT_EVQ_V2_IN_LEN(npages);
305 req.emr_out_buf = payload;
306 req.emr_out_length = MC_CMD_INIT_EVQ_V2_OUT_LEN;
308 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_SIZE, nevs);
309 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_INSTANCE, instance);
310 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_IRQ_NUM, irq);
312 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
313 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
315 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
316 case EFX_EVQ_FLAGS_TYPE_AUTO:
317 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO;
319 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
320 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT;
322 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
323 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY;
329 MCDI_IN_POPULATE_DWORD_4(req, INIT_EVQ_V2_IN_FLAGS,
330 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, interrupting,
331 INIT_EVQ_V2_IN_FLAG_RPTR_DOS, 0,
332 INIT_EVQ_V2_IN_FLAG_INT_ARMD, 0,
333 INIT_EVQ_V2_IN_FLAG_TYPE, evq_type);
335 /* If the value is zero then disable the timer */
337 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
338 MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS);
339 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, 0);
340 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, 0);
344 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
347 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
348 MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF);
349 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, ticks);
350 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, ticks);
353 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_MODE,
354 MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS);
355 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_THRSHLD, 0);
357 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_V2_IN_DMA_ADDR);
358 addr = EFSYS_MEM_ADDR(esmp);
360 for (i = 0; i < npages; i++) {
361 EFX_POPULATE_QWORD_2(*dma_addr,
362 EFX_DWORD_1, (uint32_t)(addr >> 32),
363 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
366 addr += EFX_BUF_SIZE;
369 efx_mcdi_execute(enp, &req);
371 if (req.emr_rc != 0) {
376 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_V2_OUT_LEN) {
381 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
383 EFSYS_PROBE1(mcdi_evq_flags, uint32_t,
384 MCDI_OUT_DWORD(req, INIT_EVQ_V2_OUT_FLAGS));
397 EFSYS_PROBE1(fail1, efx_rc_t, rc);
402 static __checkReturn efx_rc_t
405 __in uint32_t instance)
408 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_EVQ_IN_LEN,
409 MC_CMD_FINI_EVQ_OUT_LEN);
412 req.emr_cmd = MC_CMD_FINI_EVQ;
413 req.emr_in_buf = payload;
414 req.emr_in_length = MC_CMD_FINI_EVQ_IN_LEN;
415 req.emr_out_buf = payload;
416 req.emr_out_length = MC_CMD_FINI_EVQ_OUT_LEN;
418 MCDI_IN_SET_DWORD(req, FINI_EVQ_IN_INSTANCE, instance);
420 efx_mcdi_execute_quiet(enp, &req);
422 if (req.emr_rc != 0) {
431 * EALREADY is not an error, but indicates that the MC has rebooted and
432 * that the EVQ has already been destroyed.
435 EFSYS_PROBE1(fail1, efx_rc_t, rc);
442 __checkReturn efx_rc_t
446 _NOTE(ARGUNUSED(enp))
454 _NOTE(ARGUNUSED(enp))
457 __checkReturn efx_rc_t
460 __in unsigned int index,
461 __in efsys_mem_t *esmp,
468 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
472 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
473 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
474 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
476 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
481 if (index >= encp->enc_evq_limit) {
486 if (us > encp->enc_evq_timer_max_us) {
491 /* Set up the handler table */
492 eep->ee_rx = ef10_ev_rx;
493 eep->ee_tx = ef10_ev_tx;
494 eep->ee_driver = ef10_ev_driver;
495 eep->ee_drv_gen = ef10_ev_drv_gen;
496 eep->ee_mcdi = ef10_ev_mcdi;
498 /* Set up the event queue */
499 /* INIT_EVQ expects function-relative vector number */
500 if ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
501 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {
503 } else if (index == EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX) {
505 flags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |
506 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;
508 irq = EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX;
512 * Interrupts may be raised for events immediately after the queue is
513 * created. See bug58606.
516 if (encp->enc_init_evq_v2_supported) {
518 * On Medford the low latency license is required to enable RX
519 * and event cut through and to disable RX batching. If event
520 * queue type in flags is auto, we let the firmware decide the
521 * settings to use. If the adapter has a low latency license,
522 * it will choose the best settings for low latency, otherwise
523 * it will choose the best settings for throughput.
525 rc = efx_mcdi_init_evq_v2(enp, index, esmp, n, irq, us, flags);
530 * On Huntington we need to specify the settings to use.
531 * If event queue type in flags is auto, we favour throughput
532 * if the adapter is running virtualization supporting firmware
533 * (i.e. the full featured firmware variant)
534 * and latency otherwise. The Ethernet Virtual Bridging
535 * capability is used to make this decision. (Note though that
536 * the low latency firmware variant is also best for
537 * throughput and corresponding type should be specified
540 boolean_t low_latency = encp->enc_datapath_cap_evb ? 0 : 1;
541 rc = efx_mcdi_init_evq(enp, index, esmp, n, irq, us, flags,
558 EFSYS_PROBE1(fail1, efx_rc_t, rc);
567 efx_nic_t *enp = eep->ee_enp;
569 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
570 enp->en_family == EFX_FAMILY_MEDFORD);
572 (void) efx_mcdi_fini_evq(eep->ee_enp, eep->ee_index);
575 __checkReturn efx_rc_t
578 __in unsigned int count)
580 efx_nic_t *enp = eep->ee_enp;
584 rptr = count & eep->ee_mask;
586 if (enp->en_nic_cfg.enc_bug35388_workaround) {
587 EFX_STATIC_ASSERT(EFX_EVQ_MINNEVS >
588 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
589 EFX_STATIC_ASSERT(EFX_EVQ_MAXNEVS <
590 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
592 EFX_POPULATE_DWORD_2(dword,
593 ERF_DD_EVQ_IND_RPTR_FLAGS,
594 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
596 (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
597 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
600 EFX_POPULATE_DWORD_2(dword,
601 ERF_DD_EVQ_IND_RPTR_FLAGS,
602 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
604 rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
605 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
608 EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
609 EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
616 static __checkReturn efx_rc_t
617 efx_mcdi_driver_event(
620 __in efx_qword_t data)
623 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_DRIVER_EVENT_IN_LEN,
624 MC_CMD_DRIVER_EVENT_OUT_LEN);
627 req.emr_cmd = MC_CMD_DRIVER_EVENT;
628 req.emr_in_buf = payload;
629 req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
630 req.emr_out_buf = payload;
631 req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
633 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
635 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
636 EFX_QWORD_FIELD(data, EFX_DWORD_0));
637 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
638 EFX_QWORD_FIELD(data, EFX_DWORD_1));
640 efx_mcdi_execute(enp, &req);
642 if (req.emr_rc != 0) {
650 EFSYS_PROBE1(fail1, efx_rc_t, rc);
660 efx_nic_t *enp = eep->ee_enp;
663 EFX_POPULATE_QWORD_3(event,
664 ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
665 ESF_DZ_DRV_SUB_CODE, 0,
666 ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
668 (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
671 __checkReturn efx_rc_t
674 __in unsigned int us)
676 efx_nic_t *enp = eep->ee_enp;
677 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
682 /* Check that hardware and MCDI use the same timer MODE values */
683 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
684 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS);
685 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
686 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START);
687 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
688 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START);
689 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
690 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF);
692 if (us > encp->enc_evq_timer_max_us) {
697 /* If the value is zero then disable the timer */
699 mode = FFE_CZ_TIMER_MODE_DIS;
701 mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
704 if (encp->enc_bug61265_workaround) {
705 uint32_t ns = us * 1000;
707 rc = efx_mcdi_set_evq_tmr(enp, eep->ee_index, mode, ns);
713 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
716 if (encp->enc_bug35388_workaround) {
717 EFX_POPULATE_DWORD_3(dword,
718 ERF_DD_EVQ_IND_TIMER_FLAGS,
719 EFE_DD_EVQ_IND_TIMER_FLAGS,
720 ERF_DD_EVQ_IND_TIMER_MODE, mode,
721 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
722 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT,
723 eep->ee_index, &dword, 0);
725 EFX_POPULATE_DWORD_2(dword,
726 ERF_DZ_TC_TIMER_MODE, mode,
727 ERF_DZ_TC_TIMER_VAL, ticks);
728 EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_TMR_REG,
729 eep->ee_index, &dword, 0);
740 EFSYS_PROBE1(fail1, efx_rc_t, rc);
748 ef10_ev_qstats_update(
750 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
754 for (id = 0; id < EV_NQSTATS; id++) {
755 efsys_stat_t *essp = &stat[id];
757 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
758 eep->ee_stat[id] = 0;
761 #endif /* EFSYS_OPT_QSTATS */
763 #if EFSYS_OPT_RX_PACKED_STREAM
765 static __checkReturn boolean_t
766 ef10_ev_rx_packed_stream(
768 __in efx_qword_t *eqp,
769 __in const efx_ev_callbacks_t *eecp,
773 uint32_t next_read_lbits;
775 boolean_t should_abort;
776 efx_evq_rxq_state_t *eersp;
777 unsigned int pkt_count;
778 unsigned int current_id;
779 boolean_t new_buffer;
781 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
782 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
783 new_buffer = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_ROTATE);
787 eersp = &eep->ee_rxq_state[label];
788 pkt_count = (EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS) + 1 +
789 next_read_lbits - eersp->eers_rx_stream_npackets) &
790 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
791 eersp->eers_rx_stream_npackets += pkt_count;
794 flags |= EFX_PKT_PACKED_STREAM_NEW_BUFFER;
795 if (eersp->eers_rx_packed_stream_credits <
796 EFX_RX_PACKED_STREAM_MAX_CREDITS)
797 eersp->eers_rx_packed_stream_credits++;
798 eersp->eers_rx_read_ptr++;
800 current_id = eersp->eers_rx_read_ptr & eersp->eers_rx_mask;
802 /* Check for errors that invalidate checksum and L3/L4 fields */
803 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECC_ERR) != 0) {
804 /* RX frame truncated (error flag is misnamed) */
805 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
806 flags |= EFX_DISCARD;
809 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
810 /* Bad Ethernet frame CRC */
811 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
812 flags |= EFX_DISCARD;
816 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
817 flags |= EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE;
821 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR))
822 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
824 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR))
825 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
828 /* If we're not discarding the packet then it is ok */
829 if (~flags & EFX_DISCARD)
830 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
832 EFSYS_ASSERT(eecp->eec_rx_ps != NULL);
833 should_abort = eecp->eec_rx_ps(arg, label, current_id, pkt_count,
836 return (should_abort);
839 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
841 static __checkReturn boolean_t
844 __in efx_qword_t *eqp,
845 __in const efx_ev_callbacks_t *eecp,
848 efx_nic_t *enp = eep->ee_enp;
852 uint32_t eth_tag_class;
855 uint32_t next_read_lbits;
858 boolean_t should_abort;
859 efx_evq_rxq_state_t *eersp;
860 unsigned int desc_count;
861 unsigned int last_used_id;
863 EFX_EV_QSTAT_INCR(eep, EV_RX);
865 /* Discard events after RXQ/TXQ errors */
866 if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
869 /* Basic packet information */
870 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
871 eersp = &eep->ee_rxq_state[label];
873 #if EFSYS_OPT_RX_PACKED_STREAM
875 * Packed stream events are very different,
876 * so handle them separately
878 if (eersp->eers_rx_packed_stream)
879 return (ef10_ev_rx_packed_stream(eep, eqp, eecp, arg));
882 size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
883 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
884 eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
885 mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
886 l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
887 l4_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L4_CLASS);
888 cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
890 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
891 /* Drop this event */
898 * This may be part of a scattered frame, or it may be a
899 * truncated frame if scatter is disabled on this RXQ.
900 * Overlength frames can be received if e.g. a VF is configured
901 * for 1500 MTU but connected to a port set to 9000 MTU
903 * FIXME: There is not yet any driver that supports scatter on
904 * Huntington. Scatter support is required for OSX.
906 flags |= EFX_PKT_CONT;
909 if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
910 flags |= EFX_PKT_UNICAST;
912 /* Increment the count of descriptors read */
913 desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
914 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
915 eersp->eers_rx_read_ptr += desc_count;
918 * FIXME: add error checking to make sure this a batched event.
919 * This could also be an aborted scatter, see Bug36629.
921 if (desc_count > 1) {
922 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
923 flags |= EFX_PKT_PREFIX_LEN;
926 /* Calculate the index of the last descriptor consumed */
927 last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
929 /* Check for errors that invalidate checksum and L3/L4 fields */
930 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECC_ERR) != 0) {
931 /* RX frame truncated (error flag is misnamed) */
932 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
933 flags |= EFX_DISCARD;
936 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
937 /* Bad Ethernet frame CRC */
938 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
939 flags |= EFX_DISCARD;
942 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
944 * Hardware parse failed, due to malformed headers
945 * or headers that are too long for the parser.
946 * Headers and checksums must be validated by the host.
948 /* TODO: EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE); */
952 if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
953 (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
954 flags |= EFX_PKT_VLAN_TAGGED;
958 case ESE_DZ_L3_CLASS_IP4:
959 case ESE_DZ_L3_CLASS_IP4_FRAG:
960 flags |= EFX_PKT_IPV4;
961 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
962 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
964 flags |= EFX_CKSUM_IPV4;
967 if (l4_class == ESE_DZ_L4_CLASS_TCP) {
968 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
969 flags |= EFX_PKT_TCP;
970 } else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
971 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
972 flags |= EFX_PKT_UDP;
974 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
978 case ESE_DZ_L3_CLASS_IP6:
979 case ESE_DZ_L3_CLASS_IP6_FRAG:
980 flags |= EFX_PKT_IPV6;
982 if (l4_class == ESE_DZ_L4_CLASS_TCP) {
983 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
984 flags |= EFX_PKT_TCP;
985 } else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
986 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
987 flags |= EFX_PKT_UDP;
989 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
994 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
998 if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
999 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
1000 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
1002 flags |= EFX_CKSUM_TCPUDP;
1007 /* If we're not discarding the packet then it is ok */
1008 if (~flags & EFX_DISCARD)
1009 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
1011 EFSYS_ASSERT(eecp->eec_rx != NULL);
1012 should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
1014 return (should_abort);
1017 static __checkReturn boolean_t
1019 __in efx_evq_t *eep,
1020 __in efx_qword_t *eqp,
1021 __in const efx_ev_callbacks_t *eecp,
1024 efx_nic_t *enp = eep->ee_enp;
1027 boolean_t should_abort;
1029 EFX_EV_QSTAT_INCR(eep, EV_TX);
1031 /* Discard events after RXQ/TXQ errors */
1032 if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
1035 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
1036 /* Drop this event */
1040 /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
1041 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
1042 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
1044 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
1046 EFSYS_ASSERT(eecp->eec_tx != NULL);
1047 should_abort = eecp->eec_tx(arg, label, id);
1049 return (should_abort);
1052 static __checkReturn boolean_t
1054 __in efx_evq_t *eep,
1055 __in efx_qword_t *eqp,
1056 __in const efx_ev_callbacks_t *eecp,
1060 boolean_t should_abort;
1062 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
1063 should_abort = B_FALSE;
1065 code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
1067 case ESE_DZ_DRV_TIMER_EV: {
1070 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
1072 EFSYS_ASSERT(eecp->eec_timer != NULL);
1073 should_abort = eecp->eec_timer(arg, id);
1077 case ESE_DZ_DRV_WAKE_UP_EV: {
1080 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
1082 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1083 should_abort = eecp->eec_wake_up(arg, id);
1087 case ESE_DZ_DRV_START_UP_EV:
1088 EFSYS_ASSERT(eecp->eec_initialized != NULL);
1089 should_abort = eecp->eec_initialized(arg);
1093 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1094 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1095 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1099 return (should_abort);
1102 static __checkReturn boolean_t
1104 __in efx_evq_t *eep,
1105 __in efx_qword_t *eqp,
1106 __in const efx_ev_callbacks_t *eecp,
1110 boolean_t should_abort;
1112 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1113 should_abort = B_FALSE;
1115 data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
1116 if (data >= ((uint32_t)1 << 16)) {
1117 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1118 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1119 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1124 EFSYS_ASSERT(eecp->eec_software != NULL);
1125 should_abort = eecp->eec_software(arg, (uint16_t)data);
1127 return (should_abort);
1130 static __checkReturn boolean_t
1132 __in efx_evq_t *eep,
1133 __in efx_qword_t *eqp,
1134 __in const efx_ev_callbacks_t *eecp,
1137 efx_nic_t *enp = eep->ee_enp;
1139 boolean_t should_abort = B_FALSE;
1141 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1143 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1145 case MCDI_EVENT_CODE_BADSSERT:
1146 efx_mcdi_ev_death(enp, EINTR);
1149 case MCDI_EVENT_CODE_CMDDONE:
1150 efx_mcdi_ev_cpl(enp,
1151 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1152 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1153 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1156 #if EFSYS_OPT_MCDI_PROXY_AUTH
1157 case MCDI_EVENT_CODE_PROXY_RESPONSE:
1159 * This event notifies a function that an authorization request
1160 * has been processed. If the request was authorized then the
1161 * function can now re-send the original MCDI request.
1162 * See SF-113652-SW "SR-IOV Proxied Network Access Control".
1164 efx_mcdi_ev_proxy_response(enp,
1165 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
1166 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
1168 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
1170 case MCDI_EVENT_CODE_LINKCHANGE: {
1171 efx_link_mode_t link_mode;
1173 ef10_phy_link_ev(enp, eqp, &link_mode);
1174 should_abort = eecp->eec_link_change(arg, link_mode);
1178 case MCDI_EVENT_CODE_SENSOREVT: {
1179 #if EFSYS_OPT_MON_STATS
1181 efx_mon_stat_value_t value;
1184 /* Decode monitor stat for MCDI sensor (if supported) */
1185 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) {
1186 /* Report monitor stat change */
1187 should_abort = eecp->eec_monitor(arg, id, value);
1188 } else if (rc == ENOTSUP) {
1189 should_abort = eecp->eec_exception(arg,
1190 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1191 MCDI_EV_FIELD(eqp, DATA));
1193 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
1199 case MCDI_EVENT_CODE_SCHEDERR:
1200 /* Informational only */
1203 case MCDI_EVENT_CODE_REBOOT:
1204 /* Falcon/Siena only (should not been seen with Huntington). */
1205 efx_mcdi_ev_death(enp, EIO);
1208 case MCDI_EVENT_CODE_MC_REBOOT:
1209 /* MC_REBOOT event is used for Huntington (EF10) and later. */
1210 efx_mcdi_ev_death(enp, EIO);
1213 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1214 #if EFSYS_OPT_MAC_STATS
1215 if (eecp->eec_mac_stats != NULL) {
1216 eecp->eec_mac_stats(arg,
1217 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1222 case MCDI_EVENT_CODE_FWALERT: {
1223 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1225 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1226 should_abort = eecp->eec_exception(arg,
1227 EFX_EXCEPTION_FWALERT_SRAM,
1228 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1230 should_abort = eecp->eec_exception(arg,
1231 EFX_EXCEPTION_UNKNOWN_FWALERT,
1232 MCDI_EV_FIELD(eqp, DATA));
1236 case MCDI_EVENT_CODE_TX_ERR: {
1238 * After a TXQ error is detected, firmware sends a TX_ERR event.
1239 * This may be followed by TX completions (which we discard),
1240 * and then finally by a TX_FLUSH event. Firmware destroys the
1241 * TXQ automatically after sending the TX_FLUSH event.
1243 enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
1245 EFSYS_PROBE2(tx_descq_err,
1246 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1247 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1249 /* Inform the driver that a reset is required. */
1250 eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
1251 MCDI_EV_FIELD(eqp, TX_ERR_DATA));
1255 case MCDI_EVENT_CODE_TX_FLUSH: {
1256 uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
1259 * EF10 firmware sends two TX_FLUSH events: one to the txq's
1260 * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
1261 * We want to wait for all completions, so ignore the events
1262 * with TX_FLUSH_TO_DRIVER.
1264 if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
1265 should_abort = B_FALSE;
1269 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
1271 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
1273 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
1274 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
1278 case MCDI_EVENT_CODE_RX_ERR: {
1280 * After an RXQ error is detected, firmware sends an RX_ERR
1281 * event. This may be followed by RX events (which we discard),
1282 * and then finally by an RX_FLUSH event. Firmware destroys the
1283 * RXQ automatically after sending the RX_FLUSH event.
1285 enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
1287 EFSYS_PROBE2(rx_descq_err,
1288 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1289 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1291 /* Inform the driver that a reset is required. */
1292 eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
1293 MCDI_EV_FIELD(eqp, RX_ERR_DATA));
1297 case MCDI_EVENT_CODE_RX_FLUSH: {
1298 uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
1301 * EF10 firmware sends two RX_FLUSH events: one to the rxq's
1302 * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
1303 * We want to wait for all completions, so ignore the events
1304 * with RX_FLUSH_TO_DRIVER.
1306 if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
1307 should_abort = B_FALSE;
1311 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
1313 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
1315 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
1316 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1321 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1322 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1323 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1327 return (should_abort);
1331 ef10_ev_rxlabel_init(
1332 __in efx_evq_t *eep,
1333 __in efx_rxq_t *erp,
1334 __in unsigned int label,
1335 __in boolean_t packed_stream)
1337 efx_evq_rxq_state_t *eersp;
1339 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1340 eersp = &eep->ee_rxq_state[label];
1342 EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
1344 #if EFSYS_OPT_RX_PACKED_STREAM
1346 * For packed stream modes, the very first event will
1347 * have a new buffer flag set, so it will be incremented,
1348 * yielding the correct pointer. That results in a simpler
1349 * code than trying to detect start-of-the-world condition
1350 * in the event handler.
1352 eersp->eers_rx_read_ptr = packed_stream ? ~0 : 0;
1354 eersp->eers_rx_read_ptr = 0;
1356 eersp->eers_rx_mask = erp->er_mask;
1357 #if EFSYS_OPT_RX_PACKED_STREAM
1358 eersp->eers_rx_stream_npackets = 0;
1359 eersp->eers_rx_packed_stream = packed_stream;
1360 if (packed_stream) {
1361 eersp->eers_rx_packed_stream_credits = (eep->ee_mask + 1) /
1362 (EFX_RX_PACKED_STREAM_MEM_PER_CREDIT /
1363 EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE);
1364 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, !=, 0);
1366 * A single credit is allocated to the queue when it is started.
1367 * It is immediately spent by the first packet which has NEW
1368 * BUFFER flag set, though, but still we shall take into
1369 * account, as to not wrap around the maximum number of credits
1372 eersp->eers_rx_packed_stream_credits--;
1373 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, <=,
1374 EFX_RX_PACKED_STREAM_MAX_CREDITS);
1377 EFSYS_ASSERT(!packed_stream);
1382 ef10_ev_rxlabel_fini(
1383 __in efx_evq_t *eep,
1384 __in unsigned int label)
1386 efx_evq_rxq_state_t *eersp;
1388 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1389 eersp = &eep->ee_rxq_state[label];
1391 EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
1393 eersp->eers_rx_read_ptr = 0;
1394 eersp->eers_rx_mask = 0;
1395 #if EFSYS_OPT_RX_PACKED_STREAM
1396 eersp->eers_rx_stream_npackets = 0;
1397 eersp->eers_rx_packed_stream = B_FALSE;
1398 eersp->eers_rx_packed_stream_credits = 0;
1402 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */